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Master

Affiliation (Master)

  • Research Center for Integrated Quantum Electronics

Affiliation (Master)

  • Research Center for Integrated Quantum Electronics

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Profile and Settings

Affiliation

  • Hokkaido University, Research Center for Integrated Quantum ElectronicsResearch Area for Quantum Integrated Systems

Profile and Settings

  • Name (Japanese)

    Akazawa
  • Name (Kana)

    Masamichi
  • Name

    201201021966719061

Affiliation

  • Hokkaido University, Research Center for Integrated Quantum ElectronicsResearch Area for Quantum Integrated Systems

Achievement

Research Interests

  • GaN   surface passivation   interface   surface   XPS   MOS   Al2O3   InAlN   nitride semiconductor   界面準位   InGaAs   GaAs   MIS   テラヘルツ   InP   デバイス   ヘテロ界面   

Research Areas

  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electric/electronic material engineering
  • Nanotechnology/Materials / Thin-film surfaces and interfaces
  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electronic devices and equipment
  • Nanotechnology/Materials / Crystal engineering
  • Nanotechnology/Materials / Applied materials

Research Experience

  • 1995/04 - Today Hokkaido University Associate Professor
  • 1988/11 - 1995/03 Hokkaido University Research Associate

Education

  • 1988/04 - 1988/10  Hokkaido University  Graduate School of Enigineering  Division of Electrical Engineering
  • 1984/04 - 1988/03  Hokkaido University  Faculty of Enigineering  Department of Electrical Engineering

Committee Memberships

  • 2019/08 - Today   The 14th International Conference on Nitride Semiconductors (ICNS-14)   ICNS-14 Local Arrangement Comittee
  • 2020/09 -2021/11   International Conference on Solid-State Devices and Materials   Secretary of Steering Committee

Awards

  • 2024/03 16th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials / 17th International Conference on Plasma-Nano Technology & Science / 13th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (ISPlasma2024/IC-PLANTS2024/APSPT-13, Nagoya University, Nagoya, Japan, March 3–7, 2024) The Best Poster Presentation Award
     "Effects of SiO2-Cap Annealing Prior to Interface Formation on Properties of Al2O3/p-type GaN Interfaces" 
    受賞者: Yining Jiao;Takahide Nukariya;Umi Takatsu;Taketomo Sato;Masamichi Akazawa
  • 2023/03 15th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials/ 16th International Conference on Plasma-Nano Technology & Science (ISPlasam2023/IC-PLANTS2023, Gifu University, Gifu, Japan, March 5–9, 2023) The Best Poster Presentation Awards
     "Impact of ultra-high-pressure annealing on interface state density distribution near conduction band at Al2O3/Mg-ion-implanted GaN interface" 
    受賞者: Y. Hatakeyama;M. Akazawa;T. Narita;M. Bockowski;T. Kachi
  • 2016/09 JSAP JSAP Paper Award
     "Characterization of electronic states at insulator/(Al)GaN interfaces for improved insulated gate and surface passivation structures of GaN-based transistors" 
    受賞者: Zenji Yatabe;Yujin Hori;Wan-Cheng Ma;Joel T. Asubar;Masamichi Akazawa;Taketomo Sato;Tamotsu Hashizume
  • 2013/05 CSManTech 2013 Paper Awards (He Bong Kim Award)
     "Characterization and Control of Insulated Gate Interfaces" 
    受賞者: Tamotsu Hashizume;Masamichi Akazawa
  • 1998/10 the 5th International Conference on Soft Computing and Information/ Intelligent Systems (IIZUKA '98) Best Paper Award
     "A Functional Neuro-MOS Circuit for Implementing Cellular-Automaton Picture-Processing Devices" 
    受賞者: M. Ikebe;M. Akazawa;Y. Amemiya
  • 1990/08 International Conference on Solid State Devices and Materials SSDM Young Researcher Award
     "In0.53Ga0.47As MISFETs Having an Ultrathin MBE Si Interface Control Layer and Photo-CVD SiO2 Insulator" 
    受賞者: M. Akazawa

Published Papers

  • Yining Jiao, Takahide Nukariya, Umi Takatsu, Tetsuo Narita, Tetsu Kachi, Taketomo Sato, Masamichi Akazawa
    Physica Status Solidi (B) Basic Research Wiley 2400025-1 - 2400025-9 0370-1972 2024/03 [Refereed][Not invited]
     
    The process-dependent properties of Al2O3/p-type GaN (p-GaN) interfaces formed by atomic layer deposition at 300 °C after photoelectrochemical (PEC) etching are reported. For investigating the gap states at the Al2O3/p-GaN interface, metal-oxide-semiconductor (MOS) diodes are fabricated and examined by sub-bandgap-light-assisted and temperature-dependent capacitance–voltage (C–V) measurements. PEC etching prior to Al2O3/p-GaN interface formation is conducted with the etching depth varied in the range between 12.5 and 32.1 nm. The C–V characteristics of the MOS diodes without PEC etching indicate Fermi-level pinning due to the near-surface defect level in p-GaN at 0.7 eV above the valence band edge EV and a high density of gap states around the midgap. However, all samples with PEC etching exhibit C–V characteristics, indicating a reduction in the density of the defect states at EV + 0.7 eV and midgap states. Still, PEC etching after capless annealing at 800 °C for the activation of Mg acceptors cannot reduce the density of gap states near the valence band edge. On the other hand, annealing of a sample with a SiO2 cap layer at 800 °C after PEC etching can reduce the gap state density near the valence band edge.
  • Yuliu Luo, Yuki Hatakeyama, Masamichi Akazawa
    Japanese Journal of Applied Physics IOP 62 (12) 126501-1 - 126501-6 2023/10 [Refereed][Not invited]
  • Ryota Ochi, Takuya Togashi, Yoshito Osawa, Fumimasa Horikiri, Hajime Fujikura, Kazunari Fujikawa, Takashi Furuya, Ryota Isono, Masamichi Akazawa, Taketomo Sato
    Applied Physics Express IOP 16 (9) 091002-1 - 091002-2 2023/09 [Refereed][Not invited]
  • Y. Hatakeyama, T. Narita, M. Bockowski, T. Kachi, M. Akazawa
    Jpn. J. Appl. Phys. IOP 62 (SN) SN1002-1 - SN1002-7 2023/07 [Refereed]
  • Yuki Hatakeyama, Masamichi Akazawa
    AIP Advances AIP Publishing 12 (12) 125224-1 - 125224-7 2022/12/01 [Refereed][Not invited]
     
    An interface state density ( D it) distribution near the conduction band edge ( E C) at the Al2O3/Mg-ion-implanted GaN interface was measured after ion implantation, annealing with an AlN protective cap, and cap layer removal. Mg ions were implanted into n-GaN with a Si concentration of 6 × 1017 cm−3 at a maximum Mg concentration of 2 × 1017 cm−3, resulting in the maintenance of the n-type conduction in GaN even after the activation of Mg dopants. Activation annealing was carried out at 1250 °C for 1 min using an AlN cap layer. The complete removal of the AlN cap layer was accomplished by wet etching, which was confirmed by x-ray photoelectron spectroscopy. The photoluminescence spectrum showed donor–acceptor-pair emission after annealing, indicating the activation of Mg acceptors. By applying the capacitance–voltage method to a completed metal–oxide–semiconductor diode, we derived a continuous distribution of relatively low D it below 5 × 1012 cm−2 eV−1, which increased monotonically toward E C in the range from E C − 0.15 to E C − 0.45 eV. Compared with the D it distribution of the as-implanted sample, the density of the discrete level at E C − 0.25 eV generated by divacancies markedly decreased upon 1250 °C annealing.
  • Masamichi Akazawa, Yuya Tamamura, Takahide Nukariya, Kouta Kubo, Taketomo Sato, Tetsuo Narita, Tetsu Kachi
    Journal of Applied Physics 132 (19) 195302-1 - 195302-10 2022/11/16 [Refereed][Not invited]
  • Masamichi Akazawa, Shunta Murai, Tetsu Kachi
    Journal of Electronic Materials Springer Science and Business Media LLC 51 (4) 1731 - 1739 0361-5235 2022/03 [Refereed][Not invited]
  • Masamichi Akazawa, Yuya Kitawaki
    AIP Advances 11 (8) 085020-1 - 085020-5 2021/08/01 [Refereed][Not invited]
  • Masamichi Akazawa, Encheng Wu, Hideki Sakurai, Michal Bockowski, Tetsuo Narita, Tetsu Kachi
    Japanese Journal of Applied Physics 60 (3) 036503-1 - 036503-8 0021-4922 2021/03/01 [Refereed][Not invited]
  • Erratum: Impact of surface treatment on metal-work-function dependence of barrier height of GaN-on-GaN Schottky barrier diode (AIP Advances (2018) 8 (115011) DOI: 10.1063/1.5057401)
    Kazuki Isobe, Masamichi Akazawa
    AIP Advances 11 (2) 2158-3226 2021/02/01 
    There was a typo in Eq. (1) of the original paper.1 The correct form of the equation is (Equation Presented) This typo does not affect the results in this paper.
  • Kazuki Isobe, Masamichi Akazawa
    Japanese Journal of Applied Physics 60 (1) 1347-4065 2021/01/01 
    There was a typo in Eq. (5). The correct form of this equation is (Formula Presented) This typo does not affect the results in this paper.
  • Masamichi Akazawa, Ryo Kamoshida, Shunta Murai, Tetsu Kachi, Akira Uedono
    Japanese Journal of Applied Physics 60 (1) 016502-1 - 016502-8 0021-4922 2021/01/01 [Refereed][Not invited]
  • Masamichi Akazawa, Ryo Kamoshida
    Japanese Journal of Applied Physics 59 (9) 096502 - 096502 0021-4922 2020/09/01 [Refereed][Not invited]
  • Kazuki Isobe, Masamichi Akazawa
    Japanese Journal of Applied Physics 59 (4) 046506 - 046506 0021-4922 2020/04/01 [Refereed][Not invited]
  • Masamichi Akazawa, Ryo Kamoshida, Shunta Murai, Tetsuo Narita, Masato Omori, Jun Suda, Tetsu Kachi
    physica status solidi (b) 257 (2) 1900367 - 1900367 0370-1972 2020/02 [Refereed][Not invited]
  • M. Akazawa, S. Kitajima, Y. Kitawaki
    Jpn. J. Appl. Phys. 58 (10) 106504-1 - 106504-7 2019/10 [Refereed][Not invited]
  • Masamichi Akazawa, Shouhei Kitajima
    Jpn. J. Appl. Phys. 58 (SI) SIIB06-1 - SIIB06-8 2019/08 [Refereed][Not invited]
  • Masamichi Akazawa, Kei Uetake
    Jpn. J. Appl. Phys. 58 (SC) SCCB10-1 - SCCB10-6 2019/06 [Refereed][Not invited]
  • Kazuki Isobe, Masamichi Akazawa
    AIP Advances 8 (11) 115011-1 - 115011--6 2018/11 [Refereed][Not invited]
  • Masamichi Akazawa, Taito Hasezaki
    Physica Status Solidi (B) Basic Research 255 (5) 1700382- 1 - 1700382- 6 1521-3951 2018/05/01 [Refereed][Not invited]
     
    Fermi level depinning at a metal/semiconductor interface by using an ultrathin insulating interlayer to block the penetration of the metal wave function into the semiconductor is examined on GaN. A Si-doped n-type GaN epitaxial layer on a freestanding GaN substrate is used as the host material. For the samples with an interlayer, an ultrathin Al2O3 layer of 1 nm thickness is deposited by atomic layer deposition. As the metal layers, Ag, Cu, Au, Ni, and Pt are deposited by electron beam evaporation. Samples without an interlayer are also fabricated for comparison. The apparent change in current–voltage characteristics of the Schottky barrier diodes with the insertion of the interlayer is dependent on the electrode metal. However, the apparent Schottky barrier height (SBH) for the samples with the interlayer is almost constant and independent of the metal electrode, although the samples without an interlayer exhibit a moderate dependence of the SBH on the metal work function. Thus, the pinning becomes stronger upon the insertion of the interlayer, although blocking of the metal wave function by using an ultrathin insulator is expected to lead to depinning.
  • Masamichi Akazawa, Naoshige Yokota, Kei Uetake
    AIP Advances 8 (2) 025310-1 - 025310-7 2158-3226 2018/02/01 [Refereed][Not invited]
     
    We report experimental results for the detection of deep-level defects in GaN after Mg ion implantation before higherature annealing. The n-type GaN samples were grown on GaN free-standing substrates by metalorganic vapor phase epitaxy. Mg ions were implanted at 50 keV with a small dosage of 1.5×1011 cm-2, which did not change the conduction type of the n-GaN. By depositing Al2O3 and a Ni/Au electrode onto the implanted n-GaN, metal-oxide-semiconductor (MOS) diodes were fabricated and tested. The measured capacitance-voltage (C-V) characteristics showed a particular behavior with a plateau region and a region with an anomalously steep slope. Fitting to the experimental C-V curves by simulation showed the existence of deep-level defects and a reduction of the carrier concentration near the GaN surface. By annealing at 800oC, the density of the deep-level defects was reduced and the carrier concentration partially recovered.
  • Masamichi Akazawa, Atsushi Seino
    PHYSICA STATUS SOLIDI B-BASIC SOLID STATE PHYSICS 254 (8) 1600691-1 - 1600691-6 0370-1972 2017/08 [Refereed][Not invited]
     
    SiO2/InAlN interfaces formed by plasma-enhanced chemical vapor deposition were investigated. X-ray photoelectron spectroscopy showed that the direct deposition of SiO2 onto an InAlN surface led to the oxidation of the InAlN surface. The interface state density, D-it, was on the order of 10(12) cm(-2) eV(-1) (5 x 10(12) cm(-2) eV(-1) at 0.3 eV from the conduction band edge, E-c), which indicated the possibility of improving the interface properties. Reduction of the interface state density was attempted using an Al2O3 interlayer and a plasma oxide interlayer. The insertion of a 2-nm-thick Al2O3 interlayer to prevent surface oxidation by plasma reduced D-it slightly. A marked reduction in D-it to less than 10(11) cm(-2) eV(-1) deeper than 0.3 eV from E-c, however, was achieved by the intentional formation of a 1-nm-thick plasma oxide layer, formed by N2O plasma oxidation, as an interlayer between SiO2 and InAlN. (C) 2017 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • M. Matys, B. Adamowicz, A. Domanowska, A. Michalewicz, R. Stoklas, M. Akazawa, Z. Yatabe, T. Hashizume
    JOURNAL OF APPLIED PHYSICS 120 (22) 225305-1 - 225305-12 0021-8979 2016/12 [Refereed][Not invited]
     
    The energy spectrum of interface state density, D-it(E), was determined at oxide/III-N heterojunction interfaces in the entire band gap, using two complementary photo-electric methods: (i) photo-assisted capacitance-voltage technique for the states distributed near the midgap and the conduction band (CB) and (ii) light intensity dependent photo-capacitance method for the states close to the valence band (VB). In addition, the Auger electron spectroscopy profiling was applied for the characterization of chemical composition of the interface region with the emphasis on carbon impurities, which can be responsible for the interface state creation. The studies were performed for the AlGaN/GaN metal-insulator-semiconductor heterostructures (MISH) with Al2O3 and SiO2 dielectric films and AlxGa1-x layers with x varying from 0.15 to 0.4 as well as for an Al2O3/InAlN/GaN MISH structure. For all structures, it was found that: (i) D-it(E) is an U-shaped continuum increasing from the midgap towards the CB and VB edges and (ii) interface states near the VB exhibit donor-like character. Furthermore, D-it(E) for SiO2/AlxGa1-x/GaN structures increased with rising x. It was also revealed that carbon impurities are not present in the oxide/III-N interface region, which indicates that probably the interface states are not related to carbon, as previously reported. Finally, it was proven that the obtained D-it(E) spectrum can be well fitted using a formula predicted by the disorder induced gap state model. This is an indication that the interface states at oxide/III-N interfaces can originate from the structural disorder of the interfacial region. Furthermore, at the oxide/barrier interface we revealed the presence of the positive fixed charge (Q(F)) which is not related to D-it(E) and which almost compensates the negative polarization charge (Q(pol)(-)). Published by AIP Publishing.
  • Taketomo Sato, Yusuke Kumazaki, Masaaki Edamoto, Masamichi Akazawa, Tamotsu Hashizume
    GALLIUM NITRIDE MATERIALS AND DEVICES XI 9748 97480Y-1 - 97480Y-7 0277-786X 2016 [Refereed][Not invited]
     
    The selective and low-damaged etching of p-type GaN or AlGaN layer is inevitable process for AlGaN/GaN high-power transistors. We have investigated an electrochemical etching of p-GaN layer grown on AlGaN/GaN heterostructures, consisting of an anodic oxidation of p-GaN surface and a subsequent dissolution of the resulting oxide. The p- GaN layer was electrochemically etched by following the pattern of the SiO2 film that acted as an etching mask. Etching depth was linearly controlled by cycle number of triangular waveform at a rate of 25 nm/cycle. The AFM, TEM and mu-AES results showed that the top p- GaN layer was completely removed after 5 cycles applied, and the etching reaction was automatically sopped on the AlGaN surface. I-V and C-V measurements revealed that no significant damages were induced in the AlGaN/GaN heterostructures.
  • Zenji Yatabe, Yujin Hori, Wan-Cheng Ma, Joel T. Asubar, Masamichi Akazawa, Taketomo Sato, Tamotsu Hashizume
    Japanese Journal of Applied Physics 53 (10) 100213-1 - 10 1347-4065 2014/10/01 [Refereed][Not invited]
     
    This paper presents a systematic characterization of electronic states at insulators/(Al)GaN interfaces, particularly focusing on insulator/AlGaN/GaN structures. First, we review important results reported for GaN metal-insulator-semiconductor (MIS) structures. SiO2 is an attractive material for MIS transistor applications due to its large bandgap and high chemical stability. In-situ SiNx is effective for improving the operation stability of high electron mobility transistors (HEMTs). Meanwhile, Al2O3/GaN structures have high band offsets and low interface state densities, which are also desirable for insulated gate applications. We have proposed a calculation method for describing capacitance-voltage (C-V) characteristics of HEMT MIS structures for evaluating electronic state properties at the insulator/AlGaN interfaces. To evaluate near-midgap states at insulator/AlGaN interfaces, a photo-assisted C-V technique using photon energies less than the bandgap of GaN has been developed. Using the calculation in conjunction with the photo-assisted C-V technique, we estimate interface state density distributions at the Al2O3/AlGaN interfaces.
  • rocess-dependent properties of InAlN surface and ALD-Al2O3/InAlN interface
    M. Akazawa, M. Chiba, T. Nakano
    Extended Abstracts of 2014 International Conference on Compound Semiconductor Manufacturing Technology (CSMANTECH 2014, Sheraton Downtown Denver, Denver, Colorado, USA, May 19-22, 2014) 313 - 316 2014/05 [Not refereed][Not invited]
  • Takuma Nakano, Masahito Chiba, Masamichi Akazawa
    JAPANESE JOURNAL OF APPLIED PHYSICS 53 (4) 04EF06-1 - 04EF06-5 0021-4922 2014/04 [Refereed][Not invited]
     
    An attempt was made to control the Al2O3/InAlN interface by the phase change of the Al2O3 layer formed by atomic layer deposition (ALD). The electrical properties of an InAlN metal-oxide-semiconductor (MOS) diode with a sufficiently thick ALD-Al2O3 layer deteriorated following conventional postdeposition annealing (PDA) at 850 degrees C, which is sufficiently high for microcrystallization of the ALD-Al2O3 layer. However, X-ray photoelectron spectroscopy showed no evidence of an interface disorder in the ultrathin ALD-Al2O3/InAlN structure annealed at 850 degrees C. Two-step ALD interrupted by annealing at 850 degrees C right after the formation of the initial ultrathin Al2O3 layer improved the electrical properties of the MOS diode with reduced interface state density (D-it) and leakage current. A weak crystallization of the ultrathin Al2O3 layer was confirmed by transmission electron microscopy. Improvement of the interface disorder by high-temperature annealing is discussed as the origin of the D-it reduction. (C) 2014 The Japan Society of Applied Physics
  • Masamichi Akazawa, Takuma Nakano
    e-Journal of Surface Science and Nanotechnology 12 83 - 88 1348-0391 2014/03/01 [Refereed][Not invited]
     
    The effects of high-temperature annealing on the properties of an Al 2O3/InAlN interface formed by atomic layer deposition (ALD) is investigated by X-ray photoelectron spectroscopy (XPS). The interface between 2-nm-thick ALD Al2O3 and InAlN were annealed in N2 at 800, 850, or 950°C. The shapes of the In 3d, In 4d, N 1s, and Al 2p core-level spectra were not changed by annealing, which indicated that significant intermixing was not induced at the Al2O 3/InAlN interface by annealing at high temperatures of up to 950°C. The O 1s spectra consisted of two components for all samples. The higher-energy component in the O 1s spectra, which was reduced in intensity but not removed by annealing, was revealed to be localized at the Al 2O3 surface. The Fermi level position at the InAlN surface was also investigated but no change was observed upon annealing at all temperatures. By also considering results of the electrical measurement, the absence of Fermi level pinning at the Al2O3/InAlN interface is discussed. © 2014 The Surface Science Society of Japan.
  • Masamichi Akazawa
    JAPANESE JOURNAL OF APPLIED PHYSICS 53 (2) 0021-4922 2014/02 [Refereed][Not invited]
     
    The midgap interface state density of the Al2O3/In0.19Al0.81N interface formed by atomic layer deposition was investigated by photoassisted capacitance-voltage (C-V) measurement. The interface-state density was derived to be in the range of 10(12)eV(-1)cm(-2) around the midgap. The hysteresis of the C-V curve increased as the irradiated photon energy increased beyond the threshold value of 1.8 eV. This threshold energy value coincided with the energy difference between the conduction band edge and the charge neutrality level E-CNL. for In0.19Al0.81N, which indicated the density of interface states at around E-CNL to be below the detection limit. (C) 2014 The Japan Society of Applied Physics
  • Masahito Chiba, Takuma Nakano, Masamichi Akazawa
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 11, NO 3-4 11 (3-4) 902 - 905 1862-6351 2014 [Refereed][Not invited]
     
    The fabrication-procedure dependence of the electrical properties of the InAlN metal-oxide-semiconductor (MOS) structure with Al2O3 formed by atomic layer deposition (ALD) was investigated. When the ALD Al2O3/InAlN interface was formed after ohmic-contact annealing in nitrogen without the use of a cap layer, the electrical characteristics were poor with a small capacitance change in the capacitance-voltage (C-V) curve. Xray photoelectron spectroscopy (XPS) study indicated that the bare InAlN surface was oxidized during capless annealing presumably owing to the trace contamination in the furnace. High-temperature ohmic-contact annealing after Al2O3/InAlN interface formation, using the Al2O3 layer as a cap layer for surface protection, did not improve the interface properties, resulting in the interface state density Dit in the range of 10(13) cm(-2)eV(-1); this was highly likely related to the crystallization of Al2O3. When a SiNx layer was used as the cap layer during ohmiccontact annealing prior to ALD, greatly improved characteristics of the MOS diode were achieved, indicating that Dit was suppressed to be in the range of 10(12) cm(-2)eV(-1) near the conduction band. The obtained results indicate that an appropriate fabrication procedure leads to an improvement of the Al2O3/InAlN interface properties. (C) 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • Effects of High-Temperature Annealing on Properties of Al2O3/InAlN Interface Formed by Atomic Layer Deposition
    T. Nakano, M. Chiba, M. Akazawa
    Extended Abstracts of 2013 International Conference on Solid State Devices and Materials (SSDM2013, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, Sept. 25-27, 2013) PS-6-3-1 - PS-6-3-2 2013/09 [Refereed][Not invited]
  • Masamichi Akazawa, Takuma Nakano
    JAPANESE JOURNAL OF APPLIED PHYSICS 52 (8) 08JN23-1 - 08JN23-3 0021-4922 2013/08 [Refereed][Not invited]
     
    The effects of chemical treatments and Al2O3 deposition on the InAlN surface were investigated by X-ray photoelectron spectroscopy (XPS). Independent of the extent of native oxide removal, the In 4d core-level binding energy was the same for untreated, HCl-treated, and HF-treated InAlN. This indicated a strong pinning tendency of the Fermi level at the InAlN bare surface. However, a 300 meV decrease in the In 4d binding energy was observed after atomic layer deposition (ALD) of Al2O3, which indicated an increase in the negative surface potential at the InAlN surface. The reduction of positive charge at the InAlN surface is discussed. (c) 2013 The Japan Society of Applied Physics
  • Masamichi Akazawa, Masahito Chiba, Takuma Nakano
    Applied Physics Letters 102 (23) 231605-1 - 231605-3 0003-6951 2013/06/10 [Refereed][Not invited]
     
    The Al2O3/InAlN interface formed by atomic layer deposition on a sufficiently thick silicon-doped InAlN layer lattice matched to GaN was investigated electrically. A metal-oxide-semiconductor (MOS) diode fabricated through careful interface formation showed a minimized leakage current and a capacitance-voltage (C-V) characteristic with a capacitance change large enough to evaluate the interface-state density, in the range of 10 12 eV-1cm-2, near the conduction band. However, the MOS diode with careless interface formation resulted in degraded electrical characteristics, which indicated the process dependence of the interface properties. The effects of the acceptor-like interface states on the C-V curves are discussed. © 2013 AIP Publishing LLC.
  • Takuma Nakano, Masamichi Akazawa
    IEICE TRANSACTIONS ON ELECTRONICS E96C (5) 686 - 689 1745-1353 2013/05 [Refereed][Not invited]
     
    We investigated the effects of chemical treatments for removing native oxide layers on InAlN surfaces by X-ray photoelectron spectroscopy (XPS). The untreated surface of the air exposed InAlN layer was covered with the native oxide layer mainly composed of hydroxides. Hydrochloric acid treatment and ammonium hydroxide treatment were not efficient for removing the native oxide layer even after immersion for 15 min, while hydrofluoric acid (HF) treatment led to a removal in a short treatment time of 1 min. After the HF treatment, the surface was prevented from reoxidation in air for 1 h. We also found that the 5-min buffered HE treatment had almost the same effect as the 1-min HF treatment. Finally, an attempt was made to apply the HF-based treatment to the metal-InAlN contact to confirm the XPS results.
  • Characterization and control of insulated gate interfaces on GaN-based heterostructures
    Tamotsu Hashizume, Masamichi Akazawa
    2013 International Conference on Compound Semiconductor Manufacturing Technology, CS MANTECH 2013 329 - 332 2013 
    We observed the peculiar capacitance-voltage (C-V) characteristics with two capacitance steps in the Al2O3/ AlGaN/GaN structure prepared by atomic layer deposition. The detailed potential analysis showed that interface states near midgap or deeper in energies act as "fixed and frozen" charges at room temperature. From the voltage shift at the reverse bias in the photo-assisted C-V curve, we estimated the interface state density distribution at the Al2O3 /AlGaN interface for the first time.
  • M. Akazawa, T. Nakano
    APPLIED PHYSICS LETTERS 101 (12) 122110-122110-4  0003-6951 2012/09 [Refereed][Not invited]
     
    The valence band offset, Delta E-V, at an Al2O3/In0.17Al0.83N interface formed by atomic layer deposition was measured by x-ray photoelectron spectroscopy. The conventional method of using the core level separation, Delta E-CL, between O 1s and In 4d resulted in Delta E-V = 1.3 eV, which was apparently consistent with the direct observation of the valence band edge varying the photoelectron exit angle, theta. However, Delta E-CL and full width at half maximum of core-level spectra were dependent on theta, which indicated significant potential gradients in Al2O3 and InAlN layers. An actual Delta E-V of 1.2 eV was obtained considering the potential gradients. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4754141]
  • 橋詰 保, 堀 祐臣, 赤澤 正道
    電子情報通信学会技術研究報告 : 信学技報 電子情報通信学会 112 (154) 17 - 20 0913-5685 2012/07 [Not refereed][Invited]
  • Effect of hydrofluoric acid treatment on InAlN surfaces
    T. Nakano, M. Akazawa
    Workshop Digest of 2012 Asia-Pacific Workshop on Fundamental and Applications of Advanced Semiconductor Devices (AWAD2012, Naha, Okinawa, Japan, June 27-29, 2012) 242 - 246 2012/06 [Refereed][Not invited]
  • M. Akazawa, B. Gao, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 9, NO 3-4 9 (3-4) 592 - 595 1862-6351 2012 [Refereed][Not invited]
     
    AlGaN-based spacer layers for lattice-matched and nearly lattice matched InAlN/GaN interfaces were examined in Al2O3/InAlN/AlGaN/AlN/GaN structures. An Al2O3 overlayer was deposited to investigate the characteristics under positive bias by capacitance-voltage (C-V) measurement. The C-V characteristic for a sample with an Al0.38Ga0.62N/AlN double spacer layer indicated unfavorable electron accumulation at the InAlN/AlGaN interface inside the barrier under positive bias. To suppress the unfavorable accumulation, attempts were made to increase the Al molar fraction of the AlGaN layer to reduce the conduction band discontinuity and interface charge at InAlN/AlGaN interface. An Al0.44Ga0.56N/AlN double spacer layer and an Al0.44Ga0.56N single spacer layer of almost the same total thickness were investigated. Although both spacer layers result in normal C-V characteristics without the indication of unfavorable electron accumulation, the InAlN layer on a 1.5-nm-thick Al0.44Ga0.56N single spacer layer exhibited superior surface morphology without deteriorating the mobility of the two-dimensional electron gas despite the absence of the AlN layer. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • M. Akazawa, T. Nakano
    ECS SOLID STATE LETTERS 1 (1) P4 - P6 2162-8742 2012 [Refereed][Not invited]
     
    The characteristics of native oxide layers on untreated and chemically treated InAlN surfaces were investigated by X-ray photoelectron spectroscopy (XPS). Ammonia (NH4OH), hydrochloric acid (HCl), and hydrofluoric acid (HF) were used for chemical treatment. The native oxide layer on an untreated InAlN surface was found to mainly consist of hydroxide components. These hydroxides were completely removed by HF treatment, whereas the other treatments resulted in incomplete removal. NH4OH treatment increased the intensity of the In-related hydroxide component, indicating that oxidation had occurred. This was confirmed by successive NH4OH/HF treatments applied to an ultrathin InAlN layer, which resulted in etching. (C) 2012 The Electrochemical Society. All rights reserved.
  • M. Akazawa, B. Gao, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    APPLIED PHYSICS LETTERS 98 (14) 142117  0003-6951 2011/04 [Refereed][Not invited]
     
    The barrier structure in lattice-matched InAlN/GaN heterostructures with AlGaN-based spacer layers grown by metal organic vapor phase epitaxy was studied by the capacitance-voltage (C-V) method. To investigate the characteristics under positive bias, an Al2O3 overlayer was added. The C-V characteristic of a sample with an Al0.38Ga0.62N (5 nm)/AlN (0.75 nm) double spacer layer exhibited an anomalous saturation at a value far below the insulator capacitance under positive bias, which indicated electron accumulation at the InAlN/AlGaN interface. The C-V characteristic of an alternative sample with a single Al0.44Ga0.56N (1.5 nm) spacer layer did not exhibit the anomalous saturation. (C) 2011 American Institute of Physics. [doi:10.1063/1.3578449]
  • M. Akazawa, B. Gao, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 8, NO 7-8 8 (7-8) 2139 - 2141 1862-6351 2011 [Refereed][Not invited]
     
    The polarization-induced electric field in ultrathin InxAl(1-x)N (0.17 <= x <= 0.30) layers on GaN was investigated by using X-ray photoelectron spectroscopy (XPS). The core-level energy position, E-CL, and the full width at half maximum (FWHM) of the Al2p, In4d, and In3d spectra from 2.5-nm-thick InAlN layers increased with the increase in the photoelectron exit angle (elevation angle). These increases were well reproduced with numerical calculations assuming polarization-induced internal fields combined with surface Fermi level pinning. The magnitudes of the internal field decreased as the In molar fraction increased. The Ga3d spectra from the host GaN layers markedly shifted by 530 meV depending on the molar fraction of InAlN layers, which was independent of the exit angle. This indicated that the Fermi level was unpinned at the interfaces, or GaN surfaces, and shifted due to the potential drop in the InAlN layers. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • M. Akazawa, B. Gao, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    JOURNAL OF APPLIED PHYSICS 109 (1) 013703  0021-8979 2011/01 [Refereed][Not invited]
     
    The valence band offsets, Delta E-V, of In0.17Al0.83N/GaN, In0.25Al0.75N/GaN, and In0.30Al0.70N/GaN heterostructures grown by metal-organic vapor phase epitaxy were evaluated by using x-ray photoelectron spectroscopy (XPS). The dependence of the energy position and the full width at half maximum of the Al 2p spectrum on the exit angle indicated that there was sharp band bending caused by the polarization-induced electric field combined with surface Fermi-level pinning in each ultrathin InAlN layer. The Delta E-V values evaluated without taking into account band bending indicated large discrepancies from the theoretical estimates for all samples. Erroneous results due to band bending were corrected by applying numerical calculations, which led to acceptable results. The evaluated Delta E-V values were 0.2 +/- 0.2 eV for In0.17Al0.83N/GaN, 0.1 +/- 0.2 eV for In0.25Al0.75N/GaN, and 0.0 +/- 0.2 eV for In0.30Al0.70N/GaN. Despite the large decrease of around 1.0 eV in the band gap of InAlN layers according to the increase in the In molar fraction, the decrease in Delta E-V was as small as 0.2 eV. Therefore, the change in band-gap discontinuity was mainly distributed to that in conduction band offset. (C) 2011 American Institute of Physics. [doi: 10.1063/1.3527058]
  • H. Hasegawa, M. Akazawa, A. Domanowska, B. Adamowicz
    APPLIED SURFACE SCIENCE 256 (19) 5698 - 5707 0169-4332 2010/07 [Refereed][Not invited]
     
    Currently, III-V metal-insulator-semiconductor field effect transistors (MISFETs) are considered to be promising device candidates for the so-called "More Moore Approach" to continue scaling CMOS transistors on the silicon platform. Strong interest also exists in III-V nanowire MISFETs as a possible candidate for a "Beyond CMOS"-type device. III-V sensors using insulator-semiconductor interfaces are good candidates for "More Moore"-type of devices on the Si platform. The success of these new approaches for future electronics depends on the availability of a surface passivation technology which can realize pinning-free, high-quality interfaces between insulator and III-V semiconductors. This paper reviews the past history, present status and key issues of the research on the surface passivation technology for III-V semiconductors. First, a brief survey of previous research on surface passivation and MISFETs is made, and Fermi level pinning at insulator-semiconductor interface is discussed. Then, a brief review is made on recent approaches of interface control for high-k III-V MIS structures. Subsequently, as an actual example of interface control, latest results on the authors' surface passivation approach using a silicon interface control layer (Si ICL) are discussed. Finally, a photoluminescence (PL) method to characterize the interface quality is presented as an efficient contactless and non-destructive method which can be applied at each step of interface formation process without fabrication of MIS capacitors and MISFETs. (C) 2010 Elsevier B.V. All rights reserved.
  • M. Akazawa, H. Hasegawa
    APPLIED SURFACE SCIENCE 256 (19) 5708 - 5713 0169-4332 2010/07 [Refereed][Not invited]
     
    This paper attempts to realize unpinned high-k insulator-semiconductor interfaces on air-exposed GaAs and In0.53Ga0.47As by using the Si interface control layer (Si ICL). Al2O3 was deposited by ex situ atomic layer deposition (ALD) as the high-k insulator. By applying an optimal chemical treatment using HF acid combined with subsequent thermal cleaning below 500 degrees C in UHV, interface bonding configurations similar to those by in situ UHV process were achieved both for GaAs and InGaAs after MBE growth of the Si ICL with no trace of residual native oxide components. As compared with the MIS structures without Si ICL, insertion of Si ICL improved the electrical interface quality, a great deal both for GaAs and InGaAs, reducing frequency dispersion of capacitance, hysteresis effects and interface state density (D-it). A minimum value of D-it of 2 x 10(11) eV(-1) cm(-2) was achieved both for GaAs and InGaAs. However, the range of bias-induced surface potential excursion within the band gap was different, making formation of electron layer by surface inversion possible in InGaAs, but not possible in GaAs. The difference was explained by the disorder induced gap state (DIGS) model. (C) 2010 Elsevier B. V. All rights reserved.
  • M. Akazawa, T. Matsuyama, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    APPLIED PHYSICS LETTERS 96 (13) 132104  0003-6951 2010/03 [Refereed][Not invited]
     
    The valence-band offset of a lattice-matched In0.17Al0.83N/GaN heterostructure grown by metal-organic vapor phase epitaxy (MOVPE) was investigated by x-ray photoelectron spectroscopy (XPS). Atomic force microscopy and angle-resolved XPS indicated that a thin In0.17Al0.83N (2.5 nm) layer was successfully grown by MOVPE on GaN. The XPS result showed that the valence band offset was 0.2 +/- 0.3 eV. This result indicates that the conduction-band offset at the In0.17Al0.83N/GaN interface is large, i.e., 0.9 to 1.0 eV, and occupies a large part of the entire band discontinuity.
  • Masamichi Akazawa, H. Hasegawa
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 7, NO 2 7 (2) 351 - 354 1862-6351 2010 [Refereed][Not invited]
     
    This paper attempts to control the interface between the air-exposed InGaAs wafer and a high-k dielectric by the Si interface control layer (ICL) technique. As the high-k insulator, HfO2 film was formed by atomic layer deposition (ALD). Prior to a molecular beam epitaxy (MBE) growth of the Si ICL, efforts were made to minimize native oxide components from the InGaAs surface by various wet surface treatment. After the growth of the Si ICL, an ultrathin SiNx layer was formed by in-situ partial nitridation of the Si ICL to prevent a subcutaneous oxidation during the sample transfer in air to the ALD chamber. Surface/interface properties were characterized by in-situ X-ray photoelectron spectroscopy (XPS) at each step of interface formation. By using HF-based cleaning, interface bonding configurations similar to those obtained by in-situ UHV process was realized with no trace of native oxide components. As compared with the ALD HfO2/InGaAs metal-insulator-semiconductor (MIS) structure which showed existence of strong Fermi level pinning, insertion of the Si ICL achieved large reduction of interface state density, D-it, giving a minimum value of 2x10(11) eV(-1)cm(-2). (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • Masamichi Akazawa, H. Hasegawa
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 7, NO 2 7 (2) 351 - 354 1862-6351 2010 [Refereed][Not invited]
     
    This paper attempts to control the interface between the air-exposed InGaAs wafer and a high-k dielectric by the Si interface control layer (ICL) technique. As the high-k insulator, HfO2 film was formed by atomic layer deposition (ALD). Prior to a molecular beam epitaxy (MBE) growth of the Si ICL, efforts were made to minimize native oxide components from the InGaAs surface by various wet surface treatment. After the growth of the Si ICL, an ultrathin SiNx layer was formed by in-situ partial nitridation of the Si ICL to prevent a subcutaneous oxidation during the sample transfer in air to the ALD chamber. Surface/interface properties were characterized by in-situ X-ray photoelectron spectroscopy (XPS) at each step of interface formation. By using HF-based cleaning, interface bonding configurations similar to those obtained by in-situ UHV process was realized with no trace of native oxide components. As compared with the ALD HfO2/InGaAs metal-insulator-semiconductor (MIS) structure which showed existence of strong Fermi level pinning, insertion of the Si ICL achieved large reduction of interface state density, D-it, giving a minimum value of 2x10(11) eV(-1)cm(-2). (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • Masamichi Akazawa, Hideki Hasegawa
    MATERIALS SCIENCE AND ENGINEERING B-ADVANCED FUNCTIONAL SOLID-STATE MATERIALS 165 (1-2) 122 - 125 0921-5107 2009/11 [Refereed][Not invited]
     
    This paper reports on a GaAs high-k MIS structure having an MBE-grown Si interface control layer (ICL) which has recently shown a promising result. It has a HfO(2)/SiN(x)/Si ICL/GaAs structure where an ultrathin SiN(x) buffer layer is produced by direct nitridation of Si ICL In this study, a particular attention is paid to optimize the initial thickness of Si ICL by correlating the interface structure studied by in situ X-ray photoelectron spectroscopy with the electronic interface quality studied by capacitance-voltage measurements. It was found that the presence of ML-level Si ICL at the interface after the formation of the SiN(x) is vitally important to obtain low values of interface trap density (D(it)). Excess initial thickness of Si ICL also resulted in increase of D(it). Initial Si ICL thicknesses of 5-6 MLs were found to be optimum, and gave U-shaped D(it) distributions with minimum D(it) values around 1 x 10(11) cm(-2) eV(-1) or below. (C) 2009 Elsevier B.V. All rights reserved.
  • Hideki Hasegawa, Masamichi Akazawa
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY 55 (3) 1167 - 1179 0374-4884 2009/09 [Refereed][Not invited]
     
    The current transport, Fermi level pinning and transient behavior of Group-III nitride Schottky barriers are reviewed. First, an overview of interface models is given. Then, the current transport mechanism in GaN, AlGaN, and InGaN Schottky barriers is discussed. We show that discrepancy in barrier height measurements in the I-V and the C-V methods, as well as large reverse leakage currents, can be explained by using the thin surface barrier (TSB) model. This understanding has led to a large leakage reduction by using an oxygen gettering process. Finally, the transient behavior of AlGaN/GaN planar Schottky diodes is discussed to get insight into the surface-related current collapse phenomenon in AlGaN/GaN high electron mobility transistors (HEMTs). The responses are explained in terms of the dispersive transport caused by a time-continual random walk with hopping through surface states. This provides a new understanding of the current collapse.
  • Hideki Hasegawa, Masamichi Akazawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 27 (4) 2048 - 2054 1071-1023 2009/07 [Refereed][Not invited]
     
    The current collapse transient behavior of a practical submicron AlGaN/GaN heterostructure field effect transistor (HFET) is investigated, and its mechanism is proposed. First, the steady-state and transient characteristics of the Schottky diode obtained by connecting the source and drain electrodes of the transistor have been investigated. The steady-state characteristics can be explained by the thin surface barrier model, indicating the presence of tunneling injection of electrons. Turn-on and turn-off transient characteristics of the reverse current of Schottky diode showed very slow nonexponential transients covering six orders of magnitude of time scale from milliseconds to thousands of seconds. They are very similar to those of a large planar Schottky diode studied recently by the authors. The HFET device showed a clear current collapse behavior after a gate stress beyond pinch off. Pulsed gate stress visualized drain current transients which again included very slow nonexponential transients covering six orders of magnitude of time scale. The whole experimental results are explained consistently by a model in which the current collapse is due to surface state charging near the source side and drain side of the gate edge where its rate limiting process is not the usual Shockley-Read-Hall capture-emission process but the dispersive electron transport through the surface states by time-continual hopping, which is triggered by the tunneling injection process at the gate edge.
  • Masamichi Akazawa, Alina Domanowska, Boguslawa Adamowicz, Hideki Hasegawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 27 (4) 2028 - 2035 1071-1023 2009/07 [Refereed][Not invited]
     
    The authors performed a detailed capacitance-voltage (C-V) and photoluminescence (PL) study of the high-k dielectric/GaAs interface controlled by the Si interface control layer (Si ICL) grown by molecular beam epitaxy to investigate the feasibility of a PL method for interface characterization and to find out the optimum thickness of the Si ICL. The sample had a HfO2/SiNx/Si ICL/n-GaAs structure where the ultrathin SiNx buffer layer was formed by in situ partial nitridation of the Si ICL itself. For this structure, they measured the quantum efficiency of photoluminescence as a function of the excitation photon flux density and carried out a computer analysis to determine the most likely distribution of the interface state density D-it. Remarkably good agreements were obtained between the high-frequency C-V method and the PL method, indicating that the present PL method may serve as a powerful contactless and nondestructive tool for developing an optimal surface passivation structure and its processing technology. Using C-V and PL methods, they found the optimum initial thickness of Si ICL before partial nitridation to be 5-6 ML. With this thickness, a D-it minimum value of (1-2)x10(11) cm(-2) eV(-1) was achieved in the HfO2/SiNx/Si ICL/n-GaAs structure. When the thickness was too large, it led to the generation of misfit dislocations, whereas a too thin Si ICL led to subcutaneous nitridation of GaAs during partial nitridation of the Si ICL, leading to interface disorder.
  • Masamichi Akazawa, Hideki Hasegawa
    e-Journal of Surface Science and Nanotechnology 7 122 - 128 1348-0391 2009/01/10 [Refereed][Not invited]
     
    III-V metal-insulator-semiconductor (MIS) structures are recently attracting attentions as possible candidates of high-k gate stack for next generation CMOS transistors on the silicon platform. However, their basic electrical properties are not well understood. In order to further confirm the validity of the recently proposed distributed pinning-spot (DPS) model for anomalous admittance behavior of III-V MIS structures, we have carried out in this paper a detailed experimental and computer simulation study of a HfO 2/GaAs high-k MIS structure controlled by a silicon interface control layer (Si ICL). It is clearly shown that the measured frequency dependences of C-V curves and admittance are far away from the predictions by the standard Si MOS theory. On the other hand, they can be well reproduced by the DPS model which assumes random spatial distribution of pinning spots with high densities of interface states in addition to pinning-free regions with low interface state densities. The model indicates that use of low-dimensional structures such as nanowires and nanodots may be beneficial for removal of pinning spots. © 2009 The Surface Science Society of Japan.
  • Hideki Hasegawa, Masamichi Akazawa
    APPLIED SURFACE SCIENCE 255 (3) 628 - 632 0169-4332 2008/11 [Refereed][Not invited]
     
    The present status and key issues of surface passivation technology for III-V surfaces are discussed in view of applications to emerging novel III-V nanoelectronics. First, necessities of passivation and currently available surface passivation technologies for GaAs, InGaAs and AlGaAs are reviewed. Then, the principle of the Si interface control layer (ICL)-based passivation scheme by the authors' group is introduced and its basic characterization is presented. Ths Si ICL is a molecular beam epitaxy ( MBE)grown ultrathin Si layer inserted between III-V semiconductor and passivation dielectric. Finally, applications of the Si ICL method to passivation of GaAs nanowires and GaAs nanowire transistors and to realization of pinning-free high-k dielectric/GaAs MOS gate stacks are presented. (c) 2008 Elsevier B. V. All rights reserved.
  • H. Hasegawa, M. Akazawa
    APPLIED SURFACE SCIENCE 254 (24) 8005 - 8015 0169-4332 2008/10 [Refereed][Not invited]
     
    Interface models and processing technologies are reviewed for successful establishment of surface passivation, interface control and MIS gate stack formation in III-V nanoelectronics. First, basic considerations on successful surface passivation and interface control are given, including review of interface models for the band alignment at interfaces, and effects of interface states in nanoscale devices. Then, a brief review is given on currently available surface passivation technologies for III-V materials, including the Si interface control layer (ICL)- based passivation scheme by the authors' group. The Si-ICL technique has been successfully applied to surface passivation of nanowires and to formation of a HfO(2) high-k dielectric/GaAs interfaces with low values of the interface state density. (C) 2008 Published by Elsevier B. V.
  • Masamichi Akazawa, Hideki Hasegawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 26 (4) 1569 - 1578 1071-1023 2008/07 [Refereed][Not invited]
     
    Admittance behavior of high-k GaAs metal-insulator-semiconductor (MIS) capacitors having an ultrathin SiNx/Si interface control double layer has been investigated in detail. The measured admittance showed characteristic features that are difficult to explain by the standard Si metal-oxide-semiconductor theory. They include (1) vertical and horizontal types of frequency dispersion in C-V curves, (2) presence of offset conductance in G/omega-f plot, and (3) discrepancy between the surface potential from the high-frequency capacitance and the corresponding relaxation frequency of interface states. All of these features are tentatively explained in a unified manner by a new distributed pinning spot (DPS) model where the MIS interface consists of DPSs in addition to pinning-free regions. When the separation of pinning spots is small, the sample shows vertical type of frequency dispersion with almost bias-independent high-frequency capacitance corresponding to pinning near midgap. When pinning spots are widely separated, the C-V curves show horizontal type of frequency dispersion, each curve showing large capacitance variation with bias. This is due to flatband voltage shifts caused by effective interface state charge at the pinning spots. The pinning spot also gives rise to conductance offset. The discrepancy related to the relaxation frequency of interface states is explained by appearance of saddle points in the potential due to interaction between pinning spots and pinning-free region. (C) 2008 American Vacuum Society.
  • Hideki Hasegawa, Masamichi Akazawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 26 (4) 1542 - 1550 1071-1023 2008/07 [Refereed][Not invited]
     
    To get information on the current collapse mechanism under gate bias stress in AlGaN/GaN heterostructure field effect transistors, this article investigates the steady state and transient behavior of current in a planar Schottky metal contact formed on a standard AlGaN/GaN high electron mobility transistor wafer. Schottky contacts with reduced reverse leakage currents were prepared by using an oxygen gettering process, and their electrical characteristics were studied by current-voltage, capacitance-voltage, and current-time measurements at various temperatures. When the voltage pulse was applied into the pinch-off region, an excess current flew, showing very slow nonexponential transients covering six orders of magnitude of time from millisecconds to thousand seconds. Turn-off transients were also slow and highly nonexponential. The current transients are shown to be due to charging and discharging of the virtual gate capacitor with the electrons in and out of surface trapping states where the rate limiting process is the hopping process of electrons. The process can be described by a dispersive hopping transport, leading to charging behavior with a stretched exponential dependence on time and discharging behavior with power law dependence on time. Theoretical formulas showed good agreements with experiments, and provide ample description of the transients processes directly related to the current collapse. (C) 2008 American Vacuum Society.
  • Hideki Hasegawa, Masamichi Akazawa
    APPLIED SURFACE SCIENCE 254 (12) 3653 - 3666 0169-4332 2008/04 [Refereed][Not invited]
     
    Strong interests are recently emerging for development of integrated high-performance chemical sensor chips. In this paper, the present status of understanding and controlling the current transport in the GaN and AlGaN Schottky diodes is discussed from the viewpoint of chemical sensor applications. For this purpose, a series of works recently carried out by our group are reviewed in addition to a general discussion. First, current transport in GaN and AlGaN Schottky barriers is discussed, introducing the thin surface barrier (TSB) model to explain the anomalously large leakage currents. Following this, attempts to reduce the leakage currents are presented and discussed. Then, as an example of gas-phase sensors using Schottky barriers, a Pd/AlGaN/GaN Schottky diode hydrogen sensor developed recently by our group is presented with a discussion on the sensing mechanism and related current transport. On the other hand, in liquid-phase sensors, contact is made between liquid and semiconductor which is regarded as a kind of Schottky barrier by electrochemists. As one of such liquid-phase sensors, open-gate AlGaN/GaN heterostructure field effect transistor (HFET) pH sensor developed recently by our group is presented. Finally, a brief summary is given together with some remarks for future research. (C) 2007 Elsevier B.V. All rights reserved.
  • Masamichi Akazawa, Hideki Hasegawa
    2008 IEEE 20TH INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS (IPRM) 473 - 476 1092-8669 2008 [Refereed][Not invited]
     
    Performances of InP-based and AlGaN-based Schottky diode hydrogen sensors with low-leakage currents were compared for understanding of the underlying sensing mechanism and for the purpose of material selection. The result indicated applicability of the interface dipole mechanism for sensing, higher sensitivity of InP sensor at room temperature and superiority of the AlGaN sensor at higher temperatures.
  • M. Akazawa, H. Hasegawa
    PHYSICA STATUS SOLIDI C - CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 5, NO 9 5 (9) 2729 - + 1862-6351 2008 [Refereed][Not invited]
     
    A pinning free high-k dielectric metal-insulator semiconductor (MIS) gate sstack was realized on GaAs surfaces by using a Si interface control layer (Si ICL). The MIs structure has a SiN/Si. ICL ultrathin double layer inserted between GaAs and HfO. Si ICL was grown epitaxially on a Ga stabilized GaAs surface by molecular beam epitaxy (MBE). The ultrathin SiNx buffer film was formed by in situ partial nitridation of Si. ICL in the MBE chamber. An X-ray photoelectron spectorscopy (XPS) analysis indicated that the ultrathin SiNx/Si ICL structure is chemically stable against air exposure, pre-through the ultrathin SiNx film itself partially turns into SiOxNy. Using this feature, a high k MIs capacitor was formed by ex situ deposition of HfO2 on the SiOxNy/Si. ICL/GaAs structure. The capacitance voltage (CV) analysis of the high k MIS sample after rapid thermal annealing at 500 degrees C for 30 see indicated that the MIS interface is completely free from Fermi level pinning with a minimum interface state density below 1011 cm(-2) eV(-1). (c) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
  • M. Akazawa, H. Hasegawa
    PHYSICA STATUS SOLIDI C - CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 5, NO 6 5 (6) 1959 - 1961 1862-6351 2008 [Refereed][Not invited]
     
    High temperature sensing characteristics of a Pd/AlGaN/GaN Schottky diode hydrogen sensor were investigated. By applying an oxygen gettering process, the diode showed very small leakage currents even at elevated temperatures. On exposure to 10 Torr hydrogen in an air ambient (200 Toff), the diode showed a large current change of four orders of magnitude. The observed sensing behaviour could be fitted to a theory based on the sensing mechanism involving Schottky barrier height reduction due to interface dipole formation by atomic hydrogen. The diode showed much improved characteristics at 110 degrees C than at room temperature. This surprising result is explained in terms of the current transport mechanism. The diode showed much better sensing characteristics than those of GaAs and InP.
  • AKAZAWA M
    J. Vac. Sci. Technol. B AVS Science & Technology of Materials, Interfaces, and Processing 25 (4) 1481 - 1490 0734-211X 2007/07 [Refereed][Not invited]
     
    In order to realize pinning-free high-k dielectric metal-insulator-semiconductor (MIS) gate stack on (001) and (111)B oriented GaAs surfaces using the Si interface control layer (Si ICL) concept, formation of a SiNx/Si ICL double layer was investigated as a chemically stable structure on (001) and (111)B surfaces which allows ex situ deposition of HfO2 high-k dielectric films without losing the benefit of Si ICL. First, Si ICLs grown by molecular beam epitaxy (MBE) on (001) and (111)B GaAs surfaces with various initial surface reconstructions were investigated in detail by reflection high e...
  • Hasegawa Hideki, Akazawa Masamichi
    Journal of Vacuum Science & Technology B : Microelectronics and Nanometer Structures AVS Science & Technology of Materials, Interfaces, and Processing 25 (4) 1495 - 1503 0734-211X 2007/07 [Refereed][Not invited]
     
    Hydrogen sensing characteristics in vacuum and in air were investigated on Pd Schottky diodes that were formed on AlGaN/GaN two-dimensional electron gas wafer and subjected to a surface control process for oxygen gettering. By applying the surface control process, leakage currents in Pd/AlGaN/GaN Schottky diode were greatly reduced. Such diodes showed high hydrogen detection sensitivities and fast turn-on and -off characteristics in air, although they showed very slow turn-off behavior in vacuum. From detailed measurements of current-voltage (I-V), capacitance-voltage (C-V), and current tra...
  • Hideki Hasegawaa, Masamichi Akazawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 25 (4) 1495 - 1503 1071-1023 2007/07 [Refereed][Not invited]
     
    Hydrogen sensing characteristics in vacuum and in air were investigated on Pd Schottky diodes that were formed on AlGaN/GaN two-dimensional electron gas wafer and subjected to a surface control process for oxygen gettering. By applying the surface control process, leakage currents in Pd/AlGaN/GaN Schottky diode were greatly reduced. Such diodes showed high hydrogen detection sensitivities and fast turn-on and -off characteristics in air, although they showed very slow turn-off behavior in vacuum. From detailed measurements of current-voltage (I-V), capacitance-voltage (C-V), and current transient characteristics, the sensing mechanism was explained in terms of Schottky barrier height reduction caused by formation of interface dipole by atomic hydrogen. It was shown that dipole formation is controlled in air by the Langmuir isotherm type adsorption behavior, including the reaction between atomic hydrogen and oxygen. Discrepancies in Schottky barrier height values deduced from I-V and C-V measurements have indicated that current transport is not by the standard thermionic emission process, but by the thermionic field emission process through the thin surface barrier (TSB) in accordance with the TSB model. (C) 2007 American Vacuum Society.
  • Masamichi Akazawa, Hideki Hasegawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 25 (4) 1481 - 1490 1071-1023 2007/07 [Refereed][Not invited]
     
    In order to realize pinning-free high-k dielectric metal-insulator-semiconductor (MIS) gate stack on (001) and (111)B oriented GaAs surfaces using the Si interface control layer (Si ICL) concept, formation of a SiNx,/Si ICL double layer was investigated as a chemically stable structure on (001) and (111)B surfaces which allows ex situ deposition of HfO2 high-k dielectric films without losing the benefit of Si ICL. First, Si ICLs grown by molecular beam epitaxy (MBE) on (001) and (111)B GaAs surfaces with various initial surface reconstructions were investigated in detail by reflection high energy electron diffraction and x-ray photoelectron spectroscopy (XPS) investigations at each step of the interface formation. Large shifts of the surface Fermi level position toward unpinning were observed after Si ICL growth on appropriately formed Ga-stabilized surfaces. It was found that Si layers grow epitaxially with Si-Ga bonds at the Si/GaAs interface and Si-As termination on top, suggesting surfactant roles played by As atoms. Then, an ultrathin SiNx buffer film was formed on the Si ICL by its in situ partial nitridation in the MBE chamber. An XPS analysis of the resultant SiNx/Si ICL double layer formed on (001) and (111)B surface indicated that the structure is chemically stable against air exposure on both surfaces in the sense that it prevents the host GaAs surface from subcutaneous oxidation, although SiNx film itself partially turns into SiOxNy, Finally, high-k MIS capacitors were formed by ex situ deposition of HfO2 on the SiNx/Si ICL/GaAs structure after transferring the sample through air. The capacitance-voltage (C-V) analysis indicated that the MIS interface is completely pinning-free with a minimum interface state density in the range of low 10(11) cm(-2) eV(-1). (C) 2007 American Vacuum Society.
  • Masamichi Akazawa, Hideki Hasegawa, Rui Jia
    PHYSICA STATUS SOLIDI A-APPLICATIONS AND MATERIALS SCIENCE 204 (4) 1034 - 1040 0031-8965 2007/04 [Refereed][Not invited]
     
    Detailed properties of the Si interface control layer (Si ICL)-based surface passivation structure are characterized by in-situ X-ray photoelectron spectroscopy (XPS) in an ultra-high vacuum multi-chamber system. Si ICLs were grown by molecular beam epitaxy (MBE) on GaAs and AlGaAs(001) and (1 1 1)B surfaces, and were partially converted to SiNx by nitrogen radical beam. Freshly MBE-grown clean GaAs and AlGaAs surfaces showed strong Fermi level pinning. Large shifts of the surface Fermi level position corresponding to reduction of pinning took place after Si ICL growth, particularly on (1 1 1)B surface (around 500 meV). However, subsequent surface nitridation increased pinning again. Then, a significant reduction of pinning was obtained by changing SiNx to silicon oxynitride by intentional air-exposure and subsequent annealing. This has led to realization of a stable passivation structure with an ultrathin oxynitride/Si ICL structure which prevented subcutaneous oxidation during further device processing under air-exposure. The Si-ICL-based passivation process was applied to surface passivation of quantum wire (QWR) transistors where anomalously large side-gating phenomenon was completely eliminated. (c) 2007 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
  • Masamichi Akazawa, Hideki Hasegawa
    JOURNAL OF CRYSTAL GROWTH 301 951 - 954 0022-0248 2007/04 [Refereed][Not invited]
     
    In nanostructures, the surface-to-volume ratio is increased, and surface state problems become more serious, making success of the future Ill-V nanoelectronics strongly dependent on surface passivation. To solve this problem, we have been investigating a passivation scheme using a Si interlayer called Si interface control layer (Si ICL) [H. Hasegawa, Thin Solid Films 367 (2000) 58]. However, main efforts have been limited on (0 0 1) surfaces. This paper investigates the applicability of the Si ICL approach to (1 1 1)B surfaces. An ultrathin (1 nm) silicon layer was grown by MBE on GaAs and AlGaAs (1 1 1)B surfaces with (2 x 2), (root 19 x root 19) and (1 x 1) surface reconstructions. Surfaces were characterized by in situ X-ray photoelectron spectroscopy (XPS) technique. Si layers grew epitaxially with Si-Ga bonds at the Si/GaAs interface and Si-As termination on top, suggesting surfactant roles played by As atoms. On nitridation of Si layer by nitrogen radicals at room temperature, Si-As bonds were replaced by Si-N bonds leading to partial nitridation of the Si layer. Unlike the case of the As-stabilized GaAs (0 0 1)-(2 x 4) surface, large reduction of band bending by 250-420 meV took place on (1 1 1)B surfaces, indicating large reduction of surface states. The results indicate effectiveness of the Si ICL passivation on (1 1 1)B surface. (c) 2006 Elsevier B.V. All rights reserved.
  • Masamichi Akazawa, Hideki Hasegawa, Rui Jia
    Physica Status Solidi (A) Applications and Materials Science 204 (4) 1034 - 1040 1862-6300 2007/04 [Refereed][Not invited]
     
    Detailed properties of the Si interface control layer (Si ICL)-based surface passivation structure are characterized by in-situ X-ray photoelectron spectroscopy (XPS) in an ultra-high vacuum multi-chamber system. Si ICLs were grown by molecular beam epitaxy (MBE) on GaAs and AlGaAs(001) and (111)B surfaces, and were partially converted to SiN x by nitrogen radical beam. Freshly MBE-grown clean GaAs and AlGaAs surfaces showed strong Fermi level pinning. Large shifts of the surface Fermi level position corresponding to reduction of pinning took place after Si ICL growth, particularly on (111)B surface (around 500 meV). However, subsequent surface nitridation increased pinning again. Then, a significant reduction of pinning was obtained by changing SiN, to silicon oxynitride by intentional air-exposure and subsequent annealing. This has led to realization of a stable passivation structure with an ultrathin oxynitride/Si ICL structure which prevented subcutaneous oxidation during further device processing under airexposure. The Si-ICL-based passivation process was applied to surface passivation of quantum wire (QWR) transistors where anomalously large side-gating phenomenon was completely eliminated. © 2007 WILEY-VCH Verlag GmbH & Co. KGaA.
  • Masamichi Akazawa, Hideki Hasegawa
    PHYSICA STATUS SOLIDI C - CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 4 NO 7 2007 4 (7) 2629 - + 1862-6351 2007 [Refereed][Not invited]
     
    Hydrogen sensing characteristics of surface-controlled Pd/AlGaN/GaN Schottky diodes were investigated in air. Sensors showed high detection sensitivities and fast turn-on and turn-off characteristics. Sensing dynamics and mechanism were explained in terms of Schottky barrier height reduction due to hydrogen-induced interface dipole. Here, the dipole formation is controlled by the Langmuir isotherm including an oxygen reaction, and current transport is due to thermionic field emission. (c) 2007 WILEY-NCH Verlag GmbH & Co. KGaA, Weinheim.
  • T Tanaka, M Akazawa, E Sano, M Tanaka, F Miyamaru, M Hangyo
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 (5A) 4058 - 4063 0021-4922 2006/05 [Refereed][Not invited]
     
    Extraordinary transmission phenomena through subwavelength hole arrays perforated in metal films have been reported mainly in the optical region. Using finite difference time domain (FDTD) simulations, we investigate transmission characteristics through metal hole arrays at the frequencies where the metal acts as a perfect conductor. Simulations reveal that enhanced transmission occurs even in such a frequency region. Transmission spectra and electric field distributions suggest the Fano-type interference between the discrete surface plasmon-polariton (SPP) mode and the scattering modes. The parameters describing the Fano resonance are extracted from the transmission characteristics calculated by the FDTD method.
  • M Akazawa, N Shiozaki, H Hasegawa
    JOURNAL DE PHYSIQUE IV 132 (0) 95 - 99 1155-4339 2006/03 [Refereed][Not invited]
     
    Applicability of the Si interface control layer (Si ICL)-based surface passivation to GaAs and AlGaAs (111)B Surfaces was investigated. An in-situ X-ray photoelectron spectroscopy (XPS) study confirmed formation of the intended passivation structure. MBE grown GaAs and AlGaAs (111)B surfaces showed strong Fermi level pinning. After Si ICL growth, large shifts of the surface Fermi level position were observed. Photoluminescence (PL) measurements were also used to examine the surfaces of AlGaAs/GaAs quantum well and quantum wire structures grown oil the GaAs (111)B substrates. PL intensity reduction caused by surface states was recovered remarkably by the Si ICL-based passivation.
  • N Shiozaki, T Sato, M Akazawa, H Hasegawa
    JOURNAL DE PHYSIQUE IV 132 (0) 249 - 253 1155-4339 2006/03 [Refereed][Not invited]
     
    For controlled low-damage etching of AlGaAs/GaAs nanostructures. fundamental properties of an etching process consisting of anodic oxidation and subsequent oxide dissolution are investigated both theoretically and experimentally. Anodic oxides formed on GaAs (001) and (111)B surfaces have the same composition and the same anodization parameters according to XPS, SEM and AFM measurements. The same applies to those formed on Al(0.3)Gi(0.7)As (001) and (111)B surfaces. The etching depth can be precisely controlled in nanometer scale by the anodization voltage. Selective etching was realized, using the lithography patterns. The surface morphology is much better than that in the standard wet chemical etching.
  • AKAZAWA MASAMICHI, AKAZAWA MASAMICHI, SHIOZAKI NANAKO, SHIOZAKI NANAKO, SATO TAKETOMO, SATO TAKETOMO, HASEGAWA HIDEKI, HASEGAWA HIDEKI
    電子情報通信学会技術研究報告 一般社団法人電子情報通信学会 105 (110(ED2005 58-66)) 25 - 30 0913-5685 2005/06/03 [Not refereed][Not invited]
     
    We attempted to apply a Si-interface-control-layer (Si ICL)-based surface passivation method to the surfaces of quantum structures fabricated on GaAs(111)B substrates. The sample surfaces were investigated by an XPS study at each step of the fabrication process, and fabricated quantum structures were characterized by PL measurements. Shifts of surface Fermi level positions toward the conduction band edges at GaAs and AlGaAs(111)B surfaces were observed after the Si ICL formation. PL intensities reduced with reduction of distances between quantum structures and their surfaces. The surface passivation using the Si-ICL, however, recovered PL intensities for quantum structures.
  • M Tanaka, F Miyamaru, M Hangyo, T Tanaka, M Akazawa, E Sano
    OPTICS LETTERS 30 (10) 1210 - 1212 0146-9592 2005/05 [Refereed][Not invited]
     
    We studied the role of surface-plasmon polaritons (SPPs) in a bandpass transmission property of two-dimensional metal hole arrays (2D-MHAs) by investigating the effect of thin dielectric layers on the 2DMHA surfaces. We measured zero-order transmission spectra of the 2D-MRAs by changing the thickness of the dielectric layer and found that the bandpass transmission peak shifted to the lower-frequency side with increasing layer thickness, owing to the change of the resonant frequency of the SPR This result shows that SPPs play a crucial role in the transmission property of 2D-MH-As in the terahertz region. © 2005 Optical Society of America.
  • M Akazawa, Y Yamazaki, E Sano
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS 44 (46-49) L1481 - L1483 0021-4922 2005 [Refereed][Not invited]
     
    We studied THz transmission characteristics of a thin metal hole-array filter whose thickness was much smaller than the transmitted wavelength, based on the time-domain sampling. A high transmittance was observed in a passband without a waveguide-like cutoff frequency. Tilting incident angle resulted in splits of the transmission peak. Time-domain waveforms of the transmitted waves indicated the stagnation having frequency-spectrum components in the passbands. Participation of surface plasmon-polaritons in the transmission process is discussed.
  • 金属薄膜による表面周期構造を利用したTHz波フィルタ
    田中毅, 赤澤正道, 佐野栄一
    信学技報 109 (296) 51 - 56 2004/09 [Not refereed][Not invited]
  • T Tanaka, M Akazawa, E Sano
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS 43 (2B) L287 - L289 0021-4922 2004/02 [Refereed][Not invited]
     
    Properties of filters composed of metal meshes for THz waves are studied based on a numerical full-wave simulation by the finite difference time domain (FDTD) method. It is predicted that thinning a single metal-mesh plate deteriorates stop-band attenuation even if the metal is lossless. It is described that cascading identical thin-metal-film meshes improves stop-band attenuation and that a compact filter producible by the fabrication process for microelectronics can be obtained by inserting a dielectric layer as a reinforcement material.
  • Eiichi Sano, Koji Inafune, Masamichi Akazawa
    IEICE Electronics Express 1 (8) 233 - 236 1349-2543 2004 [Refereed][Not invited]
     
    We propose a high-performance inductor based on the concept of a high-impedance surface (or artificial magnetic conductor). The inductor is shielded from the silicon substrateby a high-impedance surface consisting of a lumped capacitor and inductor. Theoretical calculations comparing the proposed inductor with a conventional inductor shielded by an ordinarymetal surface show that the resonant frequency and quality factor (Q) in the millimeter-waveregion are higher for the proposed inductor. © 2004, The Institute of Electronics, Information and Communication Engineers. All rights reserved.
  • Masamichi Akazawa
    The IEICE Transactions on Electronics (Japanese Edition) 一般社団法人電子情報通信学会 J86-C (7) 718 - 725 1345-2827 2003/07 [Refereed][Not invited]
     
    単電子デバイスの準静的動作の極限において,消費電力がかからない無損失の,断熱的なスイッチング動作となることがあり得るかどうかについて考察した.通常,トランジスタに代表されるスイッチング素子においてはしきい値が存在し,そのしきい値において急激なエネルギー変化を伴うことから準静的動作による消費電力の低減には限界がある.しかし,単電子デバイスでは,デバイスの設計次第で,準静的な電圧変化に対して急激なエネルギー変化を伴わないスイッチングが可能である.本論文では,単電子デバイスの準静的動作について,その消費電力特性を数値計算により予測した結果を示す.
  • M Akazawa
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 86 (12) 1 - 9 8756-663X 2003 [Refereed][Not invited]
     
    This paper presents the possibility of an adiabatic switching operation that is lossless, with zero power consumption, in the limit of a quasistatic operation of a single-electron device. Usually, in a switching device represented by a transistor, there exists a threshold. Since an abrupt energy dissipation accompanies crossing of the threshold, there is a limitation in the reduction of power consumption by quasistatic operation. However, in an appropriately designed single-electron device, switching without an abrupt energy dissipation is possible by a quasistatic voltage change. In this paper, in regard to the quasistatic operation of a single-electron device, the power consumption characteristics are estimated numerically. (C) 2003 Wiley Periodicals, Inc.
  • M Akazawa, H Hasegawa
    PHYSICA STATUS SOLIDI A-APPLIED RESEARCH 195 (1) 248 - 254 0031-8965 2003/01 [Refereed][Not invited]
     
    An ultrahigh-vacuum (UHV)-based contactless capacitance-voltage (C-V) method is applied to the semiconductors on insulating substrates, placing a reference electrode along the wafer periphery. The effect of parasitic impedance on the measurement is estimated mathematically, and a numerical correction method for C-V curves is established. The correction method is applied to the experimental data, and surface states of silicon-on-insulator (SOI) and GaN/sapphire samples are successfully evaluated.
  • Y Suda, T Ono, M Akazawa, Y Sakai, J Tsujino, N Homma
    THIN SOLID FILMS 415 (1-2) 15 - 20 0040-6090 2002/08 [Refereed][Not invited]
     
    Nanometer-size carbon particles were prepared on a Si substrate using pulsed laser deposition (PLD) assisted by radio frequency (RF) Ar plasma and were compared with ones prepared by PLD in vacuum and Ar gas. In both the plasma and gas ambiences, experiments were carried out in Ar pressure p(Ar) ranging from 0.13 to 13 Pa. The particle size increased as p(Ar) increased. However, the size obtained in the RF Ar plasma was approximately 1.5 times larger than that prepared in the Ar gas. An X-ray photoelectron spectroscopy (XPS) analysis revealed that the carbon film covered by the particles was in an amorphous state. The sp(3)/sp(2) carbon ratio of the film was evaluated by deconvolution of XPS carbon (Is) spectra into three components, which are attributed to diamond (sp(3)), graphite (sp(2)) and carbon oxide components. The highest sp(3) /sp(2) ratio was 0.4 in the Ar gas and Ar plasma at p(Ar) = 0.13 Pa. The sp(3) /sp(2) ratio decreases monotonously, as the particle size increases. The ratio obtained in the Ar plasma is larger than that in the Ar gas. The effects of p(Ar) and plasma for nanoparticle characteristics are discussed. (C) 2002 Elsevier Science B.V. All rights reserved.
  • T Ono, Y Suda, M Akazawa, Y Sakai, K Suzuki
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 41 (7A) 4651 - 4654 0021-4922 2002/07 [Refereed][Not invited]
     
    Amorphous carbon (a-C) thin films were deposited on S(111) substrates by an oxygen RF plasma-assisted pulsed laser deposition (PLD) method at an oxygen pressure of 53 mPa, as well as in vacuum and oxygen gas ambient at 53 mPa for comparison, at substrate temperatures (T-sub) between room temperature and 480degreesC. An X-ray photoelectron spectroscopy (XPS) analysis showed that the highest sp(3) content of the film was 58% in oxygen plasma PLD at T-sub = 410degreesC. Under this condition, the film surface morphology was shown to be quite smooth with a roughness of about 5 mm, by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Effects of the oxygen, plasma and the substrate temperature on the film properties were examined.
  • T Ono, Y Suda, M Akazawa, Y Sakai, K Suzuki
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 41 (7A) 4651 - 4654 0021-4922 2002/07 [Refereed][Not invited]
     
    Amorphous carbon (a-C) thin films were deposited on S(111) substrates by an oxygen RF plasma-assisted pulsed laser deposition (PLD) method at an oxygen pressure of 53 mPa, as well as in vacuum and oxygen gas ambient at 53 mPa for comparison, at substrate temperatures (T-sub) between room temperature and 480degreesC. An X-ray photoelectron spectroscopy (XPS) analysis showed that the highest sp(3) content of the film was 58% in oxygen plasma PLD at T-sub = 410degreesC. Under this condition, the film surface morphology was shown to be quite smooth with a roughness of about 5 mm, by scanning electron microscopy (SEM) and atomic force microscopy (AFM). Effects of the oxygen, plasma and the substrate temperature on the film properties were examined.
  • T. Yamada, M. Akazawa, T. Asai, Y. Amemiya
    Nanotechnology 12 (1) 60 - 67 0957-4484 2001/03 [Refereed][Not invited]
     
    We proposed a method of implementing the Boltzmann machine neural network on electronic circuits by making use of the single-electron tunnelling phenomenon. The single-electron circuit shows stochastic behaviour in its operation because of the probabilistic nature of the electron tunnelling phenomenon. It can therefore be successfully used for implementing the stochastic neuron operation of the Boltzmann machine. The authors developed a single-electron neuron circuit that can produce the function required for the Boltzmann machine neuron. A method for constructing Boltzmann machine networks by combining the neuron circuits was also developed. The simulated-annealing operation can be performed easily by regulating an external control voltage for the network circuits. A sample network was designed that solves an instance of a combinatorial optimization problem. Computer simulation demonstrated that, through the simulated-annealing process, the sample network can converge to the global minimum energy state that represents the correct solution to the problem.
  • CxFy polymer film deposition in rf and dc C7F16 vapor plasmas
    Y. Sakai, M. Akazawa, Y. Sakai, H. Sugawara, M. Tabata, C. P. Lungu, A. M. Lungu
    Transactions of Korean Institute of Electrical and Electronic Material Engineers 2 (1) 1 - 6 2001/03 [Refereed][Not invited]
  • A Three-Dimensional Cellular Neural Network Circuit System Using A νMOS Circuit
    M. Akazawa, T. Fujiwara, Y. Amemiya
    Proceedings of 2000 IEEE International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS 2000, Honolulu, Hawaii, U.S.A., November 5-8, 2000) 1061 - 1066 2000/11 [Refereed][Not invited]
  • Y. Suda, T. Nishimura, T. Ono, M. Akazawa, Y. Sakai, N. Homma
    Thin Solid Films 374 (2) 287 - 290 0040-6090 2000/10/17 [Refereed][Not invited]
     
    Carbon thin films containing many fine carbon particles were deposited by a pulsed ArF laser ablation technique assisted by inductively coupled plasma (ICP). The sizes of the particles were found to be approximately 100 nm. The particles seemed to be coagulated from several finer particles of size approximately 10 nm. When ICP was applied to a plume, the shape of the coagulated particles became spherical. The deposited surface was assumed to be diamond-like carbon based on the binding energy of carbon (1s) in the particle obtained by XPS spectra.
  • C. P. Lungu, A. M. Lungu, Y. Sakai, H. Sugawara, M. Tabata, M. Akazawa, M. Miyamoto
    Vacuum 59 (1) 210 - 219 0042-207X 2000 [Refereed][Not invited]
     
    Polymer films containing CxFy have been deposited in Fluorinert vapor (C7F16) plasmas. The spatial and temporal evolution of optical emission of CF2 and C2 radicals was monitored and kinetics of the C7F16 decomposition process was discussed. The films were deposited on stainless steel, glass, molybdenum and silicon wafers at room temperature with the vapor pressures, 40 and 100 Pa. Electrical properties such as the breakdown voltage and dielectric constant as well as the structure of the films were analyzed. The composition and characteristics of the films were determined by Fourier transform infrared spectroscopy and X-ray photoelectron spectroscopy techniques, scanning electron microscopy and electron spin resonance spectroscopy.
  • M. Akazawa, E. Tokuda, N. Asahi, Y. Amemiya
    Analog Integrated Circuits and Signal Processing 24 (1) 51 - 57 2000/01 [Refereed][Not invited]
  • CP Lungu, AM Lungu, M Akazawa, Y Sakai, H Sugawara, M Tabata
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS 38 (12B) L1544 - L1546 0021-4922 1999/12 [Refereed][Not invited]
     
    An attempt to fabricate fluorinated carbon (fluoropolymer) films by rf (13.56 MHz) plasma enhanced chemical vapor deposition was made using novel fluorocarbon sourer materials of C7F16, (C3F7)(3)N/(C4F9)(3)N and C8F18/C8F16O. The deposited films were transparent and displayed excellent electrical properties as interlayer dielectrics for LSI using deep-submicron technology, namely, a dielectric constant as low as 2.0 and a dielectric strength higher than 2 MV/cm. The refractive index of these films was 1.38.
  • M Akazawa, K Kanaami, T Yamada, Y Amemiya
    IEICE TRANSACTIONS ON ELECTRONICS E82C (9) 1607 - 1614 0916-8524 1999/09 [Refereed][Not invited]
     
    ill multiple-valued logic inverter is proposed that uses single-electron-tunneling (SET) circuits in which the discreteness of the electron charge is utilized. The inverter circuit, which is composed of only two SET transistors, has a memory function as well as an inverter function for multiple-valued logic. A quantizing circuit and a D flip-flop circuit for multiple-valued logic can be compactly constructed by combining two inverters. A threshold device can be compactly constructed by attaching more than one input capacitor to the inverter circuit. A quaternary full adder circuit can be constructed by using two threshold devices. Implementation issues are also discussed.
  • Single-Flux-Quantum Logic Devices Based on the Binary Decision Diagram
    Masamichi Akazawa
    Advances in Superconductivity XI, Eds. N. Koshizuka and S. Tajima 1271 - 1274 1999/04 [Refereed][Not invited]
  • H Iwamura, M Akazawa, Y Amemiya
    IEICE TRANSACTIONS ON ELECTRONICS E81C (1) 42 - 48 0916-8524 1998/01 [Refereed][Not invited]
     
    This paper proposes an architecture for circuit construction for developing single-electron integrated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation, It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision. it produces an output of logic "1" if the majority of the inputs is 1, and an output of "0" if the majority is 0, By combining the proposed majority gate circuits, various subsystems fan be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
  • N Asahi, M Akazawa, Y Amemiya
    IEICE TRANSACTIONS ON ELECTRONICS E81C (1) 49 - 56 0916-8524 1998/01 [Refereed][Not invited]
     
    This paper proposes a method of constructing single-electron logic subsystems on the basis of the binary decision diagram (BDD). Sample subsystems, an adder and a comparator, are designed by combining single-electron BDD devices. It is demonstrated by computer simulation that the designed subsystems successfully produce, through pipelined processing, an output data flow in response to the input data flow. The operation error caused by thermal agitation is estimated. An output interface for converting single-electron transport into binary-voltage signals is also designed.
  • M Ikebe, M Akazawa, Y Amemiya
    1998 SECOND INTERNATIONAL CONFERENCE ON KNOWLEDGE-BASED INTELLIGENT ELECTRONIC SYSTEMS, KES '98, PROCEEDINGS, VOL, 3 447 - 453 1998 [Refereed][Not invited]
     
    This paper proposes circuit construction for cellular-automaton devices that can perform morphological picture processing. To produce the complex cell functions required for the morphological processing, we propose using a silicon functional MOS device, the nu-MOS FET. We designed sample cell circuits for several morphological processings, and simulated their operation. We also designed a sample cellular-automaton circuit using the proposed cell circuits, and demonstrated in simulation that the nu-MOS cellular-automata circuits are very useful for constructing intelligent image sensors.
  • M. Akazawa, Y. Amemiya, N. Shibata
    Journal of Applied Physics 82 (10) 5176 - 5184 0021-8979 1997/11/15 [Refereed][Not invited]
     
    We propose an annealing method as an effective way of operating quantum-cellular-automaton (QCA) systems, which are devices for computation that utilize the minimum energy state of electrons in a quantum cell system. A QCA system has an energy function with many local minima and therefore cannot be operated as desired if placed under the conditions of a thermodynamically open system. Accordingly, for successful operation of a QCA system (i.e., making the QCA system converge successfully to its minimum-energy state), we propose a method of operation based on the concept of thermodynamic annealing. We simulate the dynamics of various QCA logic-gate systems operated by this annealing method, and show that data processing in QCA systems can be carried out accurately by means of this annealing method. The applicability of QCA systems to non-Neumann parallel-processing computation is also described. © 1997 American Institute of Physics.
  • M. Ikebe, M. Akazawa, Y. Amemiya
    Computers and Electrical Engineering 23 (6) 439 - 451 0045-7906 1997/11/01 [Refereed][Not invited]
     
    This paper proposes a design of cell circuits for implementing cellular-automaton devices that perform morphological picture processing. To produce the complex cell functions required for the morphological processing, we present the idea of using the silicon functional device, ν-MOS FET. We designed sample cell circuits for several morphological processings, and simulated their operation to show the expected cell operation. We also designed a sample cellular-automaton circuit using the proposed cell circuits, and demonstrated in simulation its example processing (noise cleaning and edge extraction in an image). A low dissipation of about 20 μW per cell circuit can be expected at 1 MHz operation therefore, 105 or more cells that operate in parallel can be integrated into an LSI. © 1998 Elsevier Science Ltd. All rights reserved.
  • AKAZAWA Masamichi
    Extended Abstracts of the Int. Conf. on Solid State Devices and Materials (SSDM'97) 1997 (0) 306 - 307 1997/09 [Refereed][Not invited]
  • M Akazawa, Y Amemiya
    IEICE TRANSACTIONS ON ELECTRONICS E80C (7) 849 - 858 0916-8524 1997/07 [Refereed][Invited]
     
    This paper describes a guiding principle for designing functional single-electron tunneling (SET) circuits-that is a way to elicit the potential functions of a given SET circuit by using as a guiding tool the SET circuit stability diagram. A stability diagram is a map that depicts the stable regions of a SET circuit based on the circuit's variable coordinates. By scrutinizing the diagram, we can infer all the potential functions that can be obtained from a circuit configuration. As an example, we take up a well-known SET-inverter circuit and uncover its latent functions by studying the circuit configuration, based on its stability diagram. We can produce various functions. e.g., step-inverter, Schmidt-trigger, memory cell, literal, and stochastic-neuron functions. The last function makes good use of the inherent stochastic nature of single-electron tunneling, and can be applied to Boltzmann-machine neural network systems.
  • N Asahi, M Akazawa, Y Amemiya
    IEEE TRANSACTIONS ON ELECTRON DEVICES 44 (7) 1109 - 1116 0018-9383 1997/07 [Refereed][Not invited]
     
    This paper proposes a single-electron logic device based on the concept of the binary decision diagram (BDD), The unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for logic circuits of NAND, NOR, exclusive-OR, and AND-OR combinational logic. Computer simulation shows that the designed circuits perform the logic operations correctly.
  • M Akazawa, Y Amemiya
    APPLIED PHYSICS LETTERS 70 (5) 670 - 672 0003-6951 1997/02 [Refereed][Not invited]
     
    The inherent stochastic character of single-electron tunneling can be effectively utilized for creating novel electronic circuits having high-level functions. As a sample application, we present a stochastic-response circuit for implementing Boltzmann machine neurons. The circuit consists of a single-electron circuit operating under unstable conditions. It can produce an output of a random 1-0 bit stream with the probability for an output of 1 controlled by an input signal-a task that is difficult for conventional circuits using ordinary electronic devices. (C) 1991 American Institute of Physics.
  • M Akazawa, T Yamada, Y Amemiya
    SISPAD '97 - 1997 INTERNATIONAL CONFERENCE ON SIMULATION OF SEMICONDUCTOR PROCESSES AND DEVICES 201 - 204 1997 [Refereed][Not invited]
     
    We present a computer-aided-design method for constructing a circuit for a Boltzmann-machine neuron, utilizing single-electron tunneling (SET). We have found, through computer simulation, that a stochastic response unit circuit can be made in a simple configuration using SET junctions, and the probability for an output of 1 can be controlled by the input voltages.
  • M Akazawa, Y Amemiya
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 35 (6A) 3569 - 3575 0021-4922 1996/06 [Refereed][Not invited]
     
    This paper proposes a directional single-electron-tunneling (SET) junction that allows electron tunneling in only one direction. It is shown that this device will provide various SET circuits with novel functions in simple construction. Theoretical analysis indicates that a metal-insulator-insulator-metal (M-I-I-M) SET junction could achieve excellent directionality with a large forward/reverse conductance ratio of the order of hundreds of thousands. As one of the circuit applications, a multiple-valued memory cell using directional SET junctions is proposed and its writing and storage operation is simulated.
  • N ASAHI, M AKAZAWA, Y AMEMIYA
    IEEE TRANSACTIONS ON ELECTRON DEVICES 42 (11) 1999 - 2003 0018-9383 1995/11 [Refereed][Not invited]
     
    The device proposed here for future LSI's is based on a concept different from the Boolean equations usually used for representing digital functions, The unit function of this device is simple two-way switching and can be implemented utilizing various physical effects, such as optical switching, electron-wave modulation, and single-electron transport, Several possible device structures are presented, and a simulated result for a single-electron device is described.
  • KOYANAGI Satoshi, AKAZAWA Masamichi, HASEGAWA Hideki
    Extended abstracts of the ... Conference on Solid State Devices and Materials 1995 (0) 833 - 835 1995/08 [Refereed][Not invited]
  • Investigation of Valence Band Offset Modification at GaAs-AlAs and InGaAs-InAlAs Heterointerfaces Induced by Si Interlayer
    M. Akazawa, H. Hasegawa, H. Tomozawa, H. Fujikura
    Inst. Phys. Conf. Ser. 129 253 - 258 1993/06 [Refereed][Not invited]
  • S KODAMA, M AKAZAWA, H FUJIKURA, H HASEGAWA
    JOURNAL OF ELECTRONIC MATERIALS 22 (3) 289 - 295 0361-5235 1993/03 [Refereed][Not invited]
     
    This paper attempts to control and optimize the interface atomic profiles of a novel surface passivation scheme for InGaAs nanostructures, using a silicon interface control layer (ICL). An in-situ x-ray photoelectron spectroscopy characterization technique was used to establish a process sequence that satisfies the conditions of maintenance of pseudomorphic matching to InGaAs, prevention of direct oxidation of InGaAs, and formation of a good SiO2/Si interface with minimal suboxide components. It is shown that the above conditions can be -satisfied by a new process that is a formation of the thermal SiO2 at the SiO2-Si interface by repetition of deposition/oxidation/annealing cycle. A large reduction of interface state density (N(SS)) was realized by the optimization of the new process, resulting in a minimum N(SS) of 4 x 10(11) CM-2 eV-1. The silicon ICL technique was successfully applied to the passivation of InGaAs wire structures.
  • H HASEGAWA, S KODAMA, K KOYANAGI, M AKAZAWA
    FIFTH INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS 289 - 292 1993 [Refereed][Invited]
  • M AKAZAWA, H HASEGAWA, H TOMOZAWA, H FUJIKURA
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS 31 (8A) L1012 - L1014 0021-4922 1992/08 [Refereed][Not invited]
     
    X-ray photoelectron spectroscopy reinvestigation is done for the recently reported Si-interlayer-induced change of the valence band discontinuity (DELTA-E(v)) at GaAs-AlAs interfaces. The XPS measurements reproduced the large apparent change of DELTA-E(v) caused by the Si interlayer. However, it also led to anomalous increases of separations between the core level peak and the valence band edge as well as anomalous increases of full width at half maximum of the core level spectra. It is concluded that the observed change of DELTA-E(v) is only an apparent one. The anomalies were explained quantitatively by a new model based on the surface Fermi level pinning and interface delta-doping.
  • H. Fujikura, H. Tomozawa, M. Akazawa, H. Hasegawa
    Applied Surface Science 60-61 (C) 702 - 709 0169-4332 1992 [Refereed][Not invited]
     
    Removal of surface Fermi level pinning is a crucial issue for successful realization of compound semiconductir quantum-effect devices. The purpose of this paper is to establish a process to fabricate InGaAs wires by selective MBE and to investigate the capability of an ultrathin Si interface control layer (ICL) on the wires in removing the surface Fermi level pinning. In0.53Ga0.47As wire structures with or without InAlAs buffer layers were fabricated for the first time by a selective MBE growth on corrugated InP surfaces formed by laser interference lithography. Then, the wire structures were covered with the Si ICL and a thick SiO2 overlayer. For comparison, InAlAs/InGaAs/InAlAs wire structures were also prepared. The structures were characterized by SEM, C-V and photoluminescence techniques. Optimum conditions for wire formations are established. It is shown that the Si ICL technique is useful and promising for removal of the Fermi level pinning in InGaAs quantum structures. © 1992.
  • H HASEGAWA, H FUJIKURA, M AKAZAWA, H TOMOZAWA
    INSTITUTE OF PHYSICS CONFERENCE SERIES 127 (127) 115 - 118 0951-3248 1992 [Refereed][Not invited]
     
    A novel approach to control the surfaces and interfaces of GaAs and InGaAs nanometer-scale structures using an ultrathin MBE Si interface control layer (Si ICL) is presented. Details of the Si ICL technique and its application to InGaAs wire structures are discussed.
  • H HASEGAWA, H FUJIKURA, M AKAZAWA, H TOMOZAWA
    QUANTUM EFFECT PHYSICS, ELECTRONICS AND APPLICATIONS 127 115 - 118 0951-3248 1992 [Refereed][Not invited]
  • M AKAZAWA, H ISHII, H HASEGAWA
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 30 (12B) 3744 - 3749 0021-4922 1991/12 [Refereed][Not invited]
     
    Removal or control of Fermi level pinning is attempted using an ultrathin molecular beam epitaxy (MBE) Si interface control layer (Si ICL) for insulator-semiconductor (I-S) and metal-semiconductor (M-S) interfaces of GaAs and InGaAs. or successful removal of Fermi level pinning at the I-S interface, the Si ICL should maintain an ordered pseudomorphic structure. The optimum thickness of the Si ICL is about 10 angstrom. Formation of such a Si ICL alone does not remove pinning; subsequent deposition of a SiO2 film is necessary for unpinning. Pinning at the air-exposed surfaces can be removed by combining an HF surface treatment with the Si ICL technique. The Si ICL technique is promising for controlling barrier heights at M-S interfaces.
  • H HASEGAWA, M AKAZAWA, E OHUE
    INDIUM PHOSPHIDE AND RELATED MATERIALS : THIRD INTERNATIONAL CONFERENCE, VOLS 1 AND 2 630 - 633 1991 [Refereed][Not invited]
  • H. Hasagawa, M. Akazawa, H. Ishii, A.Uraie, H.Iwadate, E.Ohue
    J. Vac. Sci. Technol. B 8 (4) 867 - 873 0734-211X 1990/07 [Refereed][Not invited]
  • H HASEGAWA, M AKAZAWA, H ISHII, A URAIE, H IWADATE, E OHUE
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 8 (4) 867 - 873 1071-1023 1990/07 [Refereed][Not invited]
  • M AKAZAWA, E OHUE, H ISHII, H IWADATE, H HASEGAWA
    SECOND INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS 88 - 91 1990 [Refereed][Not invited]
  • H HASEGAWA, M AKAZAWA, H ISHII, K MATSUZAKI
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 7 (4) 870 - 878 1071-1023 1989/07 [Refereed][Not invited]
  • Masamichi Akazawa, Hideki Hasegawa, Eiji Ohue
    Japanese Journal of Applied Physics 28 (11 A) L2095 - L2097 1347-4065 1989 [Refereed][Not invited]
     
    A novel In0.53Ga0.47As MIS structure having an ultrathin MBE Si interface control layer (ICL) between InGaAs and photo-CVD SiO2, is described and applied to fabrication of MISFETs. XPS and electrical characterization show that Si ICL prevents selective oxidation of InGaAs and reduces the interface state density. Depletion mode MISFETs gave an effective channel mobility of 1700 cm2/V·s and excellent stability with drain current drift below 1% up to 104 s. © 1989 The Japan Society of Applied Physics.
  • H HASEGAWA, M AKAZAWA, KI MATSUZAKI, H ISHII, H OHNO
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 2-LETTERS & EXPRESS LETTERS 27 (12) L2265 - L2267 0021-4922 1988/12 [Refereed][Not invited]
     
    A novel compound semiconductor MIS structure using an ultra-thin partially oxidized MBE Si film as a pseudomorphic interface control layer (ICL) is reported for GaAs and InGaAs. As an outer insulator layer, a silicon dioxide or silicon nitride film is deposited in-situ by a low-temperature photo-CVD process using an ArF excimer laser. While the GaAs MIS structure exhibited strong Fermi level pinning, the InGaAs MIS structure showed completely "unpinned" behavior with a very small hysteresis after annealing. The difference is qualitatively explained by a band line-up of the constituent mater...

MISC

  • Chiba Masahito, Nakano Takuma, Akazawa Masamichi  IEICE technical report. Electron devices  113-  (329)  101  -105  2013/11/28  
    We investigated the dependence of the electrical properties on the fabrication procedure for InAlN MOS structure having an Al_2O_3 layer formed by atomic layer deposition (ALD). When the ALD Al_2O_3/InAlN interface was formed after ohmic-contact annealing in nitrogen without the use of a cap layer, the electrical properties were poor, resulting in a small capacitance change in the capacitance-voltage (C-V) curve. X-ray photoelectron spectroscopy (XPS) study indicated that the bare InAlN surface was oxidized during capless annealing presumably owing to the trace contamination in the furnace. High-temperature ohmic-contact annealing after Al_2O_3/InAlN interface formation did not improve the interface properties, resulting in interface state density D_ in the range of 10^<13>cm^<-2>eV^<-1>, despite the use of the Al_2O_3 layer for surface protection. This was highly likely related to the crystallization of Al_2O_3. When a SiN_x layer was used as the cap layer during ohmic-contact annealing prior to ALD, greatly improved characteristics of the MOS diode were achieved, indicating that D_ was suppressed to be in the range of 10^<12>cm^<-2>eV^<-1> near the conduction band. Furthermore, as a result of low-temperature post-deposition annealing at 400℃ for this sample, reduction of the interface states was achieved. The obtained results indicate that an appropriate fabrication procedure leads to an improvement of the Al_2O_3/InAlN interface properties.
  • YAMAZAKI Yusuke, INAFUNE Koji, AKAZAWA Masamichi, SANO Eiichi  IEICE technical report. Electron devices  104-  (693)  41  -46  2005/02/24  
    A periodic structure in a subterahertz coplanar stripline (CPS) was fabricated on a low-temperature-grown GaAs (LT-GaAs) layer in order to achieve an electromagnetic bandgap (EBG). To optimize dimension of structures, we used the finite-difference-time-domain (FDTD) method for the full-wave analysis. In consequence, we found that the thickness of the metal layer affects the characteristic of EBGs. Take into account this result, the sample structure was designed, fabricated, and characterized by the photoconductive sampling (PCS). Two bandgaps and an intermediate passband were observed in the range up to 0.5THz, which coincided with the results of simulation based on the FDTD method.
  • INAFUNE Koji, AKAZAWA Masamichi, SANO Eiichi  IEICE technical report. Microwaves  104-  (296)  45  -49  2004/09/07  
    A numerical study of a method to reduce the radiation loss of a coplanar waveguide (CPW) is reported, and the application of the low-loss CPW to electromagnetic-bandgap (EBG) filters for the THz region is described. The finite-difference time-domain (FDTD) method was used for the full-wave analysis of CPWs and filters. It is expected that the radiation loss could be greatly reduced by constructing a CPW on a substrate consisting of a thin GaAs film reinforced with a thick backside insulator with a low dielectric constant. The application of the same substrate structure to a newly devised EBG-based filter built in a CPW was investigated, and the structure was found effective for preserving a high transmission rate in a high-frequency passband.
  • Akazawa Masamichi, Hasegawa Hideki  Proceedings of the Society Conference of IEICE  2002-  (2)  59  -59  2002/08/20
  • ONO Tomoyuki, SUDA Yoshiyuki, AKAZAWA Masamichi, SUGAWARA Hirotake, SAKAI Yosuke, SUZUKI Kaoru  電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan  2001-  381  -386  2001/09/21
  • HOKOI K., AKAZAWA M., SUGAWARA H., SUDA Y., SAKAI Y.  電気学会研究会資料. ED, 放電研究会  2001-  (111)  13  -18  2001/08/07
  • SHOUJI Ryouhei, HASHIZUME Tamotsu, YOSHIDA Toshiyuki, AKAZAWA Masamichi, HASEGAWA Hideki  IEICE technical report. Electron devices  100-  (641)  45  -52  2001/02/21  
    Ultrathin insulator/Si interfaces formed by various low temperature processes were characterized by UHV contactless C-V and XPS methods. For the SiO_2/Si interfaces prepared by thermal oxidation process using dry O_2, the interface state density was increased with decreasing the oxidation temperature. In addition, lower temperature process was found to produce a discrete defect level near midgap. The ECR-excited N_2O plasma process at 400℃ realized the interface with relatively low interface state density and wide distribution. Furthermore improvement of interface properties were achieved by the UHV annealing process at 900℃.
  • AKAZAWA M., KASAI S., HASHIZUME T., HASEGAWA H.  IEICE technical report. Electron devices  100-  (641)  89  -96  2001/02/21  
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the proposed device as a ULSI device by reducing its size.
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the Society Conference of IEICE  2000-  (2)  83  -83  2000/09/07
  • AKAZAWA Masamichi  Proceedings of the Society Conference of IEICE  2000-  (2)  76  -76  2000/09/07
  • KANAAMI K., AKAZAWA M., AMEMIYA Y.  IEICE technical report. Circuits and systems  99-  (550)  1  -8  2000/01/19  
    Functional LSIs using extremely small amounts of power can be made by using single-electron circuits, but designing the parameters of such circuits is a complicated and troublesome task. This paper therefore propose, taking the single-electron inverter circuit as an example, a simple policy for the circuit-parameter design. Following this policy, we can easily design a single-electron inverter with a desired transfer characteristic. We have, for example, designed a special inverter circuit that can be used for constructing multiple-valued logic systems. A multiple-valued transfer characteristic(or a staircase transfer curve), which is difficult to obtain with CMOS circuits, can be obtained easily.
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the IEICE General Conference  128  -128  2000
  • NISHIMURA Takuma, MIZUNO Manabu, SUDA Yoshiyuki, SAKAI Yosuke, AKAZAWA Masamichi  電気学会研究会資料. ED, 放電研究会  1999-  (148)  79  -84  1999/10/19
  • SUDA Yoshiyuki, MIZUNO Manabu, NISHIMURA Takuma, BRATESCU M. A., SAKAI Yosuke, AKAZAWA Masamichi  電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan  1999-  324  -329  1999/09/08
  • NISHIMURA Takuma, MIZUNO Manabu, SUDA Yoshiyuki, SAKAI Yosuke, AKAZAWA Masamichi  電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan  1999-  317  -317  1999/09/08
  • Akazawa M., Amemiya Y.  Proceedings of the Society Conference of IEICE  1999-  (2)  25  -25  1999/08/16
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the Society Conference of IEICE  1999-  (2)  103  -103  1999/08/16
  • FUJIWARA T., AKAZAWA M., AMEMIYA Y.  Technical report of IEICE. VLD  99-  (107)  109  -116  1999/06/10  
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem, is designed.
  • TOKUDA E., ASAHI N., AKAZAWA M., AMEMIYA Y.  IEICE technical report. Neurocomputing  98-  (674)  77  -82  1999/03/19  
    The quantum Hopfield network is a kind of recurrent neural network that can always converge to the global minimum state without being stuck in local minima. This property is obtained by utilizing the co-tunneling phenomenon in quantum systems. This paper proposes a method of constructing the quantum Hopfield network by using single-electron circuits. The operation of the single-electron quantum Hopfield network is analized by computer simulation, assuming an instance of combinatrial optimization problems. It is demonstrated that, starting with a given initial state, the network can converge to the minimum energy state that represents the correct solution to the problem.
  • YAMADA Takashi, AKAZAWA Masamichi, AMEMIYA Yoshihito  IEICE technical report. Neurocomputing  98-  (673)  115  -120  1999/03/18  
    This paper proposes to create Boltzmann Machine device by using single-electron circuits. The Boltzmann machine is a kind of recurrent neural network that can solve various problems in subject such as combinational optimization. It is difficult for presently available electronic circuits to implement the generation of randomness for the stochastic neuron operation. We can construct the stochastic neuron device concisely by using single-electron circuits and, thereby, can implement the Boltzmann machine on an LSIs.
  • Koutani M., Akazawa M., Amemiya Y.  Proceedings of the IEICE General Conference  1999-  (2)  143  -143  1999/03/08
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the IEICE General Conference  144  -144  1999
  • ASAHI Noboru, YAMADA Takashi, AKAZAWA Masamichi, AMEMIYA Yoshihito  Technical report of IEICE. SCE  98-  (399)  43  -50  1998/11/16  
    A 32-bit adder circuit is designed using single-flux-quantum (SFQ) circuits, on the basis of the binary decision diagram (BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. We here construct a high-speed SFQ adder circuit based on a BDD representation simplified by the method of isomorphic-subgraph substitution. To construct the adder circuit compactly, we propose the BDD device that can be driven by SFQ signal. It is shown by computer simulation that the operation speed of the designed 32-bit adder is 350ps.
  • ASAHI Noboru, AKAZAWA Masamichi, AMEMIYA Yoshihito  Proceedings of the Society Conference of IEICE  1998-  (2)  28  -28  1998/09/07
  • FUKASAWA Yoshiyuki, AKAZAWA Masamichi, AMEMIYA Yoshihito  Proceedings of the Society Conference of IEICE  1998-  (2)  127  -127  1998/09/07
  • YAMADA Takashi, AKAZAWA Masamichi, AMEMIYA Yoshihito  Proceedings of the Society Conference of IEICE  1998-  7  -7  1998/09/07
  • TOKUDA E., ASAHI N., AKAZAWA M., AMEMIYA Y.  Proceedings of the Society Conference of IEICE  1998-  8  -8  1998/09/07
  • ASAHI Noboru, AKAZAWA Masamichi, AMEMIYA Yoshihito  Technical report of IEICE. SCE  98-  (222)  49  -56  1998/07/28  
    This paper proposes the single-flux-quantum logic circuit based on the binary decision diagram(BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. By implementing BDDs with single-flux-quantum circuits, we can create various logic systems that are capable of high speed operation.Construction and operation of an 8-bit adder is presented as an example.
  • AKAZAWA M., AMEMIYA Y.  IEICE technical report. Neurocomputing  97-  (624)  265  -271  1998/03/20  
    The Hopfield network is a computation model for solving combinatorial optimization problems through the use of the specific feedback network. The feedback network changes its internal state to minimize the energy function. Thus we can obtain the solution to the given problem by relating the cost function of the problem to the energy function of the network and by observing how the network settles down to the minimum energy state. Owing to the existence of local minima in the energy function, however, we cannot always be certain of obtaining the correct solution to the problem. To overcome this difficulty, the author proposes the idea that a novel Hopfield network, free from the local-minimum problem, can be attained by constructing the feedback network using single-electron circuits. In the single-election circuit, a phenomenon exists called "cotunneling", in which two or more tunnelings occur simultaneously as a coherent coupling. Using this phenomenon, we can construct a "quantum Hopfield network" in which the transition of a Hamming distance of more than two is possible.
  • Fukasawa Yoshiyuki, Akasawa Masamichi, Amemiya Yoshihito  Proceedings of the IEICE General Conference  1998-  (2)  201  -201  1998/03/06
  • IWAMURA Hiroki, AKAZAWA Masamichi, AMEMIYA Yoshihito  Technical report of IEICE. SDM  97-  (273)  39  -44  1997/09/26  
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated.
  • Asahi Noboru, Akazawa Masamichi  Proceedings of the Society Conference of IEICE  1997-  (2)  77  -77  1997/08/13  
    単電子回路では、輸送電荷の離散性とクーロンブロッケード現象とが相まって、通常の電子回路には見られない様々な特性が現れる。そのためCMOS回路では得られない種々の機能が実現可能となる。たとえば、インバータ回路を例にとってパラメータ探索を行ったところ、入出力の伝達特性がステップ的に変化する「ステップインバータ」の機能が得られることが判明した。これは、しきい論理回路や多値論理回路を低電力設計するときに不可欠のものである。以下に結果を報告する。
  • Nitta Hidehiko, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the Society Conference of IEICE  1997-  (2)  131  -131  1997/08/13  
    単電子回路を用いてCMOS型の論理回路が構成されており, 擬似CMOS型単電子回路と呼ばれている. ところで, 単電子回路の性質を上手に利用すれば, 本来のCMOSにはない新しい機能を付加することができる. ここでは, 入力の組合わせにより論理を切り換えられる可変論理デバイスを提案する.
  • Yamada Takashi, Iwamura Hiroki, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the Society Conference of IEICE  1997-  (2)  135  -135  1997/08/13  
    決定グラフとはディジタル論理を有向グラフで表す手法であり、論理設計や論理検証などのCADで使われている。本研究では、多値論理の決定グラフ(MDD:Multiple-valued Decision Diagram)を実際のデバイスで構成することを提案する。具体例として、4値論理MDDをシリコン機能デバイスのνMOSで構成してみた。加算器を例にとってシミュレーション解析を行い、正しい論理動作を確認した。以下に結果を述べる
  • IKEBE Masayuki, Honma Kunihiko, Akazawa Masamichi, AMEMIYA Yoshihito  Proceedings of the Society Conference of IEICE  1997-  (2)  134  -134  1997/08/13  [Not refereed][Not invited]
     
    νMOSインバータは、多入力しきい論理に適したデバイスである。これを用いると画像処理用セルオートマトン回路をコンパクトに構成できる。しかし、しきい論理回路ではνMOSをオンとオフの中間状態で使うことが多く、そのため貫通電流を生じて消費電力が大きくなりやすい。 ここではνMOS回路の低電力設計を考える。雑音除去・輪郭抽出セルオートマトン回路を例にとり、ダイナミック形と高しきい値MOS形の2つの構成法によって低電力設計行った。以下にその詳細を示す。
  • AKAZAWA M., ASAHI N., AMEMIYA Y.  IEICE technical report. Electron devices  96-  (573)  9  -16  1997/03/14  
    This paper proposes an idea of constructing single-electron logic circuits based on the binary-decision diagram (BDD). The proposed unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting the identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for elemental logic circuits (NAND, NOR, XOR) and combinational logic circuits (a four-variable logic circuit and a 4-bit adder). Computer simulation shows that the designed circuits perform the logic operations correctly.
  • Fukasawa Yoshiyuki, Akazawa Masamichi, Amemiya Yoshihito  Proceedings of the IEICE General Conference  1997-  (2)  192  -192  1997/03/06  
    二分決定グラフ(BDD)は, ブール代数式や真理値表とは異なる方法, 有向グラフによってディジタル論理を表す手法である。もともと論理設計や論理検証に使われていたが, 最近になって実際のデバイスでBDD論理を組むという研究が報告されるようになった。ここでは, BDDの適用範囲をアナログに拡大することを提案する。これによって新しい応用が生まれる可能性がある。
  • Akasawa Masamichi, Amemiya Yoshihito  Proceedings of the IEICE General Conference  1997-  (2)  196  -196  1997/03/06  
    単電子現象は本質的に離散現象なので, それを利用した単電子回路も本来はデジタル論理に適したものである。しかしアナログ回路の開発も将来に向けて必要とされる。ここでは電子密度変調によるアナログ表現法を提案し, そのための回路構成を考えてみた。
  • Akazawa Masamichi, Amamiya Yoshihito  Proceedings of the Society Conference of IEICE  1996-  (2)  253  -254  1996/09/18  
    量子セルの近接相互作用を利用したセルオートマトン(QCA)が提案されている。しかしこれまでのところセル配列の静的な安定状態を考察するに留まり、システム全体として動作するかどうかは理論的にも実験的にも検証されていない。そこで著者は種々の観点からその動作可能性を検討し、アニーリングによる駆動を行えばシステム動作が可能であろう、との予測を行った。
  • Aoki Takahiro, Akazawa Masamichi, Tazawa Satoshi  Proceedings of the Society Conference of IEICE  1996-  (2)  127  -127  1996/09/18  
    計算機上でプロセス・デバイス・回路をシミュレートし、デバイスの特性を予測するTechnology CAD技術は短TATな製造技術の開発に必要である。特性予測をより正確に行うには地道な実験データの蓄積とモデリングが必須である。一般にpチャネルMOSFETにおいて、nウェル形成用の燐ドーパントにはパイルアップ現象があることが知られており、この現象を取り扱っていない従来のシミュレータでは、デバイス特性予測を大きく狂わすことが知られている。また、SiO2-Si界面において酸化工程、アニール工程後の燐ドーパントの再分布(偏析)があることも一般的に知られている。本報告では、燐ドーパントのパイルアップ現象をモデル化し、種々のプロセス水準に対するpチャネルMOSFETのしきい値電圧の実測結果と比較した結果を述べる。
  • AMEMIYA Yoshihito, AKAZAWA Masamichi  應用物理  64-  (8)  765  -768  1995/08/10
  • 佐々木 恵二, 赤沢 正道, 塩原 俊助, 長谷川 英機  Bulletin of the Faculty of Engineering,Hokkaido University  (170)  p35  -43  1994/07
  • 大植 英司, 赤沢 正道, 児玉 聡, 長谷川 英機  Bulletin of the Faculty of Engineering,Hokkaido University  (156)  p51  -58  1991/07
  • Uraie Atsuhiro, Akazawa Masamichi, Hasegawa Hideki  Research reports, Kushiro Technical College  24-  53  -58  1990/12/20

Books etc

  • 第2版 応用物理ハンドブック 応用物理学会編
    Masamichi Akazawa (Contributor第9章 半導体デバイス 9.12半導体センサとトランスデューサ 9.12.1 磁電効果デバイス, p.643; 9.12.2 熱電効果デバイス, p.644; 9.12.4 放射線検出デバイス, p.645.)
    Maruzen 2002/04
  • 電子情報通信ハンドブック 6-13編 新概念集積回路
    雨宮好仁, 宮永喜一, 赤澤正道 (Contributorpp. 808 - 814)
    オーム社 1998/06

Presentations

  • Yining Jiao, Takahide Nukariya, Umi Takatsu, Taketomo Sato, Masamichi Akazawa
    16th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials / 17th International Conference on Plasma-Nano Technology & Science / 13th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (ISPlasma2024/IC-PLANTS2024/APSPT-13, Nagoya University, Nagoya, Japan, March 3–7, 2024)  2024/03
  • Y. Hatakeyama, Y. Luo, G. Shindo, M. Akazawa
    International Conference on Materials and Systems for Sustainability (ICMaSS2023, Nagoya University, Nagoya, Japan, December 1-3, 2023)  2023/12
  • MOS interface technologies for high-power and high-frequency GaN transistors (invited)  [Invited]
    T. Hashizume, M. Akazawa
    14th International Conference on Nitride Semiconductors (ICNS-14, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, November 12-17, 2023)  2023/11
  • T. Nukariya, J. Yining, U. Takatsu, T. Sato, M. Akazawa
    14th International Conference on Nitride Semiconductors (ICNS-14, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, November 12-17, 2023).  2023/11
  • Y. Hatakeyama, G. Shindo, Y. Luo, M. Akazawa
    14th International Conference on Nitride Semiconductors (ICNS-14, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, November 12-17, 2023).  2023/11
  • Photoelectrochemical etching of AlGaN/GaN heterostructures and control of reaction rates
    T. Togashi, Y. Oki, Y. Osawa, R. Ochi, M. Akazawa, T. Sato
    2023 JSAP Fall Meeting  2023/09
  • Takahide Nukariya, Jiao Yining, Umi Takatsu, Taketomo Sato, Masamichi Akazawa
    2023 JSAP Fall Meeting  2023/09
  • Yuki Hatakeyama, Masamichi Akazawa
    2023 JSAP Fall Meeting  2023/09
  • Influence of solution pH on Contactless-Photoelectrochemical (CL-PEC) etching of GaN  [Not invited]
    Y. Osawa, M. Akazawa, T. Sato
    2023 JSAP Fall Meeting  2023/09
  • Assessment of effects of 850℃ annealing on surface and bulk defects of Mg-ion implanted GaN using MOS structure  [Not invited]
    Genta Shindo, Yuki Hatakeyama, Masamichi Akazawa
    2023 JSAP Fall Meeting  2023/09
  • Yuliu Luo, Yuki Hatakeyama, Masamichi Akazawa
    2023 JSAP Fall Meeting  2023/09
  • Jiao Yining, Takahide Nukariya, Masamichi Akazawa
    2023 JSAP Fall Meeting  2023/09
  • M. Akazawa, Y. Luo, Y. Hatakeyama
    21st International Workshop on Junction Technology (IWJT2023, Kyoto University, Kyoto, Japan, June 8-9, 2023)  2023/06  Kyoto University, Kyoto, Japan  JSAP
  • Effects of PEC etching for Fermi-level pinning in AlGaN/GaN HEMTs  [Not invited]
    Ryota Ochi, Takuya Togashi, Yoshito Osawa, Fumimasa Horikiri, Noboru Fukuhara, Masamichi Akazawa, Taketomo Sato
    2023 JSAP Spring Meeting  2023/03
  • akahide Nukariya, Yuya Tamamura, Kouta Kubo, Umi Takatsu, Taketomo Sato, Masamichi Akazawa
    2023 JSAP Spring Meeting  2023/03
  • Yuki Hatakeyama, Masamichi Akazawa, Tetsuo Narita, Michal Bockowski, Tetsu Kachi
    2023 JSAP Spring Meeting  2023/03
  • Y. Hatakeyama, M. Akazawa, T. Narita, M. Bockowski, T. Kachi
    15th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials/ 16th International Conference on Plasma-Nano Technology & Science (ISPlasam2023/IC-PLANTS2023, Gifu University, Gifu, Japan, March 5–9, 2023)  2023/03  Gifu
  • M. Akazawa, T. Nukariya, Y. Tamamura, K. Kubo, T. Sato
    2022 Internationa Workshop on Nitride Semiconductors (IWN2022)  2022/10  Berlin
  • Interface control of GaN MOS structures for power transistors  [Invited]
    T. Hashizume, M. Akazawa
    2022 JSAP Fall Meeting Symposium  2022/09  仙台市
  • Takahide Nukariya, Yuya Tamamura, Kouta Kubo, Taketomo Sato, Masamichi Akazawa
    2022 JSAP Fall Meeting  2022/09
  • Yuya Tamamura, Takahide Nukariya, Masamichi Akazawa
    2022 JSAP Fall Meeting  2022/09  仙台市
  • Yuya Tamamura, Takahide Nukariya, Masamichi Akazawa
    2022 JSAP Spring Meeting  2022/03  相模原市
  • Y. Tamamura, T. Nukariya, M. Akazawa
    14th International Symposium on Advanced Science and its Application for Nitrides and Nanomaterials/15th International Conference on Plasma Nanotechnology and Science (ISPlasam2022/IC-PLANTS2022)  2022/03
  • M. Akazawa, Shunta Murai, Yuya Tamamura
    31th International Conference on Defects in Semiconductors (ICDS 2017)  2021/07
  • M. Akazawa, Yuya Tamamura, S. Murai
    13th International Symposium on Advanced Science and its Application for Nitrides and Nanomaterials/14th International Conference on Plasma Nanotechnology and Science (ISPlasam2021/IC-PLANTS2021)  2021/03
  • Shunta Murai, Encheng Wu, Masamichi Akazawa, Tetsu Kachi
    2020 JSAP Meeting  2020/09  online
  • M. Akazawa, S. Murai, R. Kamoshida, E. Wu, T. Kachi
    62nd Electronic Materials Conference (EMC2020, Virtual Holding, June 24-26, 2020)  2020/06
  • Effects of Long-Term Low-Temperature Annealing on Mg-Ion Implanted GaN  [Not invited]
    Shunta Murai, Ryo Kamoshida, M. Akazawa
    The 9th Asia-Pacific Workshop on Widegap Semiconductors (APWS2019, Okinawa Institute of Science and Technology Graduate University, Okinawa, Japan, Nov. 10 – 15, 2019).  2019/11
  • Effects of Surface Oxide Reduction Prior to Metallization on Electrical Properties of GaN-on-GaN Schottky Diodes  [Not invited]
    K. Isobe, M. Akazawa
    The 9th Asia-Pacific Workshop on Widegap Semiconductors (APWS2019, Okinawa Institute of Science and Technology Graduate University, Okinawa, Japan, Nov. 10 – 15, 2019).  2019/11
  • XPS Study on Plasma Oxide Layer of InAlN  [Not invited]
    Yuya Kitawaki, Masamichi Akazawa
    The 80th JSAP Autumn Meeting 2019  2019/09
  • Effects of Long-Term Low-Temperature annealing on Mg-Ion Implanted GaN  [Not invited]
    Shunta Murai, Ryo Kamoshida, Masamichi Akazawa
    The 80th JSAP Autumn Meeting 2019  2019/09
  • Analysis of Interface-State Admittance of MOS Diodes Constructed of Mg-Ion-Implanted GaN  [Not invited]
    Ryo Kamoshida, Shunta Murai, Masamichi Akazawa
    The 80th JSAP Autumn Meeting 201809  2019/09
  • Impact of Photolithography Development Process on GaN Schottky Barrier Diode  [Not invited]
    Kazuki Isobe, Masamichi Akazawa
    The 80th JSAP Autumn Meeting 2019  2019/09
  • Effects of Deep Level States Generated by Mg-Ion Implantation on Electrical Properties of GaN MOS Diodes before Activation Annealing  [Not invited]
    R. Kamoshida, S. Murai, M. Akazawa
    2019 International Conference on Solid State Devices and Materials (SSDM2019, Nagoya University, Nagoya, Japan, Sept. 2 – 5, 2019)  2019/09
  • Detection of Deep Level States Generated in GaN by Mg-Ion Implantation Using Conductance Method for MOS Diodes  [Not invited]
    M. Akazawa, R. Kamoshida
    13th International Conference on Nitride Semiconductors (ICNS-13, Hyatt Regency Bellevue, Bellevue, Washington, USA, July 7-12, 2019)  2019/07
  • Investigation of Impact of Dosage on Electrical Properties of Mg-Ion-Implanted GaN before Activation Annealing Using MOS Structures  [Not invited]
    Ryo Kamoshida, Kei Uetake, Shunta Murai, Masamichi Akazawa
    Compound Semiconductor Week 2019 (CSW219, Kasugano International Forum, Nara, Japan, May 19 – 23, 2019)  2019/05
  • Control of SiO2/InAlN Interface by Plasma Surface Oxidation  [Not invited]
    Shouhei Kitajima, Masamichi Akazawa
    11th International Symposium on Advanced Science and its Appliaction for Nitrides and Nanomaterials/12th International Conference on Plasma-Nano Technology & Science (ISPlasam2019/IC-PLANTS2019, Nagoya Institute of Technology, Nagoya, Japan, March 17-20)  2019/03
  • Impact of Dosage on Electrical Properties of Mg-Ion-Implanted GaN before High-Temperature Annealing (2)  [Not invited]
    Ryo Kamoshida, Kei Uetake, Shunta Murai, Masamichi Akazawa
    The 66th JSAP Spring Meting 2019  2019/03
  • Impact of Surface Treatment on GaN-on-GaN Schottky Barrier Diode  [Not invited]
    Kazuki Isobe, Masamichi Akazawa
    The 66th JSAP Spring Meeting 2019  2019/03
  • Investigation of Effect of Low-Temperature Annealing and Dosage on Mg-Ion-Implanted GaN Using MOS Structure  [Not invited]
    Kei Uetake, Ryo Kamoshida, Masamichi Akazawa
    International Workshop on Nitride Semiconductors 2018 (IWN2018, Kanazawa, Ishikawa, Japan, November 11 - 16, 2018)  2018/11
  • Investigation of Surface Pretreatment for Schottky Contacts on n-GaN on GaN Substrate  [Not invited]
    Kazuki Isobe, Masamichi Akazawa
    14th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures (ACSIN-14) in conjunction with 26th International Colloquium on Scanning Probe Microscopy (ICSPM26)  2018/10
  • Control of SiO2/InAlN Interface Using Sub-nm-Thick Al2O3 Interlayer  [Not invited]
    Shouhei Kitajima, Masamichi Akazawa
    14th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures (ACSIN-14) in conjunction with 26th International Colloquium on Scanning Probe Microscopy (ICSPM26)  2018/10
  • Investigation of Lightly Mg-Ion-Implanted GaN Using MOS Structure  [Invited]
    Masamichi Akazawa, Kei Uetake, Ryo Kamoshida
    The 79th JSAP Autumn Meeting, 2018  2018/09
  • Properties of SiO2/InAlN interface having ultrathin Al2O3 interlayer (2)  [Not invited]
    Shouhei Kitajima, Masamichi Akazawa
    The 79th JSAP Autumn Meeting, 2018  2018/09
  • Impact of Dosage on Electrical Properties of Mg-Ion-Implanted GaN before High-Temperature Annealing  [Not invited]
    Ryo Kamoshida, Kei Uetake, Masamichi Akazawa
    The 79th JSAP Autumn Meeting, 2018  2018/09
  • Impact of Surface Treatment for GaN on Surface Fermi Level Position and Metal-Work-Function Dependence of Schottky Barrier Height  [Not invited]
    Kazuki Isobe, Masamichi Akazawa
    The 79th JSAP Autumn Meeting, 2018  2018/09
  • Thermal behavior of defects generated in GaN by low-dose Mg-ion implantation  [Not invited]
    Masamichi Akazawa, Naoshige Yokota, Kei Uetake
    Compound Semiconductor Week 2018  2018/05
  • Change in electrical properties of Mg-ion implanted GaN by annealing (2)  [Not invited]
    Kei uetake, Naoshige Yokota, Masamichi Akazawa
    The 65th JSAP Spring Meeting, 2018  2018/03
  • Properties of SiO2/InAlN interface having plasma oxide interlayer  [Not invited]
    Shouhei Kitajima, Masamichi Akazawa
    The 65th JSAP Spring Meeting, 2018  2018/03
  • Properties of SiO2/InAlN interface having Al2O3 and plasma oxide ultra thin interlayer  [Not invited]
    Shouhei Kitajima, Masamichi Akazawa
    The 53th JSAP Hokkaido Branch Annual Meeting  2018/01
  • Properties of SiO2/InAlN interface having ultrathin Al2O3 interlayer  [Not invited]
    S. Kitajima, M. Akazawa
    The 78th JSAP Autum Meeting, 2017  2017/09
  • Change in electrical properties of Mg-ion implanted GaN by annealing  [Not invited]
    N. Yokota, K. Uetake, M. Akazawa
    The 78th JSAP Autum Meeting, 2017  2017/09
  • Change in properties of GaN Schottky barrier diodes by insertion of ultrathin insulator layers  [Not invited]
    T. Hasezaki, M. Akazawa
    The 78th JSAP Autum Meeting, 2017  2017/09
  • Measurement of Electronic States Generated in GaN by Mg Ion Implantation  [Not invited]
    N. Yokota, K. Uetake, M. Akazawa
    29th International Conference on Defects in Semiconductors (ICDS 2017, Matsue, Shimane, Japan, July 31 – Aug. 4, 2017)  2017/07
  • Modification of Fermi-level pinning at metal/GaN interface by inserting ultrathin Al2O3 interlayers  [Not invited]
    M. Akazawa, T. Hasezaki
    12th International Conference on Nitride Semiconductors (ICNS-12, Strasbourg, France, July 24-28, 2017)  2017/07
  • Properties of SiO2/InAlN interface with Al2O3 ultrathin interlayers  [Not invited]
    A. Seino, M. Akazawa
    The 64th JSAP Spring Meeting, 2017  2017/03
  • Electrical characterization of electron levels generated in GaN by Mg ion implantation  [Not invited]
    N. Yokota, M. Akazawa
    The 64th JSAP Spring Meeting, 2017  2017/03
  • Change of GaN Schottky barrier height by insertion of ultrathin Al2O3 layers  [Not invited]
    T. Hasezaki, M. Akazawa
    The 64th JSAP Spring Meeting, 2017  2017/03
  • Reduction of Interface State Density at SiO2/InAlN Interface by Inserting Ultrathin Interlayers  [Not invited]
    M. Akazawa, A. Seino, N. Yokota, T. Hasezaki
    International Workshop on Nitride Semiconductors 2016 (IWN2016, Hilton Orlando Lake Buena Vista, Orlando, Florida, USA, October 2 - 7, 2016)  2016/10
  • Properties of SiO2/InAlN Interface with Plasma Oxide Interlayer  [Not invited]
    Atsushi Seino, Naoshige Yokota, Masamichi Akazawa
    The 77th JSAP Autumn Meeting, 2016  2016/09
  • Effect of Insertion of Al2O3 Ultrathin Layer into PECVD SiO2/InAlN Interface  [Not invited]
    A. Seino, T. Hasezaki, N. Yokota, M. Akazawa
    The 63rd JSAP Spring Meeting, 2016  2016/03
  • Characterization of Surfaces and Interfaces of InAlN  [Not invited]
    Masamichi Akazawa
    2016 RCIQE International Seminar  2016/03
  • Nature and Origin of Interface States at Dielectric/III-N Heterojunction Interfaces  [Not invited]
    Maciej Matys, Boguslawa Adamowicz, Roman Stoklas, Masamichi Akazawa, Zenji Yatabe, Tamotsu Hashizume
    2015 MRS Fall Meeting & Exhibit  2015/11
  • Characterization of SiO2/InAlN Interface Formed by Plasma Enhanced CVD  [Not invited]
    A. Seino, M. Akazawa
    The 76th JSAP Fall Meeting  2015/09
  • [Invited] Characterization of Surfaces and Interfaces of InAlN/GaN Heterostructures  [Not invited]
    M. Akazawa, T. Hashizume
    11th International Conference on Nitride Semiconductors (ICNS-11, Beijing, China, Aug. 30 - Sept. 4, 2015)  2015/08
  • Process Dependence of Al2O3/InAlN Interface Properties  [Not invited]
    M. Chiba, M. Akazawa
    The 62nd JSAP Spring Meeting  2015/03
  • Application of Al2O3/InAlN interface formed by 2-step ALD to MOSHEMT  [Not invited]
    Y. Odanagi, M. Akazawa, J. T. Asubar, Z. Yatabe, T. Hashizume
    The 75th JSAP Fall Meeting  2014/09
  • Impact of Annealing on Properties of ALD Al2O3/InAlN Interfaces  [Not invited]
    M. Akazawa, T. Nakano, M. Chiba
    56th Electronic Materials Conference (EMC56, UCSB, Santa Barbara, California, USA, June 25-27, 2014)  2014/06
  • Process-dependent properties of InAlN surface and ALD-Al2O3/InAlN interface  [Not invited]
    M. Akazawa, M. Chiba, T. Nakano
    2014 International Conference on Compound Semiconductor Manufacturing Technology (CSMANTECH 2014, Sheraton Downtown Denver, Denver, Colorado, USA, May 19-22, 2014)  2014/05
  • Properties of Al2O3/InAlN interface formed by 2-step ALD  [Not invited]
    T. Nakano, M. Chiba, Y. Odanagi, M. Akazawa
    The 61st JSAP Spring Meeting  2014/03
  • Effect of annealing on properties of InAlN MOS diodes with ALD-Al2O3 insulator layer  [Not invited]
    M. Chiba, T. Nakano, M. Akazawa
    The 61st JSAP Spring Meeting  2014/03
  • [Invited] Characterization and control of GaN-based heterointerfaces  [Invited]
    T. Sato, M. Akazawa, T. Hashizume
    The 61st JSAP Spring Meeting  2014/03
  • Investigation of High-Temperature Annealed ALD-Al2O3/InAlN Interface  [Not invited]
    M. Akazawa, T. Nakano, M. Chiba
    12th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures in conjunction with 21st International Conference on Scanning Probe Microscopy (ACSIN-12 & ICSPM21, Tsukuba, Japan, November 4 - 8, 2013)  2013/11
  • Effects of Fabrication Process on Electrical Properties of InAlN MOS Structures with ALD-Al2O3  [Not invited]
    M. Chiba, T. Nakano, M. Akazawa
    The Technical Committee on Electron Devices, IEICE, JAPAN  2013/10
  • Effects of High-Temperature Annealing on Properties of Al2O3/InAlN Interface Formed by Atomic Layer Deposition  [Not invited]
    T. Nakano, M. Chiba, M. Akazawa
    2013 International Conference on Solid State Devices and Materials (SSDM2013, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, Sept. 25-27, 2013)  2013/09
  • Study on Fabrication Sequence of InAlN MOS Diodes with ALD-Al2O3 Insulator Layer  [Not invited]
    M. Chiba, T. Nakano, M. Akazawa
    The 74th JSAP Fall Meeting  2013/09
  • Improvement of Al2O3/InAlN interface properties through two-step ALD process interrupted by high-temperature annealing  [Not invited]
    T. Nakano, M. Chiba, M. Akazawa
    The 74th JSAP Fall Meeting  2013/09
  • Dependence of ALD-Al2O3/InAlN interface properties on fabrication process  [Not invited]
    T. Nakano, M. Chiba, M. Akazawa
    10th International Conference on Nitride Semiconductors (ICNS-10, Washington, DC, Aug. 25-30, 2013)  2013/08
  • Characterization and Control of insulated Gate Interface on GaN-Based heterostructures (invited)  [Invited]
    T. Hashizume, M. Akazawa
    2013 International Conference on Compound Semiconductor Manufacturing Technology, p.329-332 (CS MANTEC2013, Hilton New Orleans Riverside, New Orleans, Louisiana, USA, May 13-16, 2013)  2013/05
  • Effect of annealing on ALD-Al2O3/InAlN interface  [Not invited]
    T. Nakano, M. Akazawa
    JSAP Srping Meeting, 2013  2013/03
  • Characterization and control of surfaces and interfaces of InAlN/GaN heterostructures  [Invited]
    M. Akazawa, T. Hashizume
    The 60th JSAP Spring Meeting, 2013  2013/03
  • Insulated gate technologies for high-performance GaN transistors (invited)  [Invited]
    T. Hashizume, Y. Hori, S. Kim, Z. Yatabe, M. Akazawa
    International Workshop on Nitride Semiconductors 2012 (IWN2012, Sapporo, Japan, October 14 - 19, 2012)  2012/10
  • Effects of surface treatment on InAlN investigated by X-ray photoelectron spectroscopy  [Not invited]
    M. Akazawa, T. Nakano
    International Workshop on Nitride Semiconductors 2012 (IWN2012, Sapporo, Japan, October 14 - 19, 2012)  2012/10
  • 中野拓真, 赤澤正道
    応用物理学会学術講演会講演予稿集(CD−ROM)  2012/08
  • HASHIZUME TAMOTSU, HORI YUJIN, AKAZAWA MASAMICHI
    電子情報通信学会技術研究報告  2012/07
  • 中野拓真, 赤澤正道
    応用物理学関係連合講演会講演予稿集(CD−ROM)  2012/02
  • Effect of hydrofluoric acid treatment on InAlN surfaces  [Not invited]
    T. Nakano, M. Akazawa
    2012 Asia-Pacific Workshop on Fundamental and Applications of Advanced Semiconductor Devices (AWAD2012, Naha, Okinawa, Japan, June 27-29, 2012)  2012/01
  • 赤澤正道, 赤澤正道, GAO B, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM)  2011/08
  • GAO B, 赤澤正道, 赤澤正道, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM)  2011/08
  • Optimum AlGaN Spacer Layer in Al2O3/InAlN/AlGaN/GaN Structures  [Not invited]
    M. Akazawa, B. Gao, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    9th International Conference on Nitride Semiconductors (ICNS-9, Glasgow, UK, July 10-15, 2011)  2011/07
  • GAO B, 赤澤正道, 赤澤正道, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学関係連合講演会講演予稿集(CD−ROM)  2011/03
  • 赤澤正道, 赤澤正道, GAO B, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学関係連合講演会講演予稿集(CD−ROM)  2011/03
  • Investigation of polarization-induced electric field in ultrathin InAlN films on GaN by X-ray photoelectron spectroscopy  [Not invited]
    M. Akazawa, B. Gao, T. Hashizume, M. Hiroki, S. Yamahata, N. Shigekawa
    International Workshop on Nitride Semiconductors 2010 (IWN2010, Tampa, Florida, USA, September 19 - 24, 2010)  2010/09
  • GAO MB, 赤澤正道, 赤澤正道, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM)  2010/08
  • 赤澤正道, 赤澤正道, GAO MB, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM)  2010/08
  • 赤澤正道, 赤澤正道, 橋詰保, 橋詰保, 廣木正伸, 山幡章司, 重川直輝
    応用物理学関係連合講演会講演予稿集(CD−ROM)  2010/03
  • MOS Interface Control on III-V High Mobility Channel Materials (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    37th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-35, Santa Fe, New Mexico, USA, January 10-14, 2010)  2010/01
  • Fermi level Pinning and Its Removal at III-V MOS Interfaces (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    40th IEEE Semiconductor Interface Specialists Conference (Key Bridge Marriott Hotel, Arlington, VA, USA, December 3-5, 2009)  2009/12
  • Surface Passivation of III-V Semiconductors for More Moore and Beyond CMOS Devices - present status and key issues – (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    6th International Workshop on Semiconductor Surface Passivation (Zakopane, Poland, September 13-18, 2009)  2009/09
  • Formation of High-k MOS Structures with Si Interface Control Layer on Air-Exposed GaAs and InGaAs Wafers  [Not invited]
    M. Akazawa, H. Hasegawa
    6th International Workshop on Semiconductor Surface Passivation (Zakopane, Poland, September 13-18, 2009)  2009/09
  • Slow Dispersive Hopping Transport of Electrons on Surfaces of AlGaN/GaN HEMTs and Planar Schottky Diodes  [Not invited]
    H. Hasegawa, M. Akazawa
    12th International Conference on the Formation of Semiconductor Interfaces (ICFSI-12, Weimar, Germany, July 5-10, 2009)  2009/07
  • Control of Interface between HfO2 and Air-Eexposed InGaAs by Ultrathin Si Interface Control Layer  [Not invited]
    M. Akazawa, H. Hasegawa
    12th International Conference on the Formation of Semiconductor Interfaces (ICFSI-12, Weimar, Germany, July 5-10, 2009)  2009/07
  • On the Frequency Dispersion of III-V MOS C-V Curves  [Not invited]
    H. Hasegawa, M. Akazawa
    33rd Workshop on Compound Semiconductor Device and Integrated Circuits held in Europe (WOCSDICE2009, Málaga, Spain, May 17-20, 2009)  2009/05
  • Anomalous Admittance Behavior of III-V Insulator-Semiconductor Interfaces and Its Mechanism  [Not invited]
    H. Hasegawa, M. Akazawa
    Symposium on Surface and Nano Science 2009 (SSNS’09, Shizukuishi Prince Hotel, Shizukuishi, Iwate, Japan, January 27-30, 2009)  2009/01
  • Current Collapse Transient Behavior and Its Mechanism in Submicron-Gate AlGaN /GaN Heterostructure Transistors  [Not invited]
    H. Hasegawa, M. Akazawa
    36th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-36, Santa Barbara, California, USA, January 11-15, 2009)  2009/01
  • Capacitance-Voltage and Photoluminescence Study of High-k /III-V Semiconductor Interfaces Controlled by Si Interface Control Layer  [Not invited]
    M. Akazawa, M. Miczek, B. Adamowicz, H. Hasegawa
    36th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-36, Santa Barbara, California, USA, January 11-15, 2009)  2009/01
  • Distributed Pinning Spot Model for High-k Insulator - III-V Semiconductor Interface  [Not invited]
    M. Akazawa, H. Hasegawa
    International Symposium on Surface Science and Technology (ISSS-5, Waseda University, Tokyo, Japan, November 9-13, 2008)  2008/11
  • Characterization and Control of Group-III Nitride Surfaces for Power Electronics and Sensor Electronics [invited]  [Invited]
    H. Hasegawa, M. Akazawa
    14th International Symposium on the Physics of Semiconductors and Applications (ISPSA2008, Jeju, Korea, August 26-29, 2008)  2008/08
  • Anomalous Behavior of Capacitance and Conductance of III-V Metal- Insulator- Semiconductor Capacitors  [Not invited]
    M. Akazawa, H. Hasegawa
    2008 Electronic Material Conference (EMC2008, University of California Santa Barbara, California, USA, June 25-27, 2008)  2008/06
  • Slow Response Instability in the Planar Pd Schottky Diode Hydrogen Sensor Formed on AlGaN/GaN Wafer  [Not invited]
    H. Hasegawa, M. Akazawa
    2008 Electronic Material Conference (EMC2008, University of California Santa Barbara, California, USA, June 25-27, 2008)  2008/06
  • Optimization of Si Interface Control Layer Thickness for High-k GaAs Metal-Insulator-Semiconductor Structures  [Not invited]
    M. Akazawa, H. Hasegawa
    9th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC2008, Lodz, Poland, June 1- 4, 2008)  2008/06
  • Control of Surfaces and Interfaces for III-V Semiconductor Nanoelectronics [invited]  [Invited]
    H. Hasegawa, M. Akazawa
    9th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC2008, Lodz, Poland, June 1- 4, 2008)  2008/06
  • SURFACE STATE EFFECTS AND SURFACE PASSIVATION WITH A SILICON INTERFACE CONTROL LAYER FOR III-V NANOWIRE TRANSISTORS  [Not invited]
    H. Hasegawa, M. Akazawa
    32nd Workshop on Compound Semiconductor Device and Integrated Circuits held in Europe (WOCSDICE2008, Leuven, Belgium, May 18-21, 2008)  2008/05
  • 長谷川英機, 赤澤正道
    応用物理学関係連合講演会講演予稿集  2008/03
  • 赤澤正道, 長谷川英機
    応用物理学関係連合講演会講演予稿集  2008/03
  • Interface Control of High-k MOS Gate Stack for GaAs nanowire Transistors  [Not invited]
    H. Hasegawa, M. Akazawa
    Symposium on Surface and Nano Science 2008 (SSNS’08, Appi-Kougen, Iwate, Japan, January 22-25, 2008)  2008/01
  • Steady State and Transient Behavior of Currents in Low-Leakage Planar Schottky Diodes Formed on AlGaN /GaN Heterostructures  [Not invited]
    H. Hasegawa, M. Akazawa
    35th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-35, Santa Fe, New Mexico, USA, January 13-17, 2008),  2008/01
  • Frequency Dispersion of GaAs High-k MIS Capacitors with Si Interface Control Layer  [Not invited]
    M. Akazawa, H. Hasegawa
    35th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-35, Santa Fe, New Mexico, USA, January 13-17, 2008)  2008/01
  • Silicon Interface Control Layer Based Surface Passivation Method and Related High-k MIS Gate Stack for GaAs Nanowire MISFETs  [Not invited]
    M. Akazawa, H. Hasegawa
    International Symposium on Advanced nanodevices and Nanotechnology (ISANN2007, Waikoloa, Hawaii, USA, December 2-7, 2007)  2007/12
  • GaAs High-k Dielectric MOS Structure Having Silicon Interface Control Layer  [Not invited]
    M. Akazawa, H. Hasegawa
    34th International Symposium on Compound Semiconductor (iscs2007, Kyoto, Japan, October 15-18, 2007)  2007/10
  • Dynamic behavior of metal contacts formed on AlGaN/GaN heterostructure  [Not invited]
    H. Hasegawa, M. Akazawa
    7th International Conference on Nitride Semiconductor (ICNS-7, Las Vegas, Nevada, USA, September 16-21, 2007)  2007/09
  • Sensing and current transport mechanisms of a high performance Pd/AlGaN/GaN Schottky diode hydrogen sensor  [Not invited]
    M. Akazawa, H. Hasegawa
    7th International Conference on Nitride Semiconductor (ICNS-7, Las Vegas, Nevada, USA, September 16-21, 2007)  2007/09
  • Interface Control Technology for Surface Passivation of III-V Semiconductor Nanostructures (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    5th International Workshop on Semiconductor Surface Passivation (Zakopane, CRC Geovita, Poland, September 16-19, 2007)  2007/09
  • 赤澤正道, 長谷川英機
    応用物理学会学術講演会講演予稿集  2007/09
  • 赤澤正道, 長谷川英機
    応用物理学会学術講演会講演予稿集  2007/09
  • Surface passivation technology for III-V semiconductor nanoelectronics (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    11th International Conference on the Formation of Semiconductor Interfaces (ICFSI-11, Manaus-Amazonas, Brazil, August 19-24, 2007)  2007/08
  • Complete Removal of Fermi Level Pinning at High-k Dielectric/GaAs (001) and (111)B Interfaces by a Silicon Interface Control Layer  [Not invited]
    M. Akazawa, H. Hasegawa
    2007 Electronic Material Conference (EMC2007, University of Notre Dame, South Bend, Indiana, USA, June 20-22, 2007)  2007/06
  • Performance Enhancement and Sensing Mechanism of Pd/AlGaN/GaN Hydrogen Sensors Subjected to Oxygen Gettering  [Not invited]
    H. Hasegawa, M. Akazawa
    2007 Electronic Material Conference (EMC2007, University of Notre Dame, South Bend, Indiana, USA, June 20-22, 2007)  2007/06
  • Passivation of III-V Surface by Si Interface Control Layer and Its Application of high-k MIS Gate Stack (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    Interntional Workshop on High-k Dielectrics on High Speed Channel Materials, Hinsiu, Taiwan, May 24-25, 2007  2007/05
  • MBE growth and in-situ XPS characterization of silicon interlayers for surfaces passivation of GaAs quantum devices  [Invited]
    M. Akazawa, H. Hasegawa
    2007 RCIQE International Seminar on "Advanced Semiconductor Materials and Devices," (Sapporo, Japan, February 8-9, 2007)  2007/02
  • Control of Schottky Interfaces of AlGaN/GaN system for hydrogen sensor applications (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    Symposium on Surface and Nano Science 2007 (SSNS’07, Appi-Kougen, Iwate, Japan, January 23-26, 2007)  2007/01
  • Hydrogen Response Characteristics and Mechanism of Pd/ AlGaN/ GaN Schottky Diodes Subjected to Oxygen Gettering  [Not invited]
    H. Hasegawa, M. Akazawa
    34th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-34, Salt Lake City, Utah, USA, January 14-18, 2007)  2007/01
  • Growth Mechanism and Fermi Level Unpinning in Silicon Interface Control Layers for Surface Passivation of (001) and (111) GaAs and AlGaAs Surfaces  [Not invited]
    M. Akazawa, H. Hasegawa
    34th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-34, Salt Lake City, Utah, USA, January 14-18, 2007)  2007/01
  • Understanding and Control of Group-III Nitride Surfaces for Power Electronics and Sensor Electronics (invited)  [Invited]
    H. Hasegawa, M. Akazawa
    5th Solid State Surfaces and Interfaces (SSSI2006, Smolenice Castle, Slovak Republic, November 19-24, 2006)  2006/11
  • Sensing Dynamics and Mechanism of a Pd/AlGaN /GaN Schottky Diode Type Hydrogen Sensor  [Not invited]
    H. Hasegawa, M. Akazawa
    2006 International Workshop on Nitride Semiconductors (IWN2006, Kyoto, Japan, October 22-27, 2006)  2006/10
  • MBE Growth and In-Situ XPS Characterization of Silicon Interlayers on (111)B Surfaces for Passivation of GaAs Quantum Wire Devices  [Not invited]
    M. Akazawa, H. Hasegawa
    14th International Conference on Molecular Beam Epitaxy (MBE2006, Tokyo, Japan, September 3-8, 2006)  2006/09
  • Characterization and Control of AlGaN Schottky Diodes for Performance Enchancement of Hydrogen Sensors  [Not invited]
    H. Hasegawa, K. Matsuo, T. Kimura, J. Kotani, M. Akazawa, T. Hashizume
    8th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC'06, Cádiz, Spain, May 14- 17, 2006)  2006/05
  • In-situ X-ray photoelectron spectroscopy characterization of Si interlayer based surface passivation process for AlGaAs/GaAs quantum wire transistors  [Not invited]
    M. Akazawa, H. Hasegawa, R. Jia
    8th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC'06, Cádiz, Spain, May 14- 17, 2006)  2006/05
  • THz Transmission Properties of Metal Hole-Array Filters  [Not invited]
    Y. Yamazaki, M. Akazawa, E. Sano
    2006 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (IV)" (Sapporo, February 9-10, 2006)  2006/02
  • X-ray Photoelectron Spectroscopy Study of Silicon Interlayer Based Passivation for GaAs and AlGaAs (111) B Surfaces  [Not invited]
    M. Akazawa, N. Shiozaki, H. Hasegawa
    2006 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (IV)" (Sapporo, February 9-10, 2006)  2006/02
  • X-ray Photoelectron Spectroscopy Study of Silicon Interlayer Based Surface Passivation for AlGaAs/GaAs Quantum Structures on (111) B Surfaces  [Not invited]
    M. Akazawa, N. Shiozaki, H. Hasegawa
    10th International Conference on the Formation of Semiconductor Interfaces (ICFSI-10, Aix-en-Provence, France, July 3-8, 2005)  2005/07
  • Precisely Controlled Anodic Etching for Processing of GaAs-based Quantum Nanostructures and Devices  [Not invited]
    N. Shiozaki, T. Sato, M. Akazawa, H. Hasegawa
    10th International Conference on the Formation of Semiconductor Interfaces (ICFSI-10, Aix-en-Provence, France, July 3-8, 2005)  2005/07
  • AKAZAWA Masamichi, SHIOZAKI Nanako, SATO Taketomo, HASEGAWA Hideki
    IEICE technical report. Electron devices  2005/06 
    We attempted to apply a Si-interface-control-layer (Si ICL)-based surface passivation method to the surfaces of quantum structures fabricated on GaAs(111)B substrates. The sample surfaces were investigated by an XPS study at each step of the fabrication process, and fabricated quantum structures were characterized by PL measurements. Shifts of surface Fermi level positions toward the conduction band edges at GaAs and AlGaAs(111)B surfaces were observed after the Si ICL formation. PL intensities reduced with reduction of distances between quantum structures and their surfaces. The surface pa...
  • MBE Growth and Si-interlayer Based Surface Passivation of GaAs Quantum Wires  [Not invited]
    N. Shiozaki, T. Sato, M. Akazawa, H. Hasegawa
    29th Workshop on Compound Semiconductor Device and Integrated Circuits held in Europe (WOCSDICE2005, May 16-18, 2005, Cardiff)  2005/05
  • YAMAZAKI Yusuke, INAFUNE Koji, AKAZAWA Masamichi, SANO Eiichi
    IEICE technical report. Electron devices  2005/02 
    A periodic structure in a subterahertz coplanar stripline (CPS) was fabricated on a low-temperature-grown GaAs (LT-GaAs) layer in order to achieve an electromagnetic bandgap (EBG). To optimize dimension of structures, we used the finite-difference-time-domain (FDTD) method for the full-wave analysis. In consequence, we found that the thickness of the metal layer affects the characteristic of EBGs. Take into account this result, the sample structure was designed, fabricated, and characterized by the photoconductive sampling (PCS). Two bandgaps and an intermediate passband were observed in th...
  • Transmission Characteristics of THz Perfect-Conductor PerforatedPlate Filters with Two-Dimensional Periodic Holes  [Not invited]
    T. Tanaka, M. Akazawa, E. Sano
    2005 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III)" (Sapporo, February 8-10, 2005)  2005/02
  • Photoconductive Sampling of Electromagnetic Periodic Structures in Subterahertz Coplanar Striplines  [Not invited]
    Y. Yamazaki, K. Inafune, M. Akazawa, J. Motohisa, E. Sano
    2005 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III)" (Sapporo, February 8-10, 2005)  2005/02
  • Using FDTD Method to Design Millimeter-Wave Active Integrated Antena  [Not invited]
    K. Inafune, M. Akazawa, E. Sano
    2005 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III)" (Sapporo, February 8-10, 2005)  2005/02
  • TANAKA Takeshi, AKAZAWA Masamichi, SANO Eiichi
    IEICE technical report. Microwaves  2004/09 
    THz waves are expected to be applied to new technologies in several fields, and the developments of the devices in THz region are needed for the use. In this paper, we study on the structures of THz wave filters for microelectronics and the methods of designing filters by FDTD simulations. The transmission characteristics of meal-thin-film meshes are clearly based on surface plasmon-polaritons. However, other transmission characteristics mechanisms appear in the filters composed of metal-thin-film meshes cascaded at the both sides of a dielectric layer. We investigate the methods of control...
  • INAFUNE Koji, AKAZAWA Masamichi, SANO Eiichi
    IEICE technical report. Microwaves  2004/09 
    A numerical study of a method to reduce the radiation loss of a coplanar waveguide (CPW) is reported, and the application of the low-loss CPW to electromagnetic-bandgap (EBG) filters for the THz region is described. The finite-difference time-domain (FDTD) method was used for the full-wave analysis of CPWs and filters. It is expected that the radiation loss could be greatly reduced by constructing a CPW on a substrate consisting of a thin GaAs film reinforced with a thick backside insulator with a low dielectric constant. The application of the same substrate structure to a newly devised EB...
  • AKAZAWA Masamichi
    The transactions of the Institute of Electronics, Information and Communication Engineers. C  2003/07 
    単電子デバイスの準静的動作の極限において,消費電力がかからない無損失の,断熱的なスイッチング動作となることがあり得るかどうかについて考察した.通常,トランジスタに代表されるスイッチング素子においてはしきい値が存在し,そのしきい値において急激なエネルギー変化を伴うことから準静的動作による消費電力の低減には限界がある.しかし,単電子デバイスでは,デバイスの設計次第で,準静的な電圧変化に対して急激なエネルギー変化を伴わないスイッチングが可能である.本論文では,単電子デバイスの準静的動作について,その消費電力特性を数値計算により予測した結果を示す.
  • Possibility of Adiabatic Switching of Single-Electron-Devices  [Not invited]
    M. Akazawa
    2003 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies" (Sapporo, February 12-14, 2003)  2003/02
  • Electromagnetic Field Simulation of 2-Dimensional Polygon-Array Photonic Crystals  [Not invited]
    M. Akazawa, T. Tanaka, K. Inafune, E. Sano
    2003 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies" (Sapporo, February 12-14, 2003)  2003/02
  • Properties of Electronic States at Free Surfaces and Schottky Barrier Interfaces of AlGaN/ GaN Heterostructure  [Not invited]
    H. Hasegawa, T. Inagaki, S. Ootomo, M. Akazawa, T. Hashizume
    29th International Symposium on Compound Semiconductor (Lausanne, Switzerland, October 7-10, 2002)  2002/10
  • Akazawa Masamichi, Hasegawa Hideki
    Proceedings of the Society Conference of IEICE  2002/08
  • A UHV Contactless Capacitance-Voltage Characterization Method Applicable to Semiconductor Layers Grown on Insulating Substrates  [Not invited]
    M. Akazawa, H. Hasegawa
    6th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC 2002, Budapest, Hungary, May 26-29, 2002)  2002/05
  • ONO Tomoyuki, SUDA Yoshiyuki, AKAZAWA Masamichi, SUGAWARA Hirotake, SAKAI Yosuke, SUZUKI Kaoru
    電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan  2001/09
  • 赤澤正道
    応用物理学会学術講演会講演予稿集  2001/09
  • HOKOI K, AKAZAWA M, SUGAWARA H, SUDA Y, SAKAI Y
    電気学会研究会資料. ED, 放電研究会  2001/08
  • 鉾井耕司, 赤澤正道, 菅原広剛, 須田善行, 酒井洋輔
    応用物理学関係連合講演会講演予稿集  2001/03
  • QMESFETの作製と評価  [Not invited]
    赤澤正道, 葛西誠也, 橋詰保, 長谷川英機
    応用物理学関係連合講演会講演予稿集  2001/03
  • 小野智之, 須田善行, 赤澤正道, 菅原広剛, 酒井洋輔
    応用物理学関係連合講演会講演予稿集  2001/03
  • 須田善行, 小野智之, 赤澤正道, 酒井洋輔
    応用物理学関係連合講演会講演予稿集  2001/03
  • 庄子亮平, 吉田俊幸, 橋詰保, 赤澤正道, 長谷川英機
    応用物理学関係連合講演会講演予稿集  2001/03
  • Akazawa M, Kasai S, Hashizume T, Hasegawa H
    Technical report of IEICE. SDM  2001/02 
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is a quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the ...
  • SHOUJI Ryouhei, HASHIZUME Tamotsu, YOSHIDA Toshiyuki, AKAZAWA Masamichi, HASEGAWA Hideki
    Technical report of IEICE. SDM  2001/02 
    Ultrathin insulator/Si interfaces formed by various low temperature processes were characterized by UHV contactless C-V and XPS methods. For the SiO_2/Si interfaces prepared by a thermal oxidation process using dry O_2, the interface state density was increased with decreasing the oxidation temperature. In addition, lower temperature process was found to produce a discrete defect level near midgap. The ECR-excited N_2O plasma process at 400°C realized the interface with relatively low interface state density and wide destribution. Furthermore improvement of interface properties were achieve...
  • Akazawa M, Kasai S, Hashizume T, Hasegawa H
    IEICE technical report. Electron devices  2001/02 
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the pr...
  • SHOUJI Ryouhei, HASHIZUME Tamotsu, YOSHIDA Toshiyuki, AKAZAWA Masamichi, HASEGAWA Hideki
    IEICE technical report. Electron devices  2001/02 
    Ultrathin insulator/Si interfaces formed by various low temperature processes were characterized by UHV contactless C-V and XPS methods. For the SiO_2/Si interfaces prepared by thermal oxidation process using dry O_2, the interface state density was increased with decreasing the oxidation temperature. In addition, lower temperature process was found to produce a discrete defect level near midgap. The ECR-excited N_2O plasma process at 400℃ realized the interface with relatively low interface state density and wide distribution. Furthermore improvement of interface properties were achieved b...
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE  2000/09
  • AKAZAWA Masamichi
    Proceedings of the Society Conference of IEICE  2000/09
  • 庄子亮平, 吉田俊幸, 橋詰保, 赤澤正道, 長谷川英機
    応用物理学会学術講演会講演予稿集  2000/09
  • 須田善行, 小野智之, 赤澤正道, 酒井洋輔
    応用物理学会学術講演会講演予稿集  2000/09
  • 鉾井耕司, 赤澤正道, 菅原広剛, 須田善行, 酒井洋輔
    応用物理学会学術講演会講演予稿集  2000/09
  • 西村卓真, 須田善行, 小野智之, 赤澤正道, 酒井洋輔
    応用物理学関係連合講演会講演予稿集  2000/03
  • 赤澤正道, LUNGU C. P, LUNGU A, 田畑昌祥, 鉾井耕司, 菅原広剛, 酒井洋輔
    応用物理学関係連合講演会講演予稿集  2000/03
  • 赤澤正道, 谷井隆, 橋詰保
    応用物理学関係連合講演会講演予稿集  2000/03
  • 赤澤正道, 金編健太郎, 葛西誠也, 雨宮好仁, 長谷川英機
    応用物理学関係連合講演会講演予稿集  2000/03
  • 庄子亮平, 塩沢竜生, 吉田俊幸, 赤澤正道, 橋詰保, 長谷川英機
    応用物理学関係連合講演会講演予稿集  2000/03
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the IEICE General Conference  2000/03
  • Pulsed Laser Deposition of Carbon Particles Controlled by ICP Plasma  [Not invited]
    Y. Suda, T. Nishimura, T. Ono, M. Akazawa, Y. Sakai
    International Workshop on Basic Aspects of Non-equilibrium Plasmas Interacting with Surfaces (BANPIS-2000, Nagasaki, Japan, January 28 - 30, 2000)  2000/01
  • Kanaami K, Akazawa M, Amemiya Y
    IEICE technical report. Circuits and systems  2000/01 
    Functional LSIs using extremely small amounts of power can be made by using single-electron circuits, but designing the parameters of such circuits is a complicated and troublesome task. This paper therefore propose, taking the single-electron inverter circuit as an example, a simple policy for the circuit-parameter design. Following this policy, we can easily design a single-electron inverter with a desired transfer characteristic. We have, for example, designed a special inverter circuit that can be used for constructing multiple-valued logic systems. A multiple-valued transfer characteri...
  • NISHIMURA Takuma, MIZUNO Manabu, SUDA Yoshiyuki, SAKAI Yosuke, AKAZAWA Masamichi
    電気学会研究会資料. ED, 放電研究会  1999/10
  • CFx Polymer Film Deposition in DC and RF Fluorinert Vapor Plasmas  [Not invited]
    C. P. Lungu, A. M. Lungu, Y. Sakai, H. Sugawara, M. Tabata, M. Akazawa, M. Miyamoto
    Second International Symposium on Applied Plasma Science (ISPAS'99, Osaka, Japan, September 20 -24, 1999)  1999/09
  • SUDA Yoshiyuki, MIZUNO Manabu, NISHIMURA Takuma, BRATESCU M. A, SAKAI Yosuke, AKAZAWA Masamichi
    電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan  1999/09
  • NISHIMURA Takuma, MIZUNO Manabu, SUDA Yoshiyuki, SAKAI Yosuke, AKAZAWA Masamichi
    電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan  1999/09
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE  1999/08
  • Akazawa M, Amemiya Y
    Proceedings of the Society Conference of IEICE  1999/08
  • Fujiwara T, Akazawa M, Amemiya Y
    Technical report of IEICE. VLD  1999/06 
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem,...
  • Fujiwara T, Akazawa M, Amemiya Y
    Technical report of IEICE. DSP  1999/06 
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem,...
  • Fujiwara T, Akazawa M, Amemiya Y
    IEICE technical report. Circuits and systems  1999/06 
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem,...
  • Kanaami K, Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1999/03
  • TOKUDA E, ASAHI N, AKAZAWA M, AMEMIYA Y
    IEICE technical report. Neurocomputing  1999/03 
    The quantum Hopfield network is a kind of recurrent neural network that can always converge to the global minimum state without being stuck in local minima. This property is obtained by utilizing the co-tunneling phenomenon in quantum systems. This paper proposes a method of constructing the quantum Hopfield network by using single-electron circuits. The operation of the single-electron quantum Hopfield network is analized by computer simulation, assuming an instance of combinatrial optimization problems. It is demonstrated that, starting with a given initial state, the network can converge...
  • YAMADA Takashi, AKAZAWA Masamichi, AMEMIYA Yoshihito
    IEICE technical report. Neurocomputing  1999/03 
    This paper proposes to create Boltzmann Machine device by using single-electron circuits. The Boltzmann machine is a kind of recurrent neural network that can solve various problems in subject such as combinational optimization. It is difficult for presently available electronic circuits to implement the generation of randomness for the stochastic neuron operation. We can construct the stochastic neuron device concisely by using single-electron circuits and, thereby, can implement the Boltzmann machine on an LSIs.
  • Fujiwara Takanobu, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the IEICE General Conference  1999/03
  • Koutani M, Akazawa M, Amemiya Y
    Proceedings of the IEICE General Conference  1999/03
  • Single-Flux-Quantum Logic Devices Based on the Binary Decision Diagram  [Not invited]
    N. Asahi, T. Yamada, M. Akazawa, Y. Amemiya
    11th International Symposium on Superconductivity (ISS'98, Fukuoka, Japan, November 16-19, 1998)  1998/11
  • ASAHI Noboru, YAMADA Takashi, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Technical report of IEICE. SCE  1998/11 
    A 32-bit adder circuit is designed using single-flux-quantum (SFQ) circuits, on the basis of the binary decision diagram (BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. We here construct a high-speed SFQ adder circuit based on a BDD representation simplified by the method of isomorphic-subgraph substitution. To construct the adder circuit compactly, we propose the BDD device that can be driven by SFQ signal. It is shown by computer simulation that the operation speed...
  • ν-MOS Cellular-Automaton Devices for Intelligent Image Sensors  [Not invited]
    M. Ikebe, M. Akazawa, Y. Amemiya
    5th International Conference on Soft Computing and Information/ Intelligent Systems (IIZUKA'98, Iizuka, Fukuoka, Japan, October 16 - 20, 1998)  1998/10
  • YAMADA Takashi, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE  1998/09
  • FUKASAWA Yoshiyuki, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE  1998/09
  • ASAHI Noboru, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE  1998/09
  • TOKUDA E, ASAHI N, AKAZAWA M, AMEMIYA Y
    Proceedings of the Society Conference of IEICE  1998/09
  • ASAHI Noboru, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Technical report of IEICE. SCE  1998/07 
    This paper proposes the single-flux-quantum logic circuit based on the binary decision diagram(BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. By implementing BDDs with single-flux-quantum circuits, we can create various logic systems that are capable of high speed operation.Construction and operation of an 8-bit adder is presented as an example.
  • [Invited] Binary-Decision-Diagram Logic Systems Using Single-Electron Circuits and Single-Flux-Quantum Circuits-Circuit Design and Simulation  [Invited]
    M. Akazawa
    Seventh Hitachi Cambridge Seminar (McCrum Lecture Theatre, Corpus Christi College, Cambridge, U.K., July 6, 1998)  1998/07
  • ν-MOS Cellular-Automaton Devices for Intelligent Image Sensors  [Not invited]
    M. Ikebe, M. Akazawa, Y. Amemiya
    Second International Conference on Knowledge-Based Intelligent Electronic Systems (Adelaide, Australia, April 21 -23, 1998)  1998/04
  • YAMADA T, AKAZAWA M, AMEMIYA Y
    応用物理学関係連合講演会講演予稿集  1998/03
  • IWAMURA H, AKAZAWA M, AMEMIYA Y
    応用物理学関係連合講演会講演予稿集  1998/03
  • TOKUDA E, ASAHI N, AKAZAWA M, AMEMIYA Y
    応用物理学関係連合講演会講演予稿集  1998/03
  • KANAAMI K, AKAZAWA M, AMEMIYA Y
    応用物理学関係連合講演会講演予稿集  1998/03
  • AKAZAWA M, AMEMIYA Y, TABE M
    応用物理学関係連合講演会講演予稿集  1998/03
  • Kazawa M, Amemiya Y
    IEICE technical report. Neurocomputing  1998/03 
    The Hopfield network is a computation model for solving combinatorial optimization problems through the use of the specific feedback network. The feedback network changes its internal state to minimize the energy function. Thus we can obtain the solution to the given problem by relating the cost function of the problem to the energy function of the network and by observing how the network settles down to the minimum energy state. Owing to the existence of local minima in the energy function, however, we cannot always be certain of obtaining the correct solution to the problem. To overcome t...
  • Fukasawa Yoshiyuki, Akasawa Masamichi, Amemiya Yoshihito
    Proceedings of the IEICE General Conference  1998/03
  • Single-Electron Logic Circuits Based on the Binary Decision Diagram  [Not invited]
    N. Asahi, M. Akazawa, Y. Amemiya
    3rd International Workshop on Quantum Functional Devices (QFD'97, Gaithersberg, Maryland, U.S.A., November 5-7, 1997)  1997/11
  • IWAMURA Hiroki, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Technical report of IEICE. ICD  1997/09 
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • IWAMURA Hiroki, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Technical report of IEICE. SDM  1997/09 
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • IWAMURA Hiroki, AKAZAWA Masamichi, AMEMIYA Yoshihito
    Technical report of IEICE. VLD  1997/09 
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • IWAMURA Hiroki, AKAZAWA Masamichi, AMEMIYA Yoshihito
    IEICE technical report. Electron devices  1997/09 
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • [Invited] Quantum Hopfield Network Using Single-Electron Circuits  [Invited]
    M. Akazawa
    1997 International Conference on Solid State Devices and Materials (SSDM'97, Hamamatsu, Shizuoka, Japan, September 16-19, 1997)  1997/09
  • Computer-Aided Design of Single-Electron Boltzmann Machine Neuron Circuit  [Not invited]
    M. Akazawa, T. Yamada, Y. Amemiya
    1997 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'97, Boston, U.S.A., September 2-4,1997)  1997/09
  • Computer-Aided Design of Single-Electron Boltzmann Machine Neuron Circuit  [Not invited]
    M. Akazawa, T. Yamada, Y. Amemiya
    Second International research Workshop on Future Information Processing Technologies (Sapporo Kita-Hiroshima Prince Hotel, Kita-Hiroshima, August 25-28,1997)  1997/08
  • Yamada Takashi, Iwamura Hiroki, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE  1997/08 
    決定グラフとはディジタル論理を有向グラフで表す手法であり、論理設計や論理検証などのCADで使われている。本研究では、多値論理の決定グラフ(MDD:Multiple-valued Decision Diagram)を実際のデバイスで構成することを提案する。具体例として、4値論理MDDをシリコン機能デバイスのνMOSで構成してみた。加算器を例にとってシミュレーション解析を行い、正しい論理動作を確認した。以下に結果を述べる
  • IKEBE Masayuki, Honma Kunihiko, Akazawa Masamichi, AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE  1997/08 
    νMOSインバータは、多入力しきい論理に適したデバイスである。これを用いると画像処理用セルオートマトン回路をコンパクトに構成できる。しかし、しきい論理回路ではνMOSをオンとオフの中間状態で使うことが多く、そのため貫通電流を生じて消費電力が大きくなりやすい。 ここではνMOS回路の低電力設計を考える。雑音除去・輪郭抽出セルオートマトン回路を例にとり、ダイナミック形と高しきい値MOS形の2つの構成法によって低電力設計行った。以下にその詳細を示す。
  • Nitta Hidehiko, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE  1997/08 
    単電子回路を用いてCMOS型の論理回路が構成されており, 擬似CMOS型単電子回路と呼ばれている. ところで, 単電子回路の性質を上手に利用すれば, 本来のCMOSにはない新しい機能を付加することができる. ここでは, 入力の組合わせにより論理を切り換えられる可変論理デバイスを提案する.
  • Asahi Noboru, Akazawa Masamichi
    Proceedings of the Society Conference of IEICE  1997/08 
    単電子回路では、輸送電荷の離散性とクーロンブロッケード現象とが相まって、通常の電子回路には見られない様々な特性が現れる。そのためCMOS回路では得られない種々の機能が実現可能となる。たとえば、インバータ回路を例にとってパラメータ探索を行ったところ、入出力の伝達特性がステップ的に変化する「ステップインバータ」の機能が得られることが判明した。これは、しきい論理回路や多値論理回路を低電力設計するときに不可欠のものである。以下に結果を報告する。
  • Yamada T, Akazawa M
    応用物理学関係連合講演会講演予稿集  1997/03
  • Akazawa M
    応用物理学関係連合講演会講演予稿集  1997/03
  • Tokuda E, Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1997/03
  • Nitta H, Akazawa M
    応用物理学関係連合講演会講演予稿集  1997/03
  • Asahi N, Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1997/03
  • Lee G, Akazawa M, Wu Nan Jian, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1997/03
  • Akazawa M, Asahi N, Amemiya Y
    IEICE technical report. Electron devices  1997/03 
    This paper proposes an idea of constructing single-electron logic circuits based on the binary-decision diagram (BDD). The proposed unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting the identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for elemental logic circuits (NAND, NOR, XOR) and combinational logic circuits (a four-variable logic circuit and a 4-bit adder). Computer simulation shows that the designed circuits pe...
  • Fukasawa Yoshiyuki, Akazawa Masamichi, Amemiya Yoshihito
    Proceedings of the IEICE General Conference  1997/03 
    二分決定グラフ(BDD)は, ブール代数式や真理値表とは異なる方法, 有向グラフによってディジタル論理を表す手法である。もともと論理設計や論理検証に使われていたが, 最近になって実際のデバイスでBDD論理を組むという研究が報告されるようになった。ここでは, BDDの適用範囲をアナログに拡大することを提案する。これによって新しい応用が生まれる可能性がある。
  • Akasawa Masamichi, Amemiya Yoshihito
    Proceedings of the IEICE General Conference  1997/03 
    単電子現象は本質的に離散現象なので, それを利用した単電子回路も本来はデジタル論理に適したものである。しかしアナログ回路の開発も将来に向けて必要とされる。ここでは電子密度変調によるアナログ表現法を提案し, そのための回路構成を考えてみた。
  • Aoki Takahiro, Akazawa Masamichi, Tazawa Satoshi
    Proceedings of the Society Conference of IEICE  1996/09 
    計算機上でプロセス・デバイス・回路をシミュレートし、デバイスの特性を予測するTechnology CAD技術は短TATな製造技術の開発に必要である。特性予測をより正確に行うには地道な実験データの蓄積とモデリングが必須である。一般にpチャネルMOSFETにおいて、nウェル形成用の燐ドーパントにはパイルアップ現象があることが知られており、この現象を取り扱っていない従来のシミュレータでは、デバイス特性予測を大きく狂わすことが知られている。また、SiO2-Si界面において酸化工程、アニール工程後の燐ドーパントの再分布(偏析)があることも一般的に知られている。本報告では、燐ドーパントのパイルアップ現象をモデル化し、種々のプロセス水準に対するpチャネルMOSFETのしきい値電圧の実測結果と比較した結果を述べる。
  • Akazawa Masamichi, Amamiya Yoshihito
    Proceedings of the Society Conference of IEICE  1996/09 
    量子セルの近接相互作用を利用したセルオートマトン(QCA)が提案されている。しかしこれまでのところセル配列の静的な安定状態を考察するに留まり、システム全体として動作するかどうかは理論的にも実験的にも検証されていない。そこで著者は種々の観点からその動作可能性を検討し、アニーリングによる駆動を行えばシステム動作が可能であろう、との予測を行った。
  • Phosphorus Pile-Up Model for SiO2-Si Interface of p-Channel MOSFETs  [Not invited]
    M. Akazawa, T. Aoki, S. Tazawa, Y. Sato
    1996 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'96, Tokyo, Japan, September 2-4, 1996)  1996/09
  • Shibata N, Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1996/03
  • Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1996/03
  • Asahi N, Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1996/03
  • Akazawa M, Amemiya Y
    応用物理学関係連合講演会講演予稿集  1996/03
  • Contactless and Nondestructive Characterization of Silicon Surfaces by Capacitance-Voltage and Photoluminescence Method  [Not invited]
    S. Koyanagi, M. Akazawa, H. Hasegawa
    1995 Int. Conf. on Solid State Devices and Materials (SSDM'95, Osaka, Japan, August 21-24, 1995)  1995/08
  • AMEMIYA Yoshihito, AKAZAWA Masamichi
    應用物理  1995/08
  • Shiobara S, Suzuki S, Akazawa M, Hashizume T, Hasegawa H
    応用物理学関係連合講演会講演予稿集  1995/03
  • Akazawa M, Koyanagi S, Hasegawa H, Sakai T
    応用物理学関係連合講演会講演予稿集  1995/03
  • Koyanagi S, Akazawa M, Hasegawa H, Sakai T
    応用物理学関係連合講演会講演予稿集  1995/03
  • Control of Compound Semiconductor Interfaces by Si Interface Control Layer and Its Applications  [Not invited]
    H. Hasegawa, S. Kodama, K. Koyanagi, M. Akazawa
    State-of-the-Art Program on Compound Semiconductors XVIII (SOTAPOCS XVIII, Honolulu, Hawaii, U.S.A., May 18, 1993)  1993/05
  • [Invited] Control of Structure and Properties of Compound Semiconductor Interfaces by Si Interface Control Layer  [Invited]
    H. Hasegawa, S. Kodama, K. Koyanagi, M. Akazawa
    5th International Conference on Indium Phosphide and Related Materials (IPRM'93, Paris, France, April 18-22, 1993)  1993/04
  • Control of Compound Semiconductor Interfaces by Si Interface Control Layer and Its Applications  [Not invited]
    H. Hasegawa, M. Akazawa, S. Kodama, K. Koyanagi, S. Suzuki, Y. G. Xie, T. Sawada
    Conference on Advanced Heterostructure Transistors (Keauhou, Kona, Hawaii, U.S.A., November 29- December 4, 1992)  1992/11
  • In-Situ Characterization and Control of GaAs and InGaAs Surfaces and Interfaces for Completely UHV-Based Nanostructure Fabrication  [Not invited]
    H. Hasegawa, T. Sawada, T. Saitoh, S. Kodama, M. Akazawa, H. Fujikura
    International Conference on Scienece and Technology of Electron Devices (Kruger National Park, Republic of South Africa, November 16-18, 1992)  1992/11
  • In-Situ Characterization and Control of Compound Semiconductor Surfaces and Interfaces for Completely UHV-Based Nanostructure Fabrication  [Not invited]
    H. Hasegawa, T. Saitoh, M. Akazawa, H. Fujikura, T. Sawada
    3rd International Conference on Solid State and Integrated Circuit Technology (ICSIT'92, Bejin, China, Oct. 18 - 24, 1992)  1992/10
  • Investigation of Valence Band Offset Modification at GaAs-AlAs and InGaAs-InAlAs Heterointerfaces Induced by Si Interlayer  [Not invited]
    M. Akazawa, H. Hasegawa, H. Tomozawa, H. Fujikura
    19th International Symposium on GaAs and Related Compounds (Karuisawa, Japan, September 28- October 2, 1992)  1992/09
  • Removal of Fermi Level Pinning in InGaAs Nanostructures by Ultrathin MBE Si Interface Control Layer  [Not invited]
    M. Akazawa, S. Kodama, H. Fujikura, H. Hasegawa
    Electronic Materials Conference (Cambridge, U.S.A., June 24-26, 1992)  1992/06
  • Control of Compound Semiconductor Interfaces by an Ultrathin Pseudomorphic Si Layer  [Not invited]
    H. Hasegawa, M. Akazawa, S. Kodama, K. Koyanagi
    1st International Workshop on Quantum Functional Devices (QFD'92, Nasu Heights, Japan, May 12-15, 1992)  1992/05
  • Control of Surface and Interface Fermi Level Pinning for Compound Semiconductor Nanometer Scale Structures  [Not invited]
    H. Hasegawa, M. Fujikura, M. Akazawa, H. Tomozawa
    International Workshop on Quantum-Effect Physics, Electronics and Applications (Luxor, Egypt, January 5-9, 1992)  1992/01
  • Fabrication Process and Properties of InGaAs Wires Having Si Interface Control Layers for Removal of Fermi Level Pinning  [Not invited]
    H. Fujikura, H. Tomozawa, M. Akazawa, H. Hasegawa
    1st International Symposium on Atomically Controlled Surfaces and Interfaces (ACSI-1, Tokyo, Japan, November 19-22, 1991)  1991/11
  • Control of GaAs and InGaAs Insulator- Semiconductor and Metal-Semiconductor Interfaces by Ultrathin Molecular Beam Epitaxy Si Layers  [Not invited]
    M. Akazawa, H. Ishii, H. Hasegawa
    1991 Int. Conf. on Solid State Devices and Materials (SSDM'91, Yokohama, Japan, August 27-29, 1991)  1991/08
  • Formation Mechanism of Schottky Barriers on MBE Grown GaAs Surface Subjected to Various Treatment  [Not invited]
    H. Ishii, H. Hasegawa, M. Akazawa
    3rd International Conference on Formation of Surface and Interface (ICFSI-3, Rome, Italy, May, 1991)  1991/05
  • Surface Passivation Technology of InGaAs Using an MBE Si Layer Compatible with Standard Device Processing  [Not invited]
    H. Hasegawa, M. Akazawa, E. Ohue
    3rd International Conference on InP and Related Materials (IPRM'91, Cardiff, Wales, U.K., April 8-11, 1991)  1991/04
  • Surface Passivation of InGaAs Using Thin Si Layers by Novel In-situ Interface Control Process  [Not invited]
    M. Akazawa, E. Ohue, H. Ishii, H. Iwadate, H. Hasegawa
    2nd International Conference on InP and Related Materials (IPRM'90, Denver, U.S.A., April23-25, 1990)  1990/04
  • Control of GaAs and InGaAs Insulator-Semiconductor Interfaces by an Ultrathin MBE Si Layer  [Not invited]
    H. Hasegawa, M. Akazawa, H. Iwadate, E. Ohue
    7th International Workshop on Future Electron Devices (Toba, Japan, October 2-4, 1989)  1989/10
  • Surface Passivation of In0.53Ga0.47As by Ultra-thin Pseudomorphic MBE Si Layer Combined with Photo-CVD Insulator  [Not invited]
    M. Akazawa, E. Ohue, H. Ishii, H. Iwadate, H. Hasegawa
    6th International Conference on Passivity (Passivity-6, Sapporo, Japan, Sept. 24-28, 1989)  1989/09
  • In0.53Ga0.47As MISFETs Having an Ultrathin MBE Si Interface Control Layer and Photo-CVD SiO2 Insulator  [Not invited]
    M. Akazawa, H. Hasegawa, H. Ohno
    the 21st Conference on Solid State Devices and Materials (SSDM'89, Tokyo, Japan, August 28-30, 1989)  1989/08
  • Control of Compound Semiconductor-Insulator Interfaces by an Ultra-thin MBE-Si Layer  [Not invited]
    H. Hasegawa, M. Akazawa, H. Ishii, K. Matsuzaki
    The 16th Conference on Physics and Chemistry of Semiconductor Interfaces (PCSI-16, Boseman, Montana, U.S.A., February 7-9, 1989)  1989/02
  • Characterization and Control of Group-III Nitride Surfaces for Power Electronics and Sensor Electronics [invited]  [Not invited]
    H. Hasegawa, M. Akazawa
  • X-ray Photoelectron Spectroscopy Study of Silicon Interlayer Based Surface Passivation for AlGaAs/GaAs Quantum Structures on (111) B Surfaces  [Not invited]
    M. Akazawa, N. Shiozaki, H. Hasegawa
  • Characterization of Surfaces and Interfaces of InAlN/GaN Heterostructures  [Not invited]
    Masamichi Akazawa

Association Memberships

  • THE INSTITUTE OF ELECTRICAL ENGINEERS OF JAPAN   THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS.   THE JAPAN SOCIETY OF APPLIED PHYSICS   

Research Projects

  • 日本学術振興会:科学研究費助成事業
    Date (from‐to) : 2023/04 -2026/03 
    Author : 佐藤 威友, 三好 実人, 赤澤 正道
  • MEXT:委託事業(再委託)
    Date (from‐to) : 2021/04 -2025/03 
    Author : Jun Suda
  • GaN結晶の表面近傍点欠陥の評価・低減に関する研究
    株式会社サイオクス:共同研究
    Date (from‐to) : 2022/04 -2023/03 
    Author : 赤澤正道, 藤倉序章、堀切文正、金木将太
  • 公益財団法人 八洲環境技術振興財団:研究開発・調査助成
    Date (from‐to) : 2020/04 -2021/03
  • MEXT:科学技術試験研究委託事業
    Date (from‐to) : 2016/04 -2021/03 
    Author : Tetsu Kachi
  • 文部科学省:科学研究費補助金(新学術領域研究)
    Date (from‐to) : 2016/04 -2021/03 
    Author : 橋詰 保
  • 文部科学省:科学研究費補助金(基盤研究(C))
    Date (from‐to) : 2015/04 -2018/03 
    Author : 赤澤 正道
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research
    Date (from‐to) : 2012/04 -2015/03 
    Author : AKAZAWA Masamichi
     
    Fermi level pinning at the surface, insulator/semiconductor interface, and metal/semiconductor interface has been investigated for InAlN lattice matched to GaN. Pinning at the InAlN surface was found to be removed by an appropriate insulator deposition. The interface state density at the insulator/InAlN interface was found to be dependent on the interface formation process and post deposition annealing. An original method to form an Al2O3/InAlN interface with a low interface state density was developed. For the metal/InAlN interface, strong dependence of the Schottky barrier height on the metal work function was seen.
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research
    Date (from‐to) : 2009 -2012 
    Author : HASHIZUME Tamotsu, SATO Taketomo, KOGA Hiroaki, KUBO Toshiharu, AKAZAWA Masamichi
     
    To improve the operation stability of GaN-heterostructure transistors, we have carried out characterization and control of electronic states at insulator-semiconductor interfaces, fabrication and characterization of the multi-mesa-channel (MMC) transistors, and the related experiments. By applying the novel simulation and photo-assisted capacitance-voltage methods to Al_2O_3/ AlGaN/GaN structures, we determined the density distribution of electronic states at the Al_2O_3/AlGaN for the first time. It was also found that the MMC structure is very effective in improving the current stability of the GaN-based transistors.
  • 文部科学省:科学研究費補助金(萌芽研究)
    Date (from‐to) : 2008 -2008 
    Author : 長谷川 英機, 赤澤 正道
     
    本研究の目的は、III-V化合物半導体metal-insulator-semiconductor(MIS)構造の界面準位分布に関する「ピンニング・スポット面内分布(Dps)モデル」を、理論解析とSi超薄膜界面層(Si ICL)構造を用いた実験により定量的に検証することにあり、次の成果を得た。(重)従来界面準位は、面内で均一分布すると仮定されてきた。DSPモデルでは、界面準位分布は面内でナノスケール尺度の不均一性をもち、強いフェルミ準位ピンニングを引き起こすスポット状の領域「ピンニング・スポット」と、ピンニングが弱くバイアスにより電子蓄積層や反転電子層が形成され得るピンニング・フリー領域が共存すると考える。このモデルから期待されるMISアドミタンスのバイアス・周波数・温度依存性を定式化し、コンピュータを用い数値計算を行った。(2)化合物半導体およびsi ICLをMBE成長し、そのsi ICL一部をラジカル窒化したGaAsおよびInGaAsのSi ICL制御MIS試料を作製し、そのアドミタンスのバイアス・周波数・温度依存性を測定した。(3)Si ICLMIs試料について、バンド端フォトルミネセンス(PL)量子効率の励起光強度依存性を非接触測定し、その結果をポーランド・シレジアン工科大学物理学科のアダモヴィッチ教授の協力を得てコンピュータ解析し、マクロな界面準位密度(D_)...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 2006 -2007 
    Author : Hideki HASEGAWA, 赤澤 正道, 池辺 将之
     
    This project investigates key technologies for realization of GaN-based high-sensitivity chemical sensors and their on-chip integration using nanowires. The main conclusions are as follows: (1) Interface models on Schottky barrier formation are surveyed, and key issues related to AlGaN/GaN Schottky barriers including Fermi level pinning, Schottky barrier height (SBH) and reverse leakage currents are discussed. The current transport is explained by the thin surface barrier (TSB) model. Leakage currents can be reduced by the oxygen gettering process. (2) Pd Schottky barrier hydrogen sensors f...
  • 文部科学省:科学研究費補助金(萌芽研究)
    Date (from‐to) : 2006 -2006 
    Author : 長谷川 英機, 赤澤 正道
     
    量子デバイスの消費電力は極低温では小さいが、室温では電子エネルギーの熱的広がりによるスイッチ特性のだれにより増大する。本研究では、「量子ドットの空間的位置を電界で制御しトンネル確率を制御する」という原理にもとづく「電界移動型量子ドット単電子分岐スイッチ」について、その原理を確認することと、その効果を妨げる表面準位を低減することを目的として研究を推進し、次の成果を得た(1)3つのショットキ・ラップゲートにより、AlGaAs/GaAs量子細線T型分岐上に、量子ドットと3つのトンネル障壁を形成した「単電子分岐スイッチ」を試作し、その動作を測定した。その結果、低温で通常の単電子トンネル理論よりも急峻なスイッチ特性が得られた。しかしその急峻さは温度の上昇と共に急激に消失した。(2)デバイスの特性を量子ドットを円形近似した単純な解析モデルにもとづき解析して実験特性と比較した結果、ドットの電界移動によるトンネル確率の指数関数的変調が急峻なスイッチ特性を実現することが、確認された。また温度上昇による特性の劣化の主な理由は、低温では凍結している分岐スイッチの表面準位が、室温に近づくほど活性化し、ドットの電界移動を妨げることにあることが判明した。(3)その後の研究の大半は、「シリコン界面制御層(Si ICL)」を用いた代表者らの表面不活性化技術を、種々のファセット面をもつAlGaAs/GaAs量...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 2004 -2006 
    Author : Eiichi SANO, 赤澤 正道, 山本 眞史, 尾辻 泰一
     
    The purpose of this research is to establish fundamental device, circuit, and measurement technologies for realizing compact, low-power communication circuits with carrier frequencies raging from a few hundreds GHz to one THz. The following results have been obtained. (1)A finite-difference time-domain (FDTD) electromagnetic simulator analyzing simultaneously active devices like resonant-tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) has been developed. (2)An active integrated antenna (AIA) oscillator consisting of InP-based HEMTs and a slot antenna was designed usin...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(C))
    Date (from‐to) : 2004 -2005 
    Author : Masamichi AKAZAWA, 佐野 栄一
     
    It was confirmed that a metal mesh having an appropriate structure exhibits a high transmittance as a filter in the THz region. Especially a filter with the thickness much smaller than the transmitted wavelength does not have the cutoff property resulting in a high transmittance even for the tilted incidence. According to the results of simulation and experiment, it was found that the surface plasmon-polariton (SPP) contributes the transmission property. Then there is possibility that the boundary condition at the semiconductor surface for the THz emission is modified by attaching a metal m...
  • 文部科学省:科学研究費補助金(萌芽研究)
    Date (from‐to) : 2004 -2005 
    Author : 佐野 栄一, 赤澤 正道
     
    本研究は、複数の半導体レーザ(LD)で発現する互いに直交したカオス信号に情報を乗せ、それらを多重化することにより、通信容量を飛躍的に増大させる光通信方式の創出を目的とする。具体的には、複数のLDから構成される結合写像格子(CML:Coupled-Map Lattice)を送信部と受信部に配置し、送信CMLからの複数の「カオスチャネル」を一本の光ファイバ内に多重化し、送信CMLとカオス同期する受信CMLにおいて多重カオス信号を分離する光通信方式である。昨年度は、光電場レート方程式とキャリアレート方程式を数値計算することにより、CMLの振る舞いを詳細に検討し、LDの注入電流と光結合度を選ぶことにより、CMLの各LD出力を直交できること、送信CMLと受信CML問の相関はほぼδ_となると(ただし、iは送信CMLのi番目のLD、jは受信CMLのj番目のLDを示す)を明らかにした。さらに、2チャネル伝送システムをシミュレートし、1Gbit/sの伝送レートでの2チャネル伝送が可能であることを示した。しかしながら、これらの理論解析は伝送距離ゼロのいわゆるback-to-backの条件で行われていた。実際のシステムにおいては光ファイバの波長分散とカー効果により受信波形は送信波形と異なるため、送信CML.と受信CML間のカオス同期は保証されない。これまでの研究では、分散シフトファイバが仮...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 2002 -2004 
    Author : Tamotsu HASHIZUME, 赤澤 正道, 葛西 誠也, 本久 順一
     
    The purpose of this research was to characterize and control surface/interface properties of GaN-based material systems such as AlGaN/GaN hetrostrcutures for the stability improvement of high-frequency and high-power transistors. The main results obtained are listed below :(1)Serious deterioration such as stoichiometry disorder and nitrogen deficiency (N deficiency) was found at the processed AlGaN surfaces. This resulted in formation of a localized deep donor level related to N vacancy (V_N), causing excess leakage currents at the AlGaN Schottky interface and serious drain current collapse...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(A))
    Date (from‐to) : 2001 -2003 
    Author : Hideki HASEGAWA, 赤澤 正道, 橋詰 保, 雨宮 好仁, 葛西 誠也
     
    The purpose of this research was to investigate a novel single electron integrated circuit based on a binary-decision diagram (BDD) architecture utilizing quantum dots controlled by nano-Schottky gates. Main results are listed below :(1)A novel "hexagonal BDD quantum circuit approach" for realization of quantum LSIs, in which the BDD architecture is implemented on hexagonal nanowire network in high dense, was proposed. Various logic subsystems and arithmetic logic units (ALUs) were successfully designed utilizing the novel circuit approach.(2)Elemental BDD devices (node devices) were realiz...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 2001 -2003 
    Author : Yosuke SAKAI, Bratescu A, 赤澤 正道, 菅原 広剛, 中島 昌俊, 須田 善行
     
    In order to reduce the usage of SFs insulation gas, which has high GWP (global warming potential), the present project proposed to use a-C:F film coated conductor prepared by RF plasma CVD method for insulation of electric power systems as alternatives of SF_6. This project was motivated because we had experienced very high deposition rates in RF plasma if per-fluorocarbon vapors were used. The main results are listed as follows.l. The deposition rate on Si and A1 substrates was > 100-200nm/min, which is a few tens times higher than those obtained by conventional CF_4 and C_2F_6 gases.2. Th...
  • 文部科学省:科学研究費補助金(奨励研究(A), 若手研究(B))
    Date (from‐to) : 2001 -2002 
    Author : 赤澤 正道
     
    「可逆計算デバイス」には、熱的な可逆性と論理的な可逆性が要求される。本研究では、単電子デバイスの準静的動作の極限(低周波極限)が、可逆動作となる可能性があることを示した。電子デバイスにおいても、完全な熱的可逆動作は熱力学の第2法則によって否定されるが、準静的動作により極めて可逆に近い動作を実現することは物理的に否定されるものではない。しかし、電子デバイスを準静的に駆動しても、個々のデバイスが閾値をもち、その閾値において急峻なエネルギー変化を伴う限り、消費電力の低減は制限を受ける。これは、たとえ、理想的な特性を持つ量子細線トランジスタを用いたとしても同じことである。ところが、適切に設計された単電子デバイスは、励起準位を介することなく基底状態のみで動作することが可能であり、量子極限近傍で急激なエネルギーの損失が起こらないように動作することができるので、準静的動作により消費電力を任意に小さくできる。したがって、適切に設計された単電子回路の準静的動作の低周波極限は、電源から供給されたエネルギーが電荷の回収とともに完全に電源に戻されるような充放電動作、すなわち可逆動作となる。集積回路用の極微細加工はすでに、寸法的にはメゾスコピック領域に入っており、単電子現象の利用さえも、不可能ではなくなってきている。このような動向の中で、本発見は大きな意義を持つ。すなわち、Fredkin-Toffol...
  • 文部科学省:科学研究費補助金(特定領域研究(A))
    Date (from‐to) : 1999 -1999 
    Author : 赤澤 正道
     
    ボルテックス輸送の性質を巧みに利用した、新たな回路アーキテクチャを見つけ出すことは、超伝導エレクトロニクスの発展を促進する鍵となる。研究代表者は、新規なデバイスである「ボルテックスBDDデバイス」を用いて高速な理論回路を構成する方法を見出した。BDDは二分決定グラフの略であり、ブール代数によらず、有向グラフを用いてディジタル関数を表現するための1方法であり、論理設計において多くのディジタル関数を完全かつ簡便に表現することができる。本研究では、BDDをそのまま回路化し、BDD回路システムとすることを考えた。BDD回路システム中において、論理出力値は、変数の組み合わせによって活性化されるパスを、情報担体が転送されることにより決められる。BDDノードデバイス(BDDデバイス)に要求される機能は入力変数にしたがって情報担体の転送される方向を切り替える、2分岐スイッチングである。本研究においては、分岐点の2つの枝において、ジョセフソン接合の超伝導―常電導遷移を用いてボルテックスの転送方向を切り替える方式のデバイスを提案した。提案したBDDデバイスを用いて構成される32ビット加算器および32ビット比較器についてシュミレーションを行った結果、両者とも正しく動作することが示され、加算器では高々350psの処理時間、比較器では高々750psの処理時間で計算が可能なことが示された。また、SBDD...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 1998 -1999 
    Author : Yoshihito AMEMIYA, 〓 南健, 赤澤 正道, 陽 完治, 浅井 哲他
     
    In this project, we developed single-electron gate circuits based on the principle of the majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1 , and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller n...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(C))
    Date (from‐to) : 1997 -1998 
    Author : Masamichi AKAZAWA, 呉 南健, 雨宮 好仁
     
    We have investigated ways of using a single-electron-tunneling (SET) circuit to solve problems in neural networks, and have obtained the following results :1) A simple circuit for a Boltzmann machine neuron : The circuit for the Boltzmann machine neuron that has a stochastic response is usually complicated. We found, however, that by using a single-electron-tunneling circuit, we can construct a compact neuron circuit in which the Coulomb blockade condition is adjusted appropriately, It can produce an output of a random 1-0 bit stream with the probability for an output of 1 controlled by an ...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 1997 -1998 
    Author : Tamotsu HASHIZUME, 関 昇平, 呉 南健, 赤澤 正道, 長谷川 英機, 藤倉 序章
     
    The purpose of this study is to fabricate a high-speed InAlAs/InGaAs HEMT with Schottky gate using in-situ electrochemical process and to fabricate an insulated-gate InAIAs/InGaAs HEMT with low-power consumption using ultrathin Si interface-control technique. The main results obtained are listed below :(1) A novel in-situ pulsed-mode electrochemical process enables us to produce good Schottky contacts on InP, InAlAs and lnGaAs with carrier transport properties according to the thermionic emission model.(2) A Ti/n-InP contact formed by sputtering showed good ohmic characteristics after rapid...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 1997 -1998 
    Author : Nan-Jian WU, 石井 宏辰, 赤沢 正道, 雨宮 好仁, 安永 均
     
    The optimal structure of high speed InP Schottky power rectifier was designed. InP Schottky power rectifier was fabricated by Novel In-Situ Electrochemical process. Summary of the results is given as following.1) The rectification efficiency of InP Schottky power rectifier trades off the maximum operating frequency. Structure of the InP Schottky power rectifier was designed optimally. For example, to fabricate an InP Schottky power rectifier with a blocking voltage of 40V and efficiency of above 90%, the parameter of the InP epi-substrata must be designed as following. The thickness and don...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 1996 -1997 
    Author : Yoshihito AMEMIYA, 呉 南健, 赤澤 正道
     
    We proposed a method of constructing singleelectron logic systems on the basis of the binary decision diagram. Following the guiding principle that we have proposed, we designed sample logic subsystems, an adder and a comparator, by combining singleelectron BDD devices. Matters that require attention in designing the subsystems were discussed. The operation of the designed subsystems was calculated by computer simulation. It was demonstrated that the designed subsystems successfully produce an output data flow in reponse to the input data flow through pipelined processing. The operation err...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(基盤研究(C))
    Date (from‐to) : 1996 -1997 
    Author : Nan-Jian WU, 赤澤 正道, 雨宮 好仁
     
    We propose cellular automaton cicuits that use single-electron-tunneling cicuits (SET-CA). The unit cell consists of four intrinsic semiconductor islands and four single-electron-tunneling junctions. The dielectric constant of the intrinsic semiconductor is much larger than that of the junction insulator.The unit cell is charged with two single electrons. Polarization states of the two single electrons in the unit cell can be used to encode a binary signal. We designed various binary logic SET-CA circuits, and analyzed their operation by computer simulation. It was demonstrated that the SET...
  • 文部科学省:科学研究費補助金(奨励研究(A))
    Date (from‐to) : 1996 -1996 
    Author : 赤澤 正道
     
    高々数個の電子を情報媒体とする極微細な「多値メモリ素子」を独自の設計思想で世界で初めて実現し、多値論理の情報処理システムに使用できる高速・高密度・低消費電力のメモリLSIに応用するための基礎的研究を行った。その結果、次のことがわかった。1)単電子トランジスタのトンネル接合を、方向性単電子トンネル接合におきかえると、多値メモリを構成できることをモンテカルロシミュレーションにより確認した。2)方向性単電子トンネル接合は、金属と誘電率の大きく異なる2種の絶縁体の組み合わせによって実現可能であることを理論的計算により予測した。3)実際の多値メモリデバイス構造は、TiあるいはTaの金属超薄膜をSTM/AFMにより微細加工することによって作製可能であることを実験により確認した。4)多値メモリセルは200MHzでの駆動が可能であり、また200nsecのデータ保持が可能であることが予測された。このとき、消費電力は1bit当り1pW程度になり、1Tbitの集積度でも1Wの消費電力で済むことになる。5)単電子の有無を電圧の情報に変換する入出力回路や、多値論理サブシステムの単電子回路による構成も可能であることをモンテカルロシミュレーションにより確認した。
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(B), 基盤研究(B))
    Date (from‐to) : 1995 -1996 
    Author : Hideki HASEGAWA, 赤沢 正道, 本久 順一, 橋詰 保
     
    The purpose of this study is to investigate the interaction mechanism between surface states and confined levels in III-V compound semiconductor quantum structures and to control the surface properties by use of ultrathin silicon interface control layr (SiICL) for fabrication of novel optical devices. The main results obtained are listed below :(1) It was found that the photoluminescence (PL) intensity from the near-surface quantum well (OW) with the surface-to-well distance of 5nm, was reduced by a factor of 1000 as compared with that from the reference QW located deeply inside. We reveale...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(試験研究(B), 基盤研究(B))
    Date (from‐to) : 1995 -1996 
    Author : Tamotsu HASHIZUME, 関 昇平, 呉 南健, 赤沢 正道, 長谷川 英機
     
    The purpose of this study is to realize Schottky contacts with high barrier height to n-InP by a novel in-situ electrochemical process and to apply this Schottky gate technology to fabrication InP MESFETs and related high-speed integrated circuits and optoelectronic integrated circuits. The main results obtained are listed below :(1) A novel in-situ electrochemical process enables us to produce Pt/n-InP Schottky diodes with a barrier height of 0.86eV or higher and n-value of 1.1 or lower.(2) Capacitance-voltage measurements, Raman spectroscopy and X-ray photoelectron spectroscopy revealed t...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(C), 基盤研究(C))
    Date (from‐to) : 1995 -1996 
    Author : Tamotsu HASHIZUME, 呉 南健, 赤沢 正道, 長谷川 英機
     
    The purpose of this study is to investigate the properties of Schottky/2DEG contacts and to realize novel quantum structures utilizing the Schottky/2DEG contacts as in-plane gates. The main results obtained are listed below :(1) We developed a novel technique to form a direct Schottky contact to the edge of 2DEG in AlGaAs/GaAs heterojunction by use of in-situ electrochemical process, and applied this technique to formation of in-plane-gate type quantum structures.(2) In-plane-gate type quantum wire transistors were successfully fabricated. Quantized conductance was observed up to 100K,indic...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(A))
    Date (from‐to) : 1994 -1995 
    Author : Takashi FUKUI, 赤澤 正道, 本久 順一, 長谷川 英機
     
    We have fabricated AlGaAs/GaAs quantum dot structures using selective area metalorganic vapor phase epitaxy (MOVPE). First, GaAs pyramidal structures with four-fold symmetric {011} facet side walls are formed on SiN_x masked (001) GaAs with square openings. Once the pyramidal structures were completely formed, no growth occurs on the top and side walls of the pyramids. Furthermore, the shape and width of the top area observed by a scanning electron microscope (SEM) and an atomic force microscope (AFM) shows to be highly uniform. This indicates that self-limited growth mode occurs. Next, usi...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(C))
    Date (from‐to) : 1994 -1995 
    Author : 齋藤 俊也, 斉藤 俊也, 齋藤 俊也, Toshiya SAITOH, 澤田 孝幸, 赤澤 正道, 陽 完治
     
    Solar cells using InP and its related materials are drawing attention for sources of electricity of man-made satellites. However, the surface recombination velocity at InP surface is known to be larger than that at conventional Si solar cell surface. In this study, firstly, contactless and non-destructive measurements of surface state density distribution of InP surface and its related materials are carried out for the improvement of passivation technology. The measurement of surface recombination velocity under sunlight are done, for the first time, for various sunlight intensity using pho...
  • 文部科学省:科学研究費補助金(奨励研究(A))
    Date (from‐to) : 1994 -1994 
    Author : 赤澤 正道
     
    本研究は、新しい構造をもつ2次元電子ガスMISFETを実現するための基礎的研究である。年限内に得られた成果を以下に挙げる。(1)Si超薄膜による絶縁体(Si_3N_4あるいはSiO_2)-InGaAs界面の制御は、非常に薄い(100Å)InGaAs活性層上においても有効であることがわかり、2次元電子ガスの、MISゲートによる駆動にも成功した。(2)MISゲート電極下の逆HEMT構造のMBE成長条件の最適化を計り、低温成長スペ-サ層の挿入により2次元電子の移動度を、77Kにおいて5,000cm/v・secから40,000cm/v・secまで向上させた。(3)一般的にInGaAs系HEMTにおいて問題となっている、メサエッチングした側面でのゲート電極と2次元電子ガスとの接触に起因する、漏れ電流の問題を、弗化水素による表面処理とSi超薄膜形成とを組み合わせて、界面を制御して絶縁体を推積することにより回避することに成功した。年限内に、良好な特性を有する2次元電子ガスMISFETの実現には到達しなかった。これは、ソース・ドレイン電極のオーミック接触の抵抗値を下げる技術を開発できなかったためであるが、今後この点が解決されれば、本研究により得られた成果と合わせて、良好な特性を持つ新しい素子が実現すると考えられる。
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(B))
    Date (from‐to) : 1993 -1994 
    Author : Hideki HASEGAWA, 赤澤 正道, 澤田 孝幸
     
    The purpose of the research is to investigate an interaction between the quantized energy levels and the surface/interface states in compound semiconductor quantum structures, and to investigate the applicability of the novel silicon-intelayr based passivation technique to passivation of compound semiconductor quantum structures. The main results are summarized below.(1) It has been shown that the photoluminescence (PL) intensity from the near-surface AlGaAs/GaAs quantum wells (QWs) decreases exponentially with decreasing the thickness of the top AlGaAs barrier layr below 10nm, and that thi...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(C))
    Date (from‐to) : 1992 -1993 
    Author : Masamichi AKAZAWA, 斉藤 俊也, 福井 孝志, 長谷川 英機
     
    The semiconductor carrier waves and their traveling wave interactions with the electromagnetic fields in InP and GaAs layrs using the metal-insulator-semiconductor (MIS)-type carrier confinement structure were studied. Traveling wave amplifier (TWA)-type devices were made and the admittance of the devices was measured. For the first time, the existence of carrier waves was observed from the drift velocity dependence of the admittance and two modes of interaction were observed from the frequency dependence of the drift velocity, which gave the reduction peaks of the conductance. To discuss t...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(B))
    Date (from‐to) : 1992 -1993 
    Author : Takashi FUKUI, 赤沢 正道, 長谷川 英機, 本久 順一
     
    GaAs and AlGaAs micro-Pyramidal Structures having four-fold symetry facets (011) were fabricated using selective area MOVPE on (001) GaAs substrates partlally masked with a SiO_2. In order to study accurate growth rate, wider mask-patterned substrates were used. Low pressure horizontal MOVPE reactor was used. Source materials were TMGa, TEAI, quality of micro-pyramidal structures were characterized by cleaved cross section image of scanning electron microscope (SEM) and photoluminescence (PL) from quantum well. The main results are as follows : The growth rate enhances in selective are grow...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(B))
    Date (from‐to) : 1991 -1992 
    Author : Hideki HASEGAWA, 飯塚 浩一, 赤沢 正道
     
    (1) A novel photoluminescence (PL)-based measurement method (PL Surface State Spectroscopy : PLS^3) for semiconductor surface state density, N_, was newly developed. It consists of detailed measurement of the band-edge photoluminescence efficiency as a function of the excitation intensity, and its rigorous analysis by computer. By this method, N_ distribution as well as the value of surface recombination velocity, S, can be determined in a contactless and nondestructive fashion. (2) The proposed PLS^3 technique was successfully applied for the first time for in-situ determination of...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(試験研究(B))
    Date (from‐to) : 1991 -1992 
    Author : Hideki HASEGAWA, 飯塚 浩一, 坪内 夏朗, 赤沢 正道
     
    For advanced image technologies including HDTVs, solid state imaging devices whose spatial resolution is much higher than today's standard is required. The spatial resolution of conventional Si CCDs is limited not by lithography, but by its indirect bandgap nature which makes the optical absorption layer inevitably thick, causing smearing of images due to carrier diffusion. This difficulty can be overcome by using a direct energy gap materials like InGaAs. However, compound semiconductor MIS interfaces generally possess high density of gap states which makes realization of MIS devices diffi...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(B))
    Date (from‐to) : 1990 -1991 
    Author : Hideo OHNO, 赤沢 正道, 飯塚 浩一, 長谷川 英機
     
    Molecular beam epitaxial (MBE) growth and electric and magnetic properties of diluted magnetic III-V semiconductors, especially (In, Mn) As, are studied. Following is a summary of the research results. Molecular Beam Epitaxial Growth : Maximum Mn concentration that can be incorporated into InAs lattice without having second phase (which is MnAs) is critically dependent on the growth temperature during MBE growth. At 300゚C, x (in In_<1-x>Mn_xAs) has to be<0.03 and the conduction is p-type whereas at 200゚C, x<0.25 and n-type.Characterization of Epitaxial layers : (1) Magnetism All n-type samp...
  • Ministry of Education, Culture, Sports, Science and Technology:Grants-in-Aid for Scientific Research(一般研究(B))
    Date (from‐to) : 1988 -1989 
    Author : 長谷川 英機, 長谷川 秀機, Hideki HASEGAWA, 大野 英男, 飯塚 浩一, 深井 一郎, 赤澤 正道
     
    The integration level of monolithic microwave integrated circuits (MMICs)is presently limited owing to large substrate area requirements for passive circuitry in spite of the advanced miniaturization of active semiconductor devices with fine-line lithography.In the present study, MIS (metal-insulator-semiconductor) and Schottky coplanar waveguides for application to MMICs are investigated theoretically and experimentally. They are formed on semi-insulating compound semiconductor substrates ( GaAs and InP) with epitaxial surface layers, and show remarkable slow-wave propagation due to distri...

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  • 特願2011-208741:電界効果トランジスタおよびその製造方法  2011年/09/26
    橋詰 保, 赤澤 正道, 廣木 正伸


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