研究者データベース

堀山 貴史(ホリヤマ タカシ)
情報科学研究院 情報理工学部門 知識ソフトウェア科学分野
教授

基本情報

所属

  • 情報科学研究院 情報理工学部門 知識ソフトウェア科学分野

職名

  • 教授

学位

  • 博士(情報学)(京都大学)

ホームページURL

科研費研究者番号

  • 60314530

J-Global ID

研究分野

  • 情報通信 / 情報学基礎論

職歴

  • 2019年09月 - 現在 北海道大学 大学院情報科学研究院 教授
  • 2007年04月 - 2019年08月 埼玉大学 大学院理工学研究科 准教授
  • 2002年07月 - 2007年03月 京都大学 大学院情報学研究科 助手
  • 1999年04月 - 2002年06月 奈良先端科学技術大学院大学 情報科学研究科 助手

学歴

  • 1998年10月 - 1999年03月   京都大学   大学院工学研究科   数理工学専攻
  • 1995年04月 - 1998年09月   京都大学   大学院工学研究科   情報工学専攻
  • 1991年04月 - 1995年03月   京都大学   工学部   情報工学科

所属学協会

  • European Association for Theoretical Computer Science (EATCS)   電子情報通信学会   情報処理学会   LAシンポジウム   

研究活動情報

論文

  • Takashi Horiyama, Fabian Klute, Matias Korman, Irene Parada, Ryuhei Uehara, Katsuhisa Yamanaka
    Computational Geometry 104 101860 - 101860 2022年06月 [査読有り]
  • Katsuhisa Yamanaka, Takashi Horiyama, Kunihiro Wasa
    Theoretical Computer Science 2021年01月
  • Katsuhisa Yamanaka, David Avis, Takashi Horiyama, Yoshio Okamoto, Ryuhei Uehara, Tanami Yamauchi
    Discrete Applied Mathematics 303 305 - 313 2020年04月 [査読有り][通常論文]
  • Yu Nakahata, Jun Kawahara, Takashi Horiyama, Shin-ichi Minato
    In Proceedings of the 14th International Conference and Workshops on Algorithms and Computation (WALCOM 2020) 12049 211 - 222 2020年 [査読有り][通常論文]
  • Koichi Mizunashi, Takashi Horiyama, Ryuhei Uehara
    WALCOM: Algorithms and Computation - 13th International Conference, WALCOM 2019, Guwahati, India, February 27 - March 2, 2019, Proceedings 277 - 288 Springer 2019年 [査読有り][通常論文]
  • Takashi Horiyama, Shin-ichi Nakano, Toshiki Saitoh, Koki Suetsugu, Akira Suzuki, Ryuhei Uehara, Takeaki Uno, Kunihiro Wasa
    Lecture Notes in Computer Science 291 - 300 2019年
  • Yu NAKAHATA, Jun KAWAHARA, Takashi HORIYAMA, Shoji KASAHARA
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E101.A 9 1363 - 1374 2018年09月01日 [査読有り][通常論文]
  • Dawei Xu, Jinfeng Huang, Yuta Nakane, Tomoo Yokoyama, Takashi Horiyama, Ryuhei Uehara
    IEICE Transactions 101-A 9 1420 - 1430 2018年09月 [査読有り][通常論文]
  • Katsuhisa Yamanaka, Takashi Horiyama, Takeaki Uno, Kunihiro Wasa
    The proceedings of the 30th Canadian Conference on Computational Geometry (CCCG 2018) 61 - 67 2018年08月 [査読有り][通常論文]
  • Katsuhisa Yamanaka, Takashi Horiyama, J. Mark Keil, David Kirkpatrick, Yota Otachi, Toshiki Saitoh, Ryuhei Uehara, Yushi Uno
    Theoretical Computer Science 729 1 - 10 2018年06月12日 [査読有り][通常論文]
     
    We investigate the computational complexity of the following problem. We are given a graph in which each vertex has an initial and a target color. Each pair of adjacent vertices can swap their current colors. Our goal is to perform the minimum number of swaps so that the current and target colors agree at each vertex. When the colors are chosen from {1,2,…,c}, we call this problem c-COLORED TOKEN SWAPPING since the current color of a vertex can be seen as a colored token placed on the vertex. We show that c-COLORED TOKEN SWAPPING is NP-complete for c=3 even if input graphs are restricted to connected planar bipartite graphs of maximum degree 3. We then show that 2-COLORED TOKEN SWAPPING can be solved in polynomial time for general graphs and in linear time for trees. Besides, we show that, the problem for complete graphs is fixed-parameter tractable when parameterized by the number of colors, while it is known to be NP-complete when the number of colors is unbounded.
  • Tianfeng Feng, Takashi Horiyama, Yoshio Okamoto, Yota Otachi, Toshiki Saitoh, Takeaki Uno, Ryuhei Uehara
    Combinatorial Algorithms - 29th International Workshop, IWOCA 2018, Singapore, July 16-19, 2018, Proceedings 177 - 188 Springer 2018年 [査読有り][通常論文]
  • Takashi Horiyama, Takashi Iizuka, Masashi Kiyomi, Yoshio Okamoto, Ryuhei Uehara, Takeaki Uno, Yushi Uno, Yukiko Yamauchi
    Journal of Information Processing 25 708 - 715 2017年08月01日 [査読有り][通常論文]
     
    We study a combinatorial game named '‘sankaku-tori’' in Japanese, which means '‘triangle-taking’' in English. It is an old pencil-and-paper game for two players played in Western Japan. The game is played on points on the plane in general position. In each turn, a player adds a line segment to join two points, and the game ends when a triangulation of the point set is completed. The player who completes more triangles than the other wins. In this paper, we formalize this game and investigate three restricted variants of this game. We first investigate a solitaire variant for a given set of points and line segments with two integers t and k, the problem asks if you can obtain t triangles after k moves. We show that this variant is NP-complete in general. The second variant is the standard two player version, but the points are in convex position. In this case, the first player has a nontrivial winning strategy. The last variant is a natural extension of the second one we have the points in convex position but one point inside. Then, it turns out that the first player has no winning strategy.
  • Dawei Xu, Takashi Horiyama, Toshihiro Shirakawa, Ryuhei Uehara
    COMPUTATIONAL GEOMETRY-THEORY AND APPLICATIONS 64 1 - 12 2017年08月 [査読有り][通常論文]
     
    We investigate common developments that can fold into plural incongruent orthogonal boxes. Recently, it was shown that there are infinitely many orthogonal polygons that fold into three boxes of different size. However, the smallest one that folds into three boxes consists of 532 unit squares. From the necessary condition, the smallest possible surface area that can fold into two boxes is 22, and the smallest possible surface area for three different boxes is 46. For the area 22, it has been shown that there are 2,263 common developments of two boxes by exhaustive search. However, the area 46 is too huge to search. In this paper, we focus on the polygons of area 30, which is the second smallest area of two boxes that admits to fold into two boxes of size 1 x 1 x 7 and 1 x 3 x 3. Moreover, when we fold along diagonal lines of rectangles of size 1 x 2, this area 30 may admit to fold into a box of size root 5 x root 5 x root 5. The results are summarized as follows. There exist 1,080 common developments of two boxes of size 1 x 1 x 7 and 1 x 3 x 3. Among them, there are nine common developments of three boxes of size 1 x 1 x 7, 1 x 3 x 3, and root 5 x root 5 x root 5. Interestingly, one of nine such polygons folds into three different boxes 1 x 1 x 7, 1 x 3 x 3, and root 5 x root 5 x root 5 in four different ways. (C) 2017 Elsevier B.V. All rights reserved.
  • Jun Kawahara, Takashi Horiyama, Keisuke Hotta, Shin-ichi Minato
    WALCOM: ALGORITHMS AND COMPUTATION, WALCOM 2017 10167 119 - 131 2017年 [査読有り][通常論文]
     
    A balanced graph partition on a vertex-weighted graph is a partition of the vertex set such that the partition has k parts and the disparity, which is defined as the ratio of the maximum total weight of parts to the minimum one, is at most r. In this paper, a novel algorithm is proposed that enumerates all the graph partitions with small disparity. Experimental results show that five millions of partitions with small disparity for some graph with more than 100 edges can be enumerated within ten minutes.
  • Dawei Xu, Takashi Horiyama, Ryuhei Uehara
    Proceedings of the 29th Canadian Conference on Computational Geometry, CCCG 2017, July 26-28, 2017, Carleton University, Ottawa, Ontario, Canada 62 - 67 2017年 [査読有り][通常論文]
  • Katsuhisa Yamanaka, Erik D. Demaine, Takashi Horiyama, Akitoshi Kawamura, Shin-ichi Nakano, Yoshio Okamoto, Toshiki Saitoh, Akira Suzuki, Ryuhei Uehara, Takeaki Uno
    Proc. of WALCOM: ALGORITHMS AND COMPUTATION, WALCOM 2017 LNCS 10167 435 - 447 2017年 [査読有り][通常論文]
     
    We consider a puzzle consisting of colored tokens on an nvertex graph, where each token has a distinct starting vertex and a set of allowable target vertices for it to reach, and the only allowed transformation is to "sequentially" move the chosen token along a path of the graph by swapping it with other tokens on the path. This puzzle is a variation of the Fifteen Puzzle and is solvable in O(n(3)) token-swappings. We thus focus on the problem of minimizing the number of token-swappings to reach the target token-placement. We first give an inapproximability result of this problem, and then show polynomial-time algorithms on trees, complete graphs, and cycles.
  • Nagahata Y, Maeda S, Teramoto H, Horiyama T, Taketsugu T, Komatsuzaki T
    The journal of physical chemistry. B 120 8 1961 - 1971 2016年03月 [査読有り][通常論文]
  • Yoshiaki Araki, Takashi Horiyama, Ryuhei Uehara
    Journal of Graph Algorithms and Applications 20 1 101 - 104 2016年 [査読有り][通常論文]
     
    In this paper, we investigate the common unfolding between regular tetrahedra and Johnson-Zalgaller solids. More precisely, we investigate the sets of all edge developments of Johnson-Zalgaller solids that fold into regular tetrahedra. We show that, among 92 Johnson-Zalgaller solids, only J17 (gyroelongated square dipyramid) and J84 (snub disphenoid) have some edge developments that fold into a regular tetrahedron, and the remaining Johnson-Zalgaller solids do not have any such edge development.
  • Hugo A. Akitaya, Kenneth C. Cheung, Erik D. Demaine, Takashi Horiyama, Thomas C. Hull, Jason S. Ku, Tomohiro Tachi, Ryuhei Uehara
    DISCRETE AND COMPUTATIONAL GEOMETRY AND GRAPHS, JCDCGG 2015 9943 167 - 179 2016年 [査読有り][通常論文]
     
    Flat foldability of general crease patterns was first claimed to be hard for over twenty years. In this paper we prove that deciding flat foldability remains NP-complete even for box pleating, where creases form a subset of a square grid with diagonals. In addition, we provide new terminology to implicitly represent the global layer order of a flat folding, and present a new planar reduction framework for grid-aligned gadgets.
  • Takashi Horiyama, Ryuhei Uehara, Haruo Hosoya
    8th International Conference on Fun with Algorithms, FUN 2016, June 8-10, 2016, La Maddalena, Italy 20:1-20:14  Schloss Dagstuhl - Leibniz-Zentrum fuer Informatik 2016年 [査読有り][通常論文]
  • Dawei Xu, Takashi Horiyama, Toshihiro Shirakawa, Ryuhei Uehara
    THEORY AND APPLICATIONS OF MODELS OF COMPUTATION (TAMC 2015) 9076 236 - 247 2015年 [査読有り][通常論文]
     
    We investigate common developments that can fold into plural incongruent orthogonal boxes. Recently, it was shown that there are infinitely many orthogonal polygons that folds into three boxes of different size. However, the smallest one that folds into three boxes consists of 532 unit squares. From the necessary condition, the smallest possible surface area that can fold into two boxes is 22, which admits to fold into two boxes of size 1x1x5 and 1x2x3. On the other hand, the smallest possible surface area for three different boxes is 46, which may admit to fold into three boxes of size 1x1x11, 1x2x7, and 1x3x5. For the area 22, it has been shown that there are 2,263 common developments of two boxes by exhaustive search. However, the area 46 is too huge for search. In this paper, we focus on the polygons of area 30, which is the second smallest area of two boxes that admits to fold into two boxes of size 1x1x7 and 1x3x3. Moreover, when we admit to fold along diagonal lines of rectangles of size 1x2, the area may admit to fold into a box of size root 5x root 5x root 5. That is, the area 30 is the smallest candidate area for folding three different boxes in this manner. We perform two algorithms. The first algorithm is based on ZDDs, zero-suppressed binary decision diagrams, and it computes in 10.2 days on a usual desktop computer. The second algorithm performs exhaustive search, however, straightforward implementation cannot be run even on a supercomputer since it causes memory overflow. Using a hybrid search of DFS and BFS, it completes its computation in 3 months on a supercomputer. As results, we obtain (1) 1,080 common developments of two boxes of size 1x1x7 and 1x3x3, and (2) 9 common developments of three boxes of size 1x1x7, 1x3x3, and root 5 x root 5 x root 5.
  • Yoshiaki Araki, Takashi Horiyama, Ryuhei Uehara
    WALCOM: Algorithms and Computation - 9th International Workshop, WALCOM 2015, Dhaka, Bangladesh, February 26-28, 2015. Proceedings 8973 294 - 305 Springer 2015年 [査読有り][通常論文]
     
    Common unfolding of a regular tetrahedron and a Johnson-Zalgaller solid is investigated. More precisely, we investigate the sets of all edge unfoldings of Johnson-Zalgaller solids. Among 92 Johnson-Zalgaller solids, some of edge unfolding of J17 and J84 admit to fold into a regular tetrahedron. On the other hand, there are no edge unfolding of the other Johnson-Zalgaller solids that admit to fold into a regular tetrahedron.WALCOM: Algorithms and Computation, 9th International Workshop, WALCOM 2015, Dhaka, Bangladesh, February 26-28, 2015. Proceedings
  • Katsuhisa Yamanaka, Takashi Horiyama, David Kirkpatrick, Yota Otachi, Toshiki Saitoh, Ryuhei Uehara, Yushi Uno
    Lecture Notes in Computer Science (including subseries Lecture Notes in Artificial Intelligence and Lecture Notes in Bioinformatics) 9214 619 - 628 2015年 [査読有り][通常論文]
     
    We investigate the computational complexity of the following problem. We are given a graph in which each vertex has the current and target colors. Each pair of adjacent vertices can swap their current colors. Our goal is to perform the minimum number of swaps so that the current and target colors agree at each vertex. When the colors are chosen from {1, 2,..., c}, we call this problem c-COLORED TOKEN SWAPPING since the current color of a vertex can be seen as a colored token placed on the vertex. We show that c-COLORED TOKEN SWAPPING is NP-complete for every constant c ≥ 3 even if input graphs are restricted to connected planar bipartite graphs of maximum degree 3. We then show that 2-COLORED TOKEN SWAPPING can be solved in polynomial time for general graphs and in linear time for trees.
  • Jinhee Chun, Takashi Horiyama, Takehiro Ito, Natsuda Kaothanthong, Hirotaka Ono, Yota Otachi, Takeshi Tokuyama, Ryuhei Uehara, Takeaki Uno
    THEORETICAL COMPUTER SCIENCE 555 71 - 84 2014年10月 [査読有り][通常論文]
     
    A base-monotone region with a base is a subset of the cells in a pixel grid such that if a cell is contained in the region then so are the ones on a shortest path from the cell to the base. The problem of decomposing a pixel grid into disjoint base-monotone regions was first studied in the context of image segmentation. It is known that for a given pixel grid and base-lines, one can compute in polynomial time a maximum-weight region that can be decomposed into disjoint base-monotone regions with respect to the given baselines (Chun et al., 2012 [4]). We continue this line of research and show the NP-hardness of the problem of optimally locating k base-lines in a given n x n pixel grid. We then present an O (n(3))-time 2-approximation algorithm for this problem. We also study two related problems, the k base-segment problem and the quad-decomposition problem, and present some complexity results for them. (C) 2013 Elsevier B.V. All rights reserved.
  • Zachary Abel, Erik D. Demaine, Martin L. Demaine, Takashi Horiyama, Ryuhei Uehara
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E97A 6 1206 - 1212 2014年06月 [査読有り][通常論文]
     
    We prove NP-completeness of deciding whether a given loop of colored right isosceles triangles, hinged together at edges, can be folded into a specified rectangular three-color pattern. By contrast, the same problem becomes polynomially solvable with one color or when the target shape is a tree-shaped polyomino.
  • Takashi Horiyama, Masashi Kiyomi, Yoshio Okamoto, Ryuhei Uehara, Takeaki Uno, Yushi Uno, Yukiko Yamauchi
    FUN WITH ALGORITHMS 8496 230 - 239 2014年 [査読有り][通常論文]
     
    We study a combinatorial game named "sankaku-tori" in Japanese, which means "triangle-taking" in English. It is an old pencil-and-paper game for two players played in Western Japan. The game is played on points on the plane in general position. In each turn, a player adds a line segment to join two points, and the game ends when a triangulation of the point set is completed. The player who completes more triangles than the other wins. In this paper, we consider two restricted variants of this game. In the first variant, the first player always wins in a nontrivial way, and the second variant is NP-complete in general.
  • ABEL ZACHARY, DEMAINE ERIK D., DEMAINE MARTIN L., HORIYAMA TAKASHI, UEHARA RYUHEI
    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 113 50 33 - 38 一般社団法人電子情報通信学会 2013年05月17日 
    In one of the first papers about the complexity of puzzles, Robertson and Munro [12] proved that a generalized form of the then-popular Instant Insanity puzzle is NP-complete. Here we study several variations of this puzzle, exploring how the complexity depends on the piece shapes and the allowable orientations of those shapes.
  • Jinhee Chun, Takashi Horiyama, Takehiro Ito, Natsuda Kaothanthong, Hirotaka Ono, Yota Otachi, Takeshi Tokuyama, Ryuhei Uehara, Takeaki Uno
    WALCOM: Algorithms and Computation, 7th International Workshop, WALCOM 2013, Kharagpur, India, February 14-16, 2013. Proceedings 7748 53 - 64 Springer 2013年 [査読有り][通常論文]
     
    The problem of decomposing a pixel grid into base-monotoneregions was first studied in the context of image segmentation. It is known that for a given n × n pixel grid and baselines, one can compute in O(n^3) time a maximum-weight region that can be decomposed into disjoint base-monotone regions [Chun et al. ISAAC 2009]. To complement this fact, we first show the NP-hardness of the problem of optimally locating k baselines in a given pixel grid. Next we present an O(n^3)-time 2-approximation algorithm for this problem. We also study some polynomial-time solvable cases, and variants of the problem.WALCOM: Algorithms and Computation, 7th International Workshop, WALCOM 2013, Kharagpur, India, February 14-16, 2013. Proceedings
  • Xin Man, Takashi Horiyama, Shinji Kimura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A 8 1347 - 1358 2012年08月 [査読有り][通常論文]
     
    Clock gating is supported by commercial tools as a power optimization feature based on the guard signal described in HDL (structural method). However, the identification of control signals for gated registers is hard and designer-intensive work. Besides, since the clock gating cells also consume power, it is imperative to minimize the number of inserted clock gating cells and their switching activities for power optimization. In this paper, we propose an automatic multi-stage clock gating algorithm with ILP (Integer Linear Programming) formulation, including clock gating control candidate extraction, constraints construction and optimum control signal selection. By multi-stage clock gating, unnecessary clock pulses to clock gating cells can be avoided by other clock gating cells, so that the switching activity of clock gating cells can be reduced. We find that any multi-stage control signals are also single-stage control signals, and any combination of signals can be selected from single-stage candidates. The proposed method can be applied to 3 or more cascaded stages. The multi-stage clock gating optimization problem is formulated as constraints in LP format for the selection of cascaded clock-gating order of multi-stage candidate combinations, and a commercial ILP solver (IBM CPLEX) is applied to obtain the control signals for each register with minimum switching activity. Those signals are used to generate a gate level description with guarded registers from original design, and a commercial synthesis and layout tools are applied to obtain the circuit with multi-stage clock gating. For a set of benchmark circuits and a Low Density Parity Check (LDPC) Decoder (6.6k gates, 212 F.F.s), the proposed method is applied and actual power consumption is estimated using Synopsys NanoSim after layout. On average, 31% actual power reduction has been obtained compared with original designs with structural clock gating, and more than 10% improvement has been achieved for some circuits compared with single-stage optimization method. CPU time for optimum multi-stage control selection is several seconds for up to 25k variables in LP format. By applying the proposed clock gating, area can also be reduced since the multiplexors controlling register inputs are eliminated.
  • Takashi Horiyama, Takehiro Ito, Keita Nakatsuka, Akira Suzuki, Ryuhei Uehara
    Proceedings of the 24th Canadian Conference on Computational Geometry(CCCG) 211 - 216 2012年
  • Xin Man, Takashi Horiyama, Shinji Kimura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E93A 12 2472 - 2480 2010年12月 [査読有り][通常論文]
     
    Clock gating is the insertion of control signal for registers to switch off unnecessary clock signals selectively without violating the functional correctness of the original design so as to reduce the dynamic power consumption Commercial EDA tools usually have a mechanism to generate clock gating logic based on the structural method where the con trol signals specified by designers are used and the effectiveness of the clock gating depends on the specified control signals In the research we focus on the automatic clock gating logic generation and propose a method based on the candidate extraction and control signal selection We formalize the control signal selection using linear formulae and devise an optimization method based on BDD The method is effective for circuits with a lot of shared candidates by different registers The method is applied to counter circuits to check the co relation with power simulation results and a set of benchmark circuits 19 1-71 9% power reduction has been found on counter circuitsafter layout and 2 3-18 0% cost reduction on benchmark circuits
  • Takashi Horiyama, Hiro Ito, Kazuo Iwama, Jun Kawahara
    INTERNATIONAL CONFERENCE ON INFORMATICS EDUCATION AND RESEARCH FOR KNOWLEDGE-CIRCULATING SOCIETY, PROCEEDINGS 193 - + 2008年 [査読有り][通常論文]
     
    With the advances of modern computer technologies and elaborated algorithm design methodologies, it becomes important to enumerate all feasible solutions for given constraints. In this paper, we propose algorithms for enumerating Tsume-Shogi diagrams (i.e., Shogi. mating problems) by the reverse method. Conventional algorithms always take the principle 'generate candidate diagrams and sieve them by Tsume-Shogi solvers,' which tends to require lengthy execution time. In our approach, the reverse method enables us to enumerate all diagrams without using Tsume-Shogi solvers. We can sieve the candidates easily and quickly, since the), are generated in the ascending order according to the number of necessary moves for mating the defender's king. We have implemented the proposed algorithms, and enumerated all diagrams with several restrictions (e.g., those with only four knights). From this result, we prove many results for knight diagrams, e.g., i) the maximum number of moves is 11, ii) it is 13 for additional mate free, iii) it is 7 if at least one piece is in hand of the attacker, and iv) the maximum pieces in hand of the attacker is two.
  • N. Doi, T. Horiyama, M. Nakanishi, S. Kimura
    IEICE Trans. Fundamentals E89-A 12 3427 - 3434 一般社団法人電子情報通信学会 2006年12月 [査読有り][通常論文]
     
    High-level synthesis is a novel method to generate a RT-level hardware description automatically from a high-level language such as C, and is used at recent digital circuit design. Floating-point to fixed-point conversion with bit-length optimization is one of the key issues for the area and speed optimization in high-level synthesis. However, the conversion task is a rather tedious work for designers. This paper introduces automatic bit-length optimization method on floating-point to fixed-point conversion for high-level synthesis. The method estimates computational errors statistically, and formalizes an optimization problem as a non-linear problem. The application of NLP technique improves the balancing between computational accuracy and total hardware cost. Various constraints such as unit sharing, maximum bit-length of function units can be modeled easily, too. Experimental result shows that our method is fast compared with typical one, and reduces the hardware area.
  • Takashi Horiyama, Kazuo Iwama, Jun Kawahara
    In Proceedings of the 17th International Symposium on Algorithms and Computation (ISAAC 2006) 4288 71 - 80 2006年12月 [査読有り][通常論文]
  • Youichi Hanatani, Takashi Horiyama, Kazuo Iwama
    Discrete Applied Mathematics 154 16 2263 - 2270 2006年11月01日 [査読有り][通常論文]
     
    The following problem is considered: given a Boolean formula f, generate another formula g such that: (i) If f is unsatisfiable then g is also unsatisfiable. (ii) If f is satisfiable then g is also satisfiable and furthermore g is "easier" than f. For the measure of this easiness, we use the density of a formula f which is defined as (the number of satisfying assignments)/2n, where n is the number of Boolean variables of f. In this paper, we mainly consider the case that the input formula f is given as a 3-CNF formula and the output formula g may be any formula using Boolean AND, OR and negation. Two different approaches to this problem are presented: one is to obtain g by reducing the number of variables and the other by increasing the number of variables, both of which are based on existing SAT algorithms. Our performance evaluation shows that, a little surprisingly, better SAT algorithms do not always give us better density-condensation algorithms. © 2006 Elsevier B.V. All rights reserved.
  • An Optimization Method in Floating-point to Fixed-point Conversion using Positive and Negative Error Analysis and Sharing of Operations
    N. Doi, T. Horiyama, M. Nakanishi, S. Kimura
    Proc. of the 12th Workshop on Synthesis And System Integration of Mixed Information technologies(SASIMI 2004) 466 - 471 2004年10月 [査読有り][通常論文]
  • T Horiyama, T Ibaraki
    DISCRETE APPLIED MATHEMATICS 142 1-3 151 - 163 2004年08月 [査読有り][通常論文]
     
    We consider problems of reasoning with a knowledge-base, which is represented by an ordered binary decision diagram, for two cases of general and Horn knowledge-bases. Our main results say that both finding a model of a knowledge-base and deducing from a knowledge-base can be done in linear time for a general knowledge-base, but that abduction is NP-complete even for a Horn knowledge-base. Then, we consider abduction when its assumption set consists of all propositional literals (i.e., an answer for a given query is allowed to include any positive literals), and show that it can be done in polynomial time if the knowledge-base is Horn, while it remains NP-complete for the general case. Some other solvable cases are also discussed. (C) 2004 Elsevier B.V. All rights reserved.
  • Y Hanatani, T Horiyama, K Iwama
    THEORY AND APPLICATIONS OF SATISFIABILITY TESTING 2919 69 - 77 2004年 [査読有り][通常論文]
     
    The following problem is considered: Given a Boolean formula f, generate another formula g such that: (i) If f is unsatisfiable then g is also unsatisfiable. (ii) If f is satisfiable then g is also satisfiable and furthermore g is "easier" than f. For the measure of this easiness, we use the density of a formula f which is defined as (the number of satisfying assignments) / 2(n), where n is the number of Boolean variables of f. In this paper, we mainly consider the case that the input formula f is given as a 3-CNF formula and the output formula g may be any formula using Boolean AND, OR and negation. Two different approaches to this problem axe presented: One is to obtain g by reducing the number of variables and the other by increasing the number of variables, both of which are based on existing SAT algorithms. Our performance evaluation shows that, a little surprisingly, better SAT algorithms do not always give us better density-condensation algorithms. This is a preliminary report of the on-going research.
  • Minimization of Fractional Wordlength on Fixed-Point Conversion for High-Level Synthesis
    N. Doi, T. Horiyama, M. Nakanishi, S. Kimura
    In. Proc. of Asia and South Pacific Design Automation Conference 2004 (ASP-DAC 2004) 80 - 85 2004年01月 [査読有り][通常論文]
  • N. Doi, T. Horiyama, M. Nakanishi, S. Kimura, K. Watanabe
    IEICE Trans. Fundamentals E86-A 12 3184 - 3191 一般社団法人電子情報通信学会 2003年12月 [査読有り][通常論文]
     
    In the hardware synthesis from a high-level language such as C, the bit length of variables is one of the key issues for the area and speed optimization. Usually, designers are required to optimize the bit-length of each variable manually using the time-consuming simulation on huge-data. In this paper, we propose an optimization method of the fractional bit length in the conversion from floating-point variables to fixed-point variables. The method is based on error propagation and the backward propagation of the accuracy limitation. The method is fully analytical and fast compared to simulation based methods.
  • N. Doi, T. Horiyama, M. Nakanishi, S. Kimura, K. Watanabe
    Proc. of 12th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2003) 129 - 136 2003年04月 [査読有り][通常論文]
  • T Horiyama, T Ibaraki
    INFORMATION PROCESSING LETTERS 85 4 191 - 198 2003年02月 [査読有り][通常論文]
     
    We consider translation among conjunctive normal forms (CNFs), characteristic models, and ordered binary decision diagrams (OBDDs) of Boolean functions. It is shown in this paper that Horn OBDDs can be translated into their Horn CNFs in polynomial time. As for the opposite direction, the problem can be solved in polynomial time if the ordering of variables in the resulting OBDD is specified as an input. In case that such ordering is not specified and the resulting OBDD must be of minimum size, its decision version becomes NP-complete. Similar results are also obtained for the translation in both directions between characteristic models and OBDDs. We emphasize here that the above results hold on any class of functions having a basis of polynomial size. (C) 2002 Elsevier Science B.V. All rights reserved.
  • An On-Chip High Speed Serial Communication Method Based on Independent Ring Oscillators
    S. Kimura, T. Hayakawa, T. Horiyama, M. Nakanishi, K. Watanabe
    Proc. of International Solid-State Circuits Conference (ISSCC2003) 390 - 391 2003年02月 [査読有り][通常論文]
  • S Kimura, A Ishii, T Horiyama, M Nakanishi, H Kajihara, K Watanabe
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E85A 12 2701 - 2707 2002年12月 [査読有り][通常論文]
     
    The paper describes the folding method of logic functions to reduce the size of memories to keep the functions. The folding is based on the relation of fractions of logic functions. If the logic function includes 2 or 3 same parts, then only one part should be kept and other parts can be omitted. We show that the logic function of I-bit addition can be reduced to half size using the bit-wise NOT relation and the bit-wise OR relation. The paper also introduces 3-1 LUT's with the folding mechanism. A full adder can be implemented using only one 3-1 LUT with the folding. Multi-bit AND and OR operations can be mapped to our LUT's not using the extra cascading circuit but using the carry circuit for addition. We have also tested the mapping capability of 4 input functions to our 3-1 LUT's with folding and carry propagation mechanisms. We have shown the reduction of the area consumption when using our LUT's compared to the case using 4-1 LUT's on several benchmark circuits.
  • S. Kimura, T. Horiyama, M. Nakanishi, H. Kajihara
    Proc. of International Conference on Computer Aided Design (ICCAD2002) 694 - 698 2002年11月 [査読有り][通常論文]
  • T Horiyama, T Ibaraki
    ARTIFICIAL INTELLIGENCE 136 2 189 - 213 2002年04月 [査読有り][通常論文]
     
    We consider the use of ordered binary decision diagrams (OBDDs) as a means of realizing knowledge-bases, and show that, from the view point of space requirement, the OBDD-based representation is more efficient and suitable in some cases, compared with the traditional CNF-based and/or model-based representations. We then present polynomial time algorithms for the two problems of testing whether a given OBDD represents a unate Boolean function, and of testing whether it represents a Horn function. (C) 2002 Published by Elsevier Science B.V.
  • T Horiyama, T Ibaraki
    ALGORITHM AND COMPUTATION, PROCEEDINGS 1969 120 - 131 2001年 [査読有り][通常論文]
     
    We consider problems of reasoning with a knowledge-base, which is represented by an ordered binary decision diagram (OBDD), for two special cases of general and Horn knowledge-bases. Our main results say that both finding a, model of a knowledge-base and deducing from a knowledge-base. can be done in linear time for general case, but that abduction is NP-complete even if the knowledge-base is restricted to be Horn. Then, we consider the abduction when its assumption set consists of all propositional literals (i.e., an answer for a given query is allowed to include any positive literals), and show that it can be done in polynomial time if the knowledge-base is Horn, while it remains NP-complete for the general case. Some other solvable cases axe also discussed.
  • T Horiyama, T Ibaraki
    ALGORITHMS AND COMPUTATION, PROCEEDINGS 2223 231 - 243 2001年 [査読有り][通常論文]
     
    We consider translation among conjunctive normal forms (CNFs), characteristic models, and ordered binary decision diagrams (OBDDs) of Boolean functions. It is shown in this paper that Horn OBDDs can be translated into their CNFs in polynomial time. As for the opposite direction, the problem can be solved in polynomial time if the ordering of variables in the resulting OBDD is specified as an input. In case that such ordering is not specified and the resulting OBDD must be of minimum size, its decision version becomes NP-complete. Similar results are also obtained for the translation in both directions between characteristic models and OBDDs. We emphasize here that the above results holds on any class of functions having a basis B with \B\ = d.
  • T Horiyama, T Ibaraki
    ALGORITHMS AND COMPUTATIONS 1741 83 - 92 2000年 [査読有り][通常論文]
     
    We propose to make use of ordered binary decision diagrams (OBDDs) as a means of realizing knowledge-bases. We show that the OBDD-based representation is more efficient and suitable in some cases, compared with the traditional CNF-based and/or model-based representations in the sense of space requirement. We then consider two recognition problems of OBDDs, and present polynomial time algorithms for testing whether a given OBDD represents a unate Boolean function, and whether it represents a Horn function.

講演・口頭発表等

  • polyomino の p4 タイリングの列挙  [通常講演]
    列挙アルゴリズム合宿 2009年
  • 金図式、銀図式、桂馬図式の完全列挙  [通常講演]
    組合せゲーム・パズル ミニプロジェクト 研究集会 2009年
  • Enumeration of Polyominoes of p4 Tiling by the Reverse Search  [通常講演]
    LAシンポジウム講演録 2009年
  • polyomino の p4 タイリングの列挙  [通常講演]
    列挙アルゴリズム合宿 2009年
  • 金図式、銀図式、桂馬図式の完全列挙  [通常講演]
    組合せゲーム・パズル ミニプロジェクト 研究集会 2009年
  • Enumeration of Polyominoes of p4 Tiling by the Reverse Search  [通常講演]
    LAシンポジウム講演録 2009年
  • FOCS 2008 報告  [通常講演]
    電子情報通信学会技術研究報告 2008年
  • Fine-Grained Power Gating Based on the Controlling Value of Logic Gates  [通常講演]
    電子情報通信学会技術研究報告 2008年
  • 飛び道具を考慮した逆算法に基づく詰将棋列挙技術  [通常講演]
    電子情報通信学会総合大会 2008年
  • 飛び道具を考慮した逆算法に基づく詰将棋列挙技術  [通常講演]
    特定領域研究 新世代の計算限界 ミニ研究集会 2008年
  • FOCS 2008 報告  [通常講演]
    電子情報通信学会技術研究報告 2008年
  • Fine-Grained Power Gating Based on the Controlling Value of Logic Gates  [通常講演]
    電子情報通信学会技術研究報告 2008年
  • 飛び道具を考慮した逆算法に基づく詰将棋列挙技術  [通常講演]
    電子情報通信学会総合大会 2008年
  • 飛び道具を考慮した逆算法に基づく詰将棋列挙技術  [通常講演]
    特定領域研究 新世代の計算限界 ミニ研究集会 2008年
  • The Complexity of the Hajos Calculus on Planar Graphs  [通常講演]
    電子情報通信学会技術研究報告 2007年
  • The Complexity of the Hajos Calculus on Planar Graphs  [通常講演]
    LAシンポジウム講演録 2007年
  • The Complexity of the Hajos Calculus on Planar Graphs  [通常講演]
    電子情報通信学会技術研究報告 2007年
  • The Complexity of the Hajos Calculus on Planar Graphs  [通常講演]
    LAシンポジウム講演録 2007年

その他活動・業績

  • Yu Nakahata, Jun Kawahara, Takashi Horiyama, Shin-ichi Minato CoRR abs/1911.07465 2019年11月 [査読無し][通常論文]
  • Takashi Horiyama, Jun Kawahara, Shin-ichi Minato, Yu Nakahata CoRR abs/1904.09438 2019年 [査読無し][通常論文]
  • YAMANAKA KATSUHISA, HORIYAMA TAKASHI, UNO TAKEAKI, WASA KUNIHIRO 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 118 (295) 1 -6 2018年11月12日
  • YAMANAKA KATSUHISA, HORIYAMA TAKASHI, UNO TAKEAKI, WASA KUNIHIRO 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 118 (296) 1 -6 2018年11月12日
  • Akagi Toshihiro, Araki Tetsuya, Horiyama Takashi, Nakano Shin-Ichi, Okamoto Yoshio, Otachi Yota, Saitoh Toshiki, Uehara Ryuhei, Uno Takeaki, Wasa Kunihiro Lecture Notes in Computer Science (10823) 263 -272 2018年03月21日 
    Given a set P of n elements, and a function d that assigns a non-negative real number d(p, q) for each pair of elements p,q∈P, we want to find a subset S⊆P with |S|=k such that cost(S)=min{d(p,q)∣p,q∈S} is maximized. This is the max-min k-dispersion problem. In this paper, exact algorithms for the max-min k-dispersion problem are studied. We first show the max-min k-dispersion problem can be solved in O(n^<ωk>/^3logn) time. Then, we show two special cases in which we can solve the problem quickly.
  • 伝住周平, 堀山貴史, 栗田和宏, 中畑裕, 鈴木浩史, 和佐州洋, 山崎一明 電子情報通信学会技術研究報告 118 (216(COMP2018 9-20)(Web)) 2018年
  • Horiyama Takashi, Ito Takehiro, Ono Hirotaka, Otachi Yota, Uehara Ryuhei, Uno Takeaki 数理解析研究所講究録 1799 123 -129 2012年06月
  • 堀山 貴史, 鮫島 真人 数理解析研究所講究録 1649 55 -57 2009年05月
  • Enumeration of Polyominoes for p4 Isohedral Tiling by the Reverse Search
    T. Horiyama, M. Samejima Proc. of the 2nd Asian Association for Algorithms and Computation Annual Meeting (to appear) 2009年 [査読無し][通常論文]
  • Enumeration of Polyominoes for p4 Isohedral Tiling by the Reverse Search
    T. Horiyama, M. Samejima Proc. of the 2nd Asian Association for Algorithms and Computation Annual Meeting (to appear) 2009年 [査読無し][通常論文]
  • Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A (12) 3531 -3538 2008年12月 [査読無し][通常論文]
     
    Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed, In the proposed method, sleep signals of the power-gated blocks are extracted completely front the original circuits Without any extra logic element. A basic algorithm and it probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could he power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. we also show a power optimizition method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
  • Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A (12) 3531 -3538 2008年12月 [査読無し][通常論文]
     
    Leakage power consumption of logic elements has become a serious problem, especially in the sub-100-nanometer process. In this paper, a novel power gating approach by using the controlling value of logic elements is proposed, In the proposed method, sleep signals of the power-gated blocks are extracted completely front the original circuits Without any extra logic element. A basic algorithm and it probability-based heuristic algorithm have been developed to implement the basic idea. The steady maximum delay constraint has also been introduced to handle the delay issues. Experiments on the ISCAS'85 benchmarks show that averagely 15-36% of logic elements could he power gated at a time for random input patterns, and 3-31% of elements could be stopped under the steady maximum delay constraints. we also show a power optimizition method for AND/OR tree circuits, in which more than 80% of gates can be power-gated.
  • Yoichi Hanatani, Takashi Horiyama, Kazuo Iwama, Suguru Tamaki IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A (9) 2301 -2307 2008年09月 [査読無し][通常論文]
     
    The Hajos calculus is a nondeterministic procedure which generates the class of non-3-colorable graphs. If all non-3-colorable graphs can be constructed in polynomial steps by the calculus, then NP = co-NP holds. Up to date, however, it remains open whether there exists a family of graphs that cannot be generated in polynomial steps. To attack this problem, we propose two graph calculi PHC and PHC that generate non-3-colorable planar graphs, where intermediate graphs in the calculi are also restricted to be planar. Then we prove that PHC and PHC are sound and complete. We also show that PHC can polynomially simulate PHC.
  • Yoichi Hanatani, Takashi Horiyama, Kazuo Iwama, Suguru Tamaki IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E91A (9) 2301 -2307 2008年09月 [査読無し][通常論文]
     
    The Hajos calculus is a nondeterministic procedure which generates the class of non-3-colorable graphs. If all non-3-colorable graphs can be constructed in polynomial steps by the calculus, then NP = co-NP holds. Up to date, however, it remains open whether there exists a family of graphs that cannot be generated in polynomial steps. To attack this problem, we propose two graph calculi PHC and PHC that generate non-3-colorable planar graphs, where intermediate graphs in the calculi are also restricted to be planar. Then we prove that PHC and PHC are sound and complete. We also show that PHC can polynomially simulate PHC.
  • Chen Lei, Horiyama Takashi, Nakamura Yuichi, KIMURA Shinji 電子情報通信学会技術研究報告. VLD, VLSI設計技術 108 (23) 19 -24 2008年05月09日 
    Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating approach based on the controlling value of logic gates is proposed for leakage power reduction. In the method, sleep signals of the power-gated blocks are extracted based on the probability of the controlling value of logic gates without any extra control logic. A basic algorithm and a probability-based heuristic algorithm have been developed to implement this method. The steady maximum delay constraint has also been introduced to handle the delay overhead. Experiments on the ISCAS'85 benchmarks show the effectiveness of our algorithms and the effect on the extra delay.
  • Lei Chen, Takashi Horiyama, Yuichi Nakamura, Shinji Kimura 情報処理学会研究報告システムLSI設計技術(SLDM) 2008 (38) 55 -60 2008年05月01日 
    Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating approach based on the controlling value of logic gates is proposed for leakage power reduction. In the method sleep signals of the power-gated blocks are extracted based on the probability of the controlling value of logic gates without any extra control logic. A basic algorithm and a probability-based heuristic algorithm have been developed to implement this method. The steady maximum delay constraint has also been introduced to handle the delay overhead. Experiments on the ISCAS'85 benchmarks show the effectiveness of our algorithms and the effect on the extra delay.Leakage power dissipation of logic gates has become an increasingly important problem. A novel fine-grained power gating approach based on the controlling value of logic gates is proposed for leakage power reduction. In the method, sleep signals of the power-gated blocks are extracted based on the probability of the controlling value of logic gates without any extra control logic. A basic algorithm and a probability-based heuristic algorithm have been developed to implement this method. The steady maximum delay constraint has also been introduced to handle the delay overhead. Experiments on the ISCAS'85 benchmarks show the effectiveness of our algorithms and the effect on the extra delay.
  • Density Condensation of Boolean Formulas Based on Covering Codes
    T. Horiyama, A. Sato Proc. of the 1st Asian Association for Algorithms and Computation Annual Meeting 1 28 2008年 [査読無し][通常論文]
  • Density Condensation of Boolean Formulas Based on Covering Codes
    T. Horiyama, A. Sato Proc. of the 1st Asian Association for Algorithms and Computation Annual Meeting 1 28 2008年 [査読無し][通常論文]
  • Resynthesis Method for Circuit Acceleration on LUT-based FPGA
    W. Xing, T. Horiyama, S. Kuromaru, T. Kimura, S. Kimura Proc. of the 14th Workshop on Synthesis And System Integration of Mixed Information Technologies 14 375 -380 2007年 [査読無し][通常論文]
  • Truthful Auctions with Limited Range of Bids
    T. Horiyama, K. Iwama, D. Sumita Proc. of the 5th Hungarian-Japanese Symposium on Discrete Mathematics and Its Applications 5 53 -61 2007年 [査読無し][通常論文]
  • Resynthesis Method for Circuit Acceleration on LUT-based FPGA
    W. Xing, T. Horiyama, S. Kuromaru, T. Kimura, S. Kimura Proc. of the 14th Workshop on Synthesis And System Integration of Mixed Information Technologies 14 375 -380 2007年 [査読無し][通常論文]
  • Truthful Auctions with Limited Range of Bids
    T. Horiyama, K. Iwama, D. Sumita Proc. of the 5th Hungarian-Japanese Symposium on Discrete Mathematics and Its Applications 5 53 -61 2007年 [査読無し][通常論文]
  • 阿武 孝文, 堀山 貴史, 岩間 一雄 数理解析研究所講究録 1489 188 -194 2006年05月
  • 土井 伸洋, 堀山 貴志, 中西 正樹, 木村 晋二 情報処理学会研究報告システムLSI設計技術(SLDM) 2005 (27) 133 -138 2005年03月18日 
    ハードウェア設計においては浮動小数点演算の固定小数点演算化が面積速度の点から重要であるが,変換においては演算誤差を考慮してビット最適化が必要であることから,人手による変換は困難であった.そこで我々はビット長最適化問題を非線形問題へ帰着させて解く自動化手法の研究を行っている.一般的な非線形計画法では探索により整数解を求める方法を示す.This paper presents bit-length optimization technique for high-level synthesis based on non-linear programming and searching integer solutions. The results of the bit-length optimization based on non-linear programming are real values, and these values are converted to integer with round-up for hardware implementation. In this paper, we show a method to search integer solutions under the constrains of the real solution. The experimental results shows the advantage of searching based method.
  • 土井 伸洋, 堀山 貴史, 中西 正樹, 木村 晋二 情報処理学会研究報告システムLSI設計技術(SLDM) 2004 (56) 41 -46 2004年05月28日 
    Cプログラムからのハードウェア合成においてはビット長最適化をはじめとするさまざまなハードウェア向け最適化が必要である.このためにはプログラム中の変数がとりうる値やデータフローを推測することが必要で,静的解析手法が使われることが多いが,精度などの点で不十分な点がある.本稿ではソフトウエア検証の分野で注目されている抽象解釈(Abstract Interpretation)手法に基づくプログラムの解析と,データパス最適化への応用について述べる.Various optimization techniques such as bit-length optimization are required for hardware generation from C programs. The value range analysis and dataflow analysis are effective for such optimization and static pro gram analysis methods have been used. The static methods, however, have several problems such as the preciseness, the overestimation, etc. In this paper, we describe a program analysis method based on abstract interpretation and its application for datapath optimization.
  • 梶原 裕嗣, 中西 正樹, 堀山 貴史, 木村 晋二, 渡邉 勝正 情報処理学会研究報告システムLSI設計技術(SLDM) 2003 (7) 37 -42 2003年01月28日 
    論理関数の畳み込み機構を導入した新しい省面積FPGAの機構とその実現手法を提案し,LSI実現での面積および遅延の評価を示す.配線構造としては,広く用いられているislandスタイルに基づいている.複数のベンチマーク回路での評価により,通常の4-1LUTと比較して,最大で32.4%,平均でも12%の面積削減が可能であることがわかった.The paper describes an area efficient FPGA architecture based on LUTs with logic function folding. Each LUT is a 3-1 LUT but is enhanced to implement a full adder function with only one LUT. The area of our 3-1 LUT is about 56% compared to that of a simple 4-1 LUT. In the paper, we measure not only the LUT area but also the area of routing resource. We adopt the well-known island style-architecture for the routing mechanism, and find that the total FPGA area can be saved up to 32.4% and on average 12% by the experiments on several benchmark circuits compared to FPGA architecture based on 4-1 LUTs.
  • 堀山 貴史, 茨木 俊秀 数理解析研究所講究録 1093 93 -98 1999年04月

受賞

  • 2018年09月 電子情報通信学会基礎境界ソサイエティ, 貢献賞
  • 2016年05月 電子情報通信学会情報・システムソサイエティ, 情報・システムソサイエティ論文編集活動感謝状
  • 2016年05月 情報処理学会, 感謝状
  • 2011年02月 The 9th EATCS/LA Workshop on Theoretical Computer Science, EATCS/LA Best Presentation Award
  • 2001年03月 電子情報通信学会 学術奨励賞
  • 2000年05月 日経BP社 LSI IPデザイン・アワード IP賞
     
    受賞者: 中村一博;朱強;丸岡新治;堀山貴史;木村晋二;渡邉勝正

共同研究・競争的資金等の研究課題

  • -
  • -

教育活動情報

主要な担当授業

  • 大規模知識処理特論
    開講年度 : 2021年
    課程区分 : 修士課程
    開講学部 : 情報科学研究科
    キーワード : 知識処理, 数理モデル
  • 大規模知識処理特論
    開講年度 : 2021年
    課程区分 : 修士課程
    開講学部 : 情報科学院
    キーワード : 知識処理, 数理モデル
  • 大規模知識処理特論
    開講年度 : 2021年
    課程区分 : 博士後期課程
    開講学部 : 情報科学研究科
    キーワード : 知識処理, 数理モデル
  • 大規模知識処理特論
    開講年度 : 2021年
    課程区分 : 博士後期課程
    開講学部 : 情報科学院
    キーワード : 知識処理, 数理モデル
  • アルゴリズムとデータ構造
    開講年度 : 2021年
    課程区分 : 学士課程
    開講学部 : 工学部
    キーワード : 計算量,ソート,探索,グラフ,文字列照合
  • 情報理工学実験Ⅰ
    開講年度 : 2021年
    課程区分 : 学士課程
    開講学部 : 工学部
    キーワード : プログラミング、計算機システム、データ解析技法
  • 情報理工学実験Ⅱ
    開講年度 : 2021年
    課程区分 : 学士課程
    開講学部 : 工学部
    キーワード : データベース、Web、機械学習、並列プログラミング
  • 情報理工学演習Ⅲ
    開講年度 : 2021年
    課程区分 : 学士課程
    開講学部 : 工学部
    キーワード : データ構造,アルゴリズム,ソート,再帰,線形代数, 音声音響信号処理,画像信号処理,画像認識,コンピュータグラフィクス
  • コンピュータシステム
    開講年度 : 2021年
    課程区分 : 学士課程
    開講学部 : 工学部
    キーワード : ハードウェア構成、機械語命令、ノイマン型計算機、並列計算機、スーパーコンピュータ、ファームウェア、マイクロプロセッサ、パイプライン処理、キャッシュメモリ、プロセス、スレッド、スケジューリング、割り込み、デッドロック、メモリ管理、仮想メモリ、ページング、ファイルシステム
  • 情報理工学演習Ⅰ
    開講年度 : 2021年
    課程区分 : 学士課程
    開講学部 : 工学部
    キーワード : コンピュータシステム、ネットワークとクラウド、計算機アーキテクチャ、オペレーティングシステム、コンピュータネットワーク、Web技術、クラウド技術

大学運営

委員歴

  • 2019年06月 - 2021年05月   電子情報通信学会 会誌編集委員会   編集特別幹事
  • 2017年07月 - 2019年03月   埼玉県情報サービス産業協会   彩の国さいたまICT コンテスト 審査委員長.
  • 2013年08月 - 2019年03月   さいたま市 情報化計画評議会   評議委員長
  • 2016年05月 - 2018年04月   情報処理学会 アルゴリズム研究専門委員会   主査
  • 2016年04月 - 2018年03月   電子情報通信学会 基礎・境界ソサイエティ   運営委員
  • 2014年07月 - 2017年01月   埼玉県情報サービス産業協会   ホームページコンテスト 審査委員長
  • 2015年06月 - 2016年05月   情報処理学会 論文誌ジャーナル/JIP 編集委員会   基盤グループ 主査
  • 2013年06月 - 2015年05月   情報処理学会 論文誌ジャーナル/JIP 編集委員会   基盤グループ 副査
  • 2009年06月 - 2015年05月   電子情報通信学会 VLSI設計技術研究専門委員会   研究専門委員   電子情報通信学会
  • 2008年06月 - 2010年05月   電子情報通信学会   コンピュテーション研究専門委員会 幹事   電子情報通信学会
  • 2004年05月 - 2008年04月   情報処理学会アルゴリズム研究専門委員会   運営委員


Copyright © MEDIA FUSION Co.,Ltd. All rights reserved.