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研究者情報

マスター

アカウント（マスター）

  • 氏名

    葛西　誠也(カサイ　セイヤ), カサイ　セイヤ

所属（マスター）

  • 量子集積エレクトロニクス研究センター

所属（マスター）

  • 量子集積エレクトロニクス研究センター

独自項目

syllabus

  • 2021, 先端デバイス学特論, Advanced Functional Electronic Devices, 修士課程, 情報科学研究科, 半導体材料、電子物性、電界効果トランジスタ、バイポーラトランジスタ、センサ、デジタルとアナログ、信号変換、離散化、量子化
  • 2021, 応用デバイス回路学特論, Advanced Electronic Devices and Circuits, 修士課程, 情報科学院, 半導体材料、電子物性、電界効果トランジスタ、バイポーラトランジスタ、センサ、デジタルとアナログ、信号変換、離散化、量子化
  • 2021, 先端デバイス学特論, Advanced Functional Electronic Devices, 博士後期課程, 情報科学研究科, 半導体材料、電子物性、電界効果トランジスタ、バイポーラトランジスタ、センサ、デジタルとアナログ、信号変換、離散化、量子化
  • 2021, 応用デバイス回路学特論, Advanced Electronic Devices and Circuits, 博士後期課程, 情報科学院, 半導体材料、電子物性、電界効果トランジスタ、バイポーラトランジスタ、センサ、デジタルとアナログ、信号変換、離散化、量子化
  • 2021, 電気電子工学実験Ⅰ, Electrical and Electronic Engineering Laboratories I, 学士課程, 工学部, バイポーラトランジスタ，増幅回路，MOSFET，CMOS，演算増幅器，論理回路，順序回路，ディジタル回路
  • 2021, 電気電子工学実験Ⅱ, Electrical and Electronic Engineering Laboratories II, 学士課程, 工学部, 偏光，旋光，回折，屈折，結晶構造，X線回折，半導体物性，ホール効果，電気磁気エネルギー，電力
  • 2021, 電気電子工学実験Ⅲ, Electrical and Electronic Engineering Laboratories III, 学士課程, 工学部, 半導体プロセス，MOSFET，集積回路特性評価，SPICE，回路シミュレーション，アセンブリ言語
  • 2021, 電子デバイス工学, Electron Device Engineering, 学士課程, 工学部, 半導体、電子と正孔（ホール）、ダイオード、トランジスタ、集積回路、受光素子、発光素子、表示素子

researchmap

プロフィール情報

学位

  • 博士(工学)（北海道大学）

プロフィール情報

  • 姓

    葛西, カサイ

  • 名

    誠也, セイヤ

  • ID各種

    200901043318681880

対象リソース

業績リスト

研究キーワード

  • 半導体表面界面物性   ゆらぎ   確率共鳴   非線形素子   III-V族化合物半導体   量子ナノ集積回路   量子ナノデバイス   ultra-high speed device   stochastic resonance   III-V compound semiconductors   Semiconductor nanodevice   

研究分野

  • ものづくり技術（機械・電気電子・化学工学） / 電子デバイス、電子機器
  • ナノテク・材料 / 薄膜、表面界面物性
  • ナノテク・材料 / ナノマイクロシステム
  • ナノテク・材料 / ナノ材料科学

経歴

  • 2014年07月 - 現在 北海道大学 量子集積エレクトロニクス研究センター 教授
  • 2004年 - 2014年06月 北海道大学大学院情報科学研究科および量子集積エレクトロニクス研究センター 助教授（2007年〜准教授）
  • 2007年10月 - 2011年03月 JST さきがけ「革新的次世代デバイスを目指す材料とプロセス」 研究者（兼任）
  • 2009年04月 - 2010年03月 マレーシア工科大学 客員教授
  • 2001年 - 2004年 北海道大学大学院工学研究科および量子集積エレクトロニクス研究センター 助教授
  • 2004年 - Associate Professor, Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics
  • 2002年 - 2003年 Associate Professor, Graduate School of Engineering, and University and Research Center for Integrated Quantum Electronics, Hokkaido University
  • 1999年 - 2001年 北海道大学大学院工学研究科 助手
  • 1999年 - 2001年 Research Assistant, Graduate School of Engineering, Hokkaido University,
  • 1997年 - 1999年 日本電気株式会社 光・超高周波デバイス 研究所
  • 1997年 - 1999年 NEC

学歴

  • 1994年04月 - 1997年03月   北海道大学   大学院工学研究科   電気工学専攻博士課程
  •         - 1997年   北海道大学
  • 1992年04月 - 1994年03月   北海道大学   大学院工学研究科   電気工学専攻修士課程
  • 1988年04月 - 1992年03月   北海道大学   工学部   電気工学科
  •         - 1991年   北海道大学

委員歴

  • 2016年01月 - 現在   国際マイクロプロセスナノテクノロジ会議   組織委員会委員
  • 2023年01月 - 2023年12月   第３６回国際マイクロプロセスナノテクノロジ国際会議   組織委員長
  • 2021年06月 - 2023年05月   電子情報通信学会 電子デバイス研究専門委員会   副委員長
  • 2021年05月 - 2023年04月   電子情報通信学会 電子デバイス研究会   副委員長
  • 2022年01月 - 2022年12月   第３５回国際マイクロプロセスナノテクノロジ会議（MNC）   組織副委員長
  • 2021年04月   日本学術振興会 R031ハイブリッド量子ナノ技術委員会   物理・デバイス分野 副査
  • 2018年01月 - 2018年12月   国際マイクロプロセスナノテクノロジ会議   組織委員長
  • 2016年02月 - 2018年01月   応用物理学会   代議員
  • 2016年01月 - 2017年12月   国際マイクロプロセスナノテクノロジ会議   組織副委員長
  • 2013年05月 - 2015年04月   電子情報通信学会   電子デバイス研究会幹事
  • 2015年 - 2015年   国際固体素子・材料コンファレンス   実行委員会総務
  • 2014年 - 2014年   国際固体素子・材料コンファレンス   実行委員
  • 2011年05月 - 2013年04月   電子情報通信学会   電子デバイス研究会幹事補佐
  • 2009年05月 - 2012年04月   電子情報通信学会   和文誌C編集委員
  • 2009年06月 - 2011年05月   応用物理学会   講演会企画運営委員、大分科9応用物性世話人、9.3ナノエレクトロニクス世話人   応用物理学会
  • 2001年05月 - 2011年04月   電子情報通信学会   電子デバイス研究会専門委員   電子情報通信学会
  • 2007年06月 - 2009年05月   応用物理学会   9.3ナノエレクトロニクス世話人
  • 2009年 - 2009年   文部科学省   特定領域研究専門委員会委員
  • 2007年 - 2007年   文部科学省   特定領域研究専門委員会委員
  • 国際学会（ISCS, AWAD, TWHM, etc）   実行委員、プログラム委員など

受賞

  • 2020年 応用物理学会 応用物理学会優秀論文賞
     Divergence of relative difference in Gaussian distribution function and stochastic resonance in a bistable system with frictionless state transition 
    受賞者: 葛西誠也;一木輝久;田所幸浩
  • 2017年 電気通信普及財団 テレコムシステム技術賞
     Design framework of image sensor system based on dynamic range extension by adding noise for saturated conditions 
    受賞者: 田所 幸浩;葛西 誠也;一木 輝久;田中 宏哉
  • 2016年03月 電子情報通信学会 電子情報通信学会エレクトロニクスソサイエティ活動功労表彰
     
    受賞者: 葛西 誠也
  • 2015年03月 情報処理学会高度交通システムとスマートコミュニティ研究会 平成26年情報処理学会高度交通システム研究会優秀論文賞
     確率共鳴現象の応用によるハレーション環境での歩行者認識性能の改善 
    受賞者: 田所幸浩;葛西誠也;一木輝久;田中宏哉
  • 2014年11月 MNC2014 MNC2013 Award for Outstanding Paper
     "Detection of weak biological signal utilizing stochastic resonance in a GaAs-based nanowire FET and its parallel summing network 
    受賞者: Y. Imai;M. Sato;T. Tanaka;S. Kasai;Y. Hagiwara;H. Ishizaki;S. Kuwabara;T. Arakawa
  • 2011年10月 MNC2011 MNC2010 Outstanding Paper Award
     Novel Nanowire-Based Flip-Flop Circuit Utilizing Gate-Controlled GaAs Three-Branch Nanowire Junctions 
    受賞者: H. Shibata;Y. Shiratori;S. Kasai
  • 2008年 MNC2007 Outstanding Paper Award
  • 2008年 MNC2008 Outstanding paper award
  • 2007年 NGC2007 Poster Prize
  • 2000年 第9回応用物理学会「講演奨励賞」
  • 1996年 SSDM Young Researcher Award

論文

  • Seiya Kasai
    NANOTECHNOLOGY 33 50 505203.1 - 505203.8 2022年12月 [査読有り]
     
    Stochastic resonance (SR) in a single-electron system is expected to allow information to be correctly carried and processed by single electrons in the presence of thermal fluctuations. Here, we comprehensively study thermally driven single-electron SR. The response of the system to a weak voltage signal is formulated by considering the single-electron tunneling rate, instead of the Kramers' rate generally used in conventional SR models. The model indicates that the response of the system is maximized at finite temperature and that the peak position is determined by the charging energy. This model quantitatively reproduces the results of a single-electron device simulator. Single-electron SR is also demonstrated using a GaAs-based single-electron system that integrates a quantum dot and a high-sensitivity charge detector. The developed model will contribute to our understanding of single-electron SR and will facilitate accurate prediction, design, and control of single-electron systems.
  • Seiya Kasai
    SEMICONDUCTOR SCIENCE AND TECHNOLOGY 37 10 2022年10月 [査読有り]
     
    Reservoir computing (RC) is a unique machine learning framework based on a recurrent neural network, which is currently involved in numerous research fields. RC systems are distinguished from other machine learning systems since detailed network designs and weight adjustments are not necessary. This enables the availability of many device and material options to physically implement the system, referred to as physical RC. This review outlines the basics of RC and related issues from an implementation perspective that applies semiconductor electron device technology. A possible interpretation of RC computations is shown using a simple model, and the reservoir network is understood from the viewpoint of network theory. Physical implementation and operation issues are discussed by referring to our experimental investigation of dynamic nodes using a semiconductor tunnel diode with cubic nonlinearity.
  • Shintaro Mizuno, Renpeng Lu, Katsumi Shimizu, Yosuke Ueba, Mikio Ishikawa, Mitsuru Kitamura, Morihisa Hoga, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 60 SC 2021年06月 [査読有り][通常論文]
     
    To demonstrate electric discrimination of the nano-pattern for nano-artifact metrics, we fabricated and characterized a nano-convex-embedded Si MOSFET. The concept of electrical discrimination is to embed the nanostructure between the gate oxide and the Si channel of the MOSFET, and reflect the structure in the drain current. Spatial resolution in the channel direction is achieved by the drain voltage dependence of the channel pinch off position. The fabricated device with a nano-convex showed the increase of the on-resistance in the linear region and the increase of the drain conductance in the saturation region. These behaviors could be reproduced by the device simulation. The transfer characteristics in the subthreshold region showed the shift of the drain current curve to the positive voltage side by embedding a nano-convex. The overall behaviors were explained by the formation of a potential barrier in the channel under the nano-convex and its drain voltage dependence.
  • Kenta Saito, Naoki Suefuji, Seiya Kasai
    BIOINSPIRATION & BIOMIMETICS 16 3 2021年05月 [査読有り][通常論文]
     
    We investigate the effect of asymmetric deformation dynamics in an amoeboid organism on its search ability using a model amoeba. The model represents the behaviours of the amoeboid organism and its search ability is evaluated by searching for the solution to a Boolean satisfiability problem (SAT). We found that the efficiency of the search is significantly improved by implementing asymmetric delays in response to the feedback signals that increase and decrease the variable under appropriate errors. The results indicate that the model could search around the variable vector space by means of the appropriate combination of the inherent local search in the model and the error-induced global search. The results also show that the asymmetric response delays bias the variable to the values that can satisfy the SAT. We also demonstrate that an analog electronic system implementing the amoeba model with asymmetric dynamics possesses the search characteristics of the model.
  • Kenta Saito, Masashi Aono, Seiya Kasai
    SCIENTIFIC REPORTS 10 1 2020年12月 [査読有り][通常論文]
     
    Combinatorial optimization to search for the best solution across a vast number of legal candidates requires the development of a domain-specific computing architecture that can exploit the computational power of physical processes, as conventional general-purpose computers are not powerful enough. Recently, Ising machines that execute quantum annealing or related mechanisms for rapid search have attracted attention. These machines, however, are hard to map application problems into their architecture, and often converge even at an illegal candidate. Here, we demonstrate an analogue electronic computing system for solving the travelling salesman problem, which mimics efficient foraging behaviour of an amoeboid organism by the spontaneous dynamics of an electric current in its core and enables a high problem-mapping flexibility and resilience using a resistance crossbar circuit. The system has high application potential, as it can determine a high-quality legal solution in a time that grows proportionally to the problem size without suffering from the weaknesses of Ising machines.
  • Kenta Saito, Seiya Kasai
    APPLIED PHYSICS EXPRESS 13 11 2020年11月 [査読有り][通常論文]
     
    We investigate how feedback delays affect the quality of solutions from an amoeba-inspired analog electronic computing system that solves the "traveling salesman problem". Delays in the feedback process induce the oscillation of state variables. With an appropriate delay length, the system converges to the stable state that corresponds to the solution after oscillation. We find that the solution quality is improved by increasing the delay length. Consequently, delays bring a trade-off between the solution search time and the solution quality. Delay scheduling can further improve solution quality.
  • Kentaro Sasaki, Shunsuke Saito, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 59 10 2020年10月 [査読有り][通常論文]
     
    We demonstrate a current timer switch function in a GaAs-based nanowire electrostatically coupled with a polyoxometalate nanoparticle (POM NP) and a conductive atomic force microscopy (AFM) tip. The nanowire current associated with the charge state of the POM NP on the nanowire surface abruptly changed after several ten seconds from biasing the conductive tip. The current switch timing changed depending on the tip voltage. The timer switch function appeared when the tip approached the POM NP where the AFM phase image showed phase lag at high atmospheric humidity condition. We discuss the timer mechanism in terms of the configuration of the electromechanical potential of the cantilever and dynamic potential modulation by mobile ions and polarized molecules in the water-absorbed POM NP surface.
  • Junichi Motohisa, Jun Ohta, Kenichi Kawaguchi, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 59 6 2020年06月 [査読無し][通常論文]
  • Xingwei Zeng, Dongwei Zhang, Yanan Zhu, Mo Chen, Haibiao Chen, Seiya Kasai, Hong Meng, Osamu Goto
    JOURNAL OF MATERIALS CHEMISTRY C 7 45 14275 - 14283 2019年12月 [査読有り][通常論文]
     
    We report a new insight into the molecular design strategy for developing anthracene derivatives with in-plane isotropic mobility. Among three types of anthracene derivatives: 2-,9,10-, and 2,6-positions substituted anthracenes (2-ANTs, 9,10-ANTs, and 2,6-ANTs), we discovered that 2,6-ANTs offer the highest degree of in-plane isotropy in mobility. By analyzing the structure and properties of 2,6-ANTs, we identified conditions to achieve in-plane isotropic mobility: first, the molecular arrangement of the layered herringbone (LHB) structure needs to be symmetrical with respect to both the pi-pi stacking direction and the transverse direction. Second, the angle between the pi-pi stacking direction and the transverse direction, theta(T), needs to be around 50 degrees. Third, the ratio between the transfer integrals along the pi-pi stacking and transverse directions, R = V-P/V-T, needs to be smaller than 0.7. Therefore, both structural features and electronic property parameters determine the degree of isotropy. An investigation on the torsion angles between the side chain and the anthracene backbone found that a desirable R value could be obtained by improving the planarity in 2,6-ANTs to enhance the intermolecular interactions on the transverse contacts. To confirm the theory, 2,6-bis(dibenzo[b,d]furan-3-yl)anthracene (BDBFAnt) with fused aromatic rings as substituents was used to form a single-crystal organic field effect transistor (SC-OFET) and it demonstrated an isotropic mobility with values within a range of 2.6-3.4 cm(2) V-1 s(-1) in all measured directions.
  • 佐々木 健太郎, 岡本 翔真, 田代 省平, 浅井 哲也, 葛西 誠也
    Japanese Journal of Applied Physics 58 SD SDDE13(1) - SDDE13(6) 2019年05月23日 [査読有り][通常論文]
     
    To investigate the molecular charge dynamics of polyoxometalate (POM) molecules, we formed and characterized a charge coupled structure with POM molecular particles and a GaAs-based nanowire. In our system, the charge sensitivity was locally increased by capacitive coupling between a metal tip and the POM particle. Surface dispersion of POM particles on the GaAs nanowire was carried out in a controlled manner by choosing an appropriate solvent and POM concentration. We found that, after POM surface dispersion, the current in the GaAs nanowire remarkably increased by charging the POM particles using a conductive atomic force microscopy tip. The current change strongly depended on humidity of the measurement environment. The nanowire current under capacitive coupling between the conductive tip and the POM particle on the nanowire surface showed steps with a height of approximately 70 nA, suggesting that multiple hole charging and discharging occurred in the particle in a synchronized manner. (c) 2019 The Japan Society of Applied Physics
  • Amoeba-inspired electronic computing system and its application to autonomous walking of a multi-legged robot
    Kenta Saito, Naoki Suefuji, Seiya Kasai, Masashi Aono
    Journal of Applied Logics 5 9 1799 - 1814 2018年12月01日 
    An amoeba-inspired electronic computing system that searches a solution of a combinational optimization problem was developed. The computing system, called electronic amoeba, electronically represents the spatiotemporal dynamics of a single-celled amoeboid organism that is trying to maximize its food intake while minimizing the risks. We implemented the system using a conventional electronic circuit and successfully demonstrated its solution search capability for a Boolean satisfiability problem, SAT. The electronic amoeba was applied to autonomous walking of a four-legged robot without programming any leg maneuvers. The robot could walk to the target direction by successively searching a combination of the multi-valued leg joint states depending on the previous states and sensor information. We also confirmed that our approach arose the ability to travel over obstacles without prior information.
  • Saito Kenta, Suefuji Naoki, Kasai Seiya, Aono Masashi
    JOURNAL OF APPLIED LOGICS-IFCOLOG JOURNAL OF LOGICS AND THEIR APPLICATIONS 5 9 1799 - 1814 2018年12月 [査読有り][通常論文]
  • Mo Chen, Yanan Zhu, Chao Yao, Dongwei Zhang, Xingwei Zeng, Imran Murtaza, Haibiao Chen, Seiya Kasai, Hong Meng, Osamu Goto
    Organic Electronics: physics, materials, applications 54 237 - 244 2018年03月01日 [査読有り][通常論文]
     
    This study investigates the gate stress-induced mobility discrepancy in p-type single-crystal organic field-effect transistors (OFETs) on an octyltrichlorosilane (OTS)-modified SiO2/Si substrate. During measurements in atmosphere, anti-clockwise hysteresis was observed in the transfer curve, and the mobility calculated from the forward sweep was smaller than that calculated from the reverse sweep. Hysteresis has often been observed for OFETs but the mobility discrepancy has not been clearly understood. We formulated a “fast trapping vs. slow detrapping” model and suggested that the mobility values calculated from the reverse sweep represent the intrinsic property of the material. To verify the validity of this model, we investigated mobility anisotropy of an air-stable organic semiconductor, 2,7-bis(4-methoxyphenyl)benzo[b]benzo[4,5]thieno[2,3-d]thiophene (DBOP-BTBT). By measuring the single-crystal OFET characteristics of many crystals with different orientations, we observed anisotropic hole mobility calculated from the reverse sweep. The mobility along the b-axis, which corresponds to the π-π stacking direction, was 13.9 cm2 V−1 s−1, and that along the a-axis was 6.2 cm2 V−1 s−1. However, we did not see clear anisotropy when mobility was calculated from the forward sweep due to a variation in the data. The threshold voltage from the reverse and the forward sweeps showed isotropic characteristics within the range from −60 to −70 V and from −50 to −60 V, respectively. These results indicate that the numbers of filled traps were different between the reverse and the forward sweeps at the interface, and confirm the validity of our model.
  • Divergence of relative difference in Gaussian distribution function and stochastic resonance in a bistable system with frictionless state transition
    S. Kasai, A. Ichiki, Y. Tadokoro
    Applied Physics Express 11 037301.1 - 037301.4 2018年02月 [査読有り][通常論文]
  • Analytical derivation of charge relaxation time distribution in transistor from current noise spectrum using inverse integral transformation method
    Z. Yatabe, S. Inoue, J. T. Asubar, S. Kasai
    Applied Physics Express 11 031201.1 - 031201.4 2018年02月 [査読有り][通常論文]
  • Kenta Saito, Naoki Suefuji, Seiya Kasai, Masashi Aono
    127 - 131 2018年
  • Yamada, T.K., Fukuda, H., Fujiwara, T., Liu, P., Nakamura, K., Kasai, S., Vazquez De Parga, A.L., Tanaka, H.
    Nanotechnology 29 31 315705  2018年 [査読有り][通常論文]
  • Agung Setiadi, Hayato Fujii, Seiya Kasai, Ken-ichi Yamashita, Takuji Ogawa, Takashi Ikuta, Yasushi Kanai, Kazuhiko Matsumoto, Yuji Kuwahara, Megumi Akai-Kasaya
    NANOSCALE 9 30 10674 - 10683 2017年08月 [査読有り][通常論文]
     
    Detection and use of physical noise fluctuations in a signal provides significant advantages in the development of bio- and neuro-sensing and functional mimicking devices. Low-dimensional carbon nanomaterials are a good candidate for use in noise generation due to the high surface sensitivity of these materials, which may themselves serve as the main building blocks of these devices. Here, we demonstrate that the addition of a molecule with high redox activity to a carbon nanotube (CNT) field-effect transistor provides tunable current fluctuation noise. A unique charge-trap state in the vicinity of the CNT surface due to the presence of the single molecule is the origin of the noise, which generates a prominent and unique slow discrete random telegraph signal in the device current. The power spectral density reveals the peculiar frequency limit of the fluctuation for different types of molecules depending on their redox activity and adsorption configuration. These results indicate that the detected noise will provide new opportunities to obtain electronic information for a single molecule combined with a nanotube surface, and that controllability of the noise may contribute to the expansion of noise utilization in future bio-inspired devices.
  • Shoma Okamoto, Masaki Sato, Kentaro Sasaki, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 56 6 2017年06月 [査読有り][通常論文]
     
    We investigate a detection technique of charge dynamics of a molecular particle using a GaAs-based nanowire where the charge sensitivity is locally enhanced by particle-metal tip capacitive coupling. By equivalent circuit analysis, it was clarified that the nanowire channel potential becomes sensitive to the molecular particle on the nanowire when the particle is capacitively coupled with a metal tip. The concept was demonstrated using a GaAs-based nanowire with tetraphenylporphyrin (TPP) particles on its surface and a measurement system integrating an atomic force microscope (AFM) and a dynamic current measurement monitor/spectrum analyzer. When the metal tip was in contact with a TPP particle on the nanowire under an appropriate tip bias condition, random telegraph signal (RTS) noise was imposed on the nanowire current, suggesting the increase in sensitivity to the charge state of the particle by the metal tip contact. We discussed the origin of the RTS noise through analysis of the time constant of RTS noise, RTS amplitude, and noise spectrum. (C) 2017 The Japan Society of Applied Physics.
  • Ryota Kuroda, Seiya Kasai
    International Journal of Parallel, Emergent and Distributed Systems 32 3 287 - 294 2017年05月04日 [査読有り][通常論文]
     
    Toward reconfigurable and noise-coexistence information processing system utilizing nanostructures, we study a threshold logic circuit and a double threshold function using a GaAs-based nanowire field-effect transistor (FET) network. A noise coexistence capability is based on a noise-assisted state transition in a threshold function in a threshold logic element. We fabricate a circuit reconfigurable between NAND and NOR functions. A hysteresis transfer characteristic with double threshold is realized in the GaAs nanowire by using a silicon nitride (SiN) as the gate insulator. We introduce a unique inverter design using the SiN-gate FET as a load to achieve the transfer characteristic with clockwise hysteresis, similar to a Schmitt trigger.
  • Yukihiro Tadokoro, Seiya Kasai, Akihisa Ichiki, Hiroya Tanaka
    IEEE Transactions on Systems, Man, and Cybernetics: Systems 46 8 1121 - 1128 2016年08月01日 [査読有り][通常論文]
     
    It is a well-known fact that the light input to an image sensor is often out of its dynamic range under the strong light conditions of halation. In this case, the sensor cannot output any information. Therefore, various countermeasures have been proposed for sensor devices and signal processing. These countermeasures increase the dynamic range using additional components and/or computations, which increase the system cost. In this paper, we propose a simple alternative method of just adding noise. Inspired by the concept of supra-threshold stochastic resonance, which is often discussed in the context of nonlinear physics, a fluctuation in sensor response is introduced in the proposed method. We analytically describe the mechanism by which the dynamic range is increased, which is intuitively understandable and can be used in practical image sensors.
  • Yukihiro Tadokoro, Seiya Kasai, Akihisa Ichiki, Hiroya Tanaka
    IEEE TRANSACTIONS ON SYSTEMS MAN CYBERNETICS-SYSTEMS 46 8 1121 - 1128 2016年08月 [査読有り][通常論文]
     
    It is a well-known fact that the light input to an image sensor is often out of its dynamic range under the strong light conditions of halation. In this case, the sensor cannot output any information. Therefore, various countermeasures have been proposed for sensor devices and signal processing. These countermeasures increase the dynamic range using additional components and/or computations, which increase the system cost. In this paper, we propose a simple alternative method of just adding noise. Inspired by the concept of supra-threshold stochastic resonance, which is often discussed in the context of nonlinear physics, a fluctuation in sensor response is introduced in the proposed method. We analytically describe the mechanism by which the dynamic range is increased, which is intuitively understandable and can be used in practical image sensors.
  • Kento Shirata, Yuki Inden, Seiya Kasai, Takahide Oya, Yosuke Hagiwara, Shunichi Kaeriyama, Hideyuki Nakamura
    JAPANESE JOURNAL OF APPLIED PHYSICS 55 4 2016年04月 [査読有り][通常論文]
     
    We investigated the robust detection of surface electromyogram (EMG) signals based on the stochastic resonance (SR) phenomenon, in which the response to weak signals is optimized by adding noise, combined with multiple surface electrodes. Flexible carbon nanotube composite paper (CNT-cp) was applied to the surface electrode, which showed good performance that is comparable to that of conventional Ag/AgCl electrodes. The SR-based EMG signal system integrating an 8-Schmitt-trigger network and the multiple-CNT-cp-electrode array successfully detected weak EMG signals even when the subject's body is in the motion, which was difficult to achieve using the conventional technique. The feasibility of the SR-based EMG detection technique was confirmed by demonstrating its applicability to robot hand control. (C) 2016 The Japan Society of Applied Physics
  • Masaki Sato, Xiang Yin, Ryota Kuroda, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 55 2 2016年02月 [査読有り][通常論文]
     
    We investigated the detection of discrete charge dynamics of an electron trap in a GaAs-based nanowire surface through current fluctuation induced by a metallic scanning probe tip. An equivalent circuit model indicated that the charge state in the surface strongly reflects the channel potential when the local surface potential is fixed by the metal tip, which suggests that random charging and discharging dynamics of the trap appears as random telegraph signal (RTS) noise in the nanowire current. Experimental demonstration of the concept was carried out using a GaAs-based nanowire and an atomic force microscope (AFM) system with a conductive tip. We observed the RTS noise in the drain current and superposition of the Lorentzian component in the noise spectrum when the metal tip was in contact with the nanowire surface at specific positions. The obtained results indicate the possibility of detecting charge dynamics of the individual surface trap in semiconductor devices. (C) 2016 The Japan Society of Applied Physics
  • Kentaro Sasaki, Ryota Kuroda, Xiang Yin, Masaki Sato, Takuji Ogawa, Seiya Kasai
    2016 COMPOUND SEMICONDUCTOR WEEK (CSW) INCLUDES 28TH INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE & RELATED MATERIALS (IPRM) & 43RD INTERNATIONAL SYMPOSIUM ON COMPOUND SEMICONDUCTORS (ISCS) 2016年 [査読有り][通常論文]
     
    We investigate a multiple-gate GaAs-based nanowire field-effect transistor (FET) for detecting spatially distributed molecular charges. Spatial resolution is implemented to the nanowire by arranging narrow metal gate array. In this device the molecule charge position and the metal gate position are correlated through capacitive coupling between the molecule and a metal gate. Then a molecule charge in the gate periphery with appropriate gate biasing selectively reflects in the nanowire current. To demonstrate our concept, we fabricate a GaAs-based nanowire FET having a 50-nm-length Schottky gate array with 50-nm interval and investigate to arrange the charged molecules at arbitrary position using Tetraphenylporphyrin (TPP).
  • Hirofumi Tanaka, Ryo Arima, Minoru Fukumori, Daisuke Tanaka, Ryota Negishi, Yoshihiro Kobayashi, Seiya Kasai, Toyo Kazu Yamada, Takuji Ogawa
    SCIENTIFIC REPORTS 5 2015年10月 [査読有り][通常論文]
  • Hirofumi Tanaka, Ryo Arima, Minoru Fukumori, Daisuke Tanaka, Ryota Negishi, Yoshihiro Kobayashi, Seiya Kasai, Toyo Kazu Yamada, Takuji Ogawa
    SCIENTIFIC REPORTS 5 2015年07月 [査読有り][通常論文]
     
    A simple method for fabricating single-layer graphene nanoribbons (sGNRs) from double-walled carbon nanotubes (DWNTs) was developed. A sonication treatment was employed to unzip the DWNTs by inducing defects in them through annealing at 500 degrees C. The unzipped DWNTs yielded double-layered GNRs (dGNRs). Further sonication allowed each dGNR to be unpeeled into two sGNRs. Purification performed using a high-speed centrifuge ensured that more than 99% of the formed GNRs were sGNRs. The changes induced in the electrical properties of the obtained sGNR by the absorption of nanoparticles of planar molecule, naphthalenediimide (NDI), were investigated. The shape of the I-V curve of the sGNRs varied with the number of NDI nanoparticles adsorbed. This was suggestive of the existence of a band gap at the narrow-necked part near the NDI-adsorbing area of the sGNRs.
  • M. Aono, S. Kasai, S-J Kim, M. Wakabayashi, H. Miwa, M. Naruse
    NANOTECHNOLOGY 26 23 234001  2015年06月 [査読有り][通常論文]
     
    In this study, we extracted the essential spatiotemporal dynamics that allow an amoeboid organism to solve a computationally demanding problem and adapt to its environment, thereby proposing a nature-inspired nanoarchitectonic computing system, which we implemented using a network of nanowire devices called 'electrical Brownian ratchets (EBRs)'. By utilizing the fluctuations generated from thermal energy in nanowire devices, we used our system to solve the satisfiability problem, which is a highly complex combinatorial problem related to a wide variety of practical applications. We evaluated the dependency of the solution search speed on its exploration parameter, which characterizes the fluctuation intensity of EBRs, using a simulation model of our system called 'moebaSAT-Brownian'. We found that AmoebaSAT-Brownian enhanced the solution searching speed dramatically when we imposed some constraints on the fluctuations in its time series and it outperformed a well-known stochastic local search method. These results suggest a new computing paradigm, which may allow high-speed problem solving to be implemented by interacting nanoscale devices with low power consumption.
  • Yushi Abe, Ryota Kuroda, Xiang Ying, Masaki Sato, Takayuki Tanaka, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 54 6 2015年06月 [査読有り][通常論文]
     
    We investigated the structural parameter dependence of the directed current in GaAs-nanowire-based Brownian ratchet devices. The directed current was generated by flashing a ratchet potential array repeatedly using multiple asymmetric gates with a periodic signal. The amount of current in the fabricated device increased as the nanowire width W decreased, which contradicted the theoretical model. The current also depended on the number of the gates N, when N was smaller than 6. We discussed the obtained results in terms of the structural parameter dependence of carrier transfer efficiency and the effect of electron reservoirs on current generation in flashing ratchet operation. (C) 2015 The Japan Society of Applied Physics
  • Xiang Yin, Masaki Sato, Seiya Kasai
    IEICE TRANSACTIONS ON ELECTRONICS E98C 5 434 - 438 2015年05月 [査読有り][通常論文]
     
    We investigate the origin of non-ideal transfer characteristics in graphene-based three-branch nano-junction (TBJ) devices. Fabricated graphene TBJs often show asymmetric nonlinear voltage transfer characteristic, although symmetric one should appear ideally. A simple model considering the contact resistances in two input electrodes is deduced and it suggests that the non-ideal characteristic arises from inequality of the metal-graphene contact resistances in the inputs. We fabricate a graphene TBJ device with electrically equal contacts by optimizing the contact formation process and almost ideal nonlinear characteristic was successfully demonstrated.
  • Shinya Inoue, Ryota Kuroda, Xiang Yin, Masaki Sato, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 54 4 2015年04月 [査読有り][通常論文]
     
    The detection of static and dynamic molecular charge states using a GaAs-based nanowire field-effect transistor (FET) was investigated. Tetraphenylporphyrin (TPP) was put on the device as target molecules. After coating TPP on the FET, the drain current clearly decreased. On the other hand, the current largely increased by 405-nm light irradiation, indicating that TPP worked as a photo-excited donor. The light irradiation on the FET also induced a Lorentzian noise component, which was superimposed onto conventional 1/f noise. These behaviors were not seen in the gateless nanowire even with TPP. The obtained results indicated that electrical interaction between TPP and the nanowire was enhanced when a metal gate existed, although the channel was protected from TPP by the gate metal. We discuss the observed behaviors on the basis of a model where only TPP in the gate periphery modulated the channel potential and the drain current. (C) 2015 The Japan Society of Applied Physics
  • Zenji Yatabe, Toru Muramatsu, Joel T. Asubar, Seiya Kasai
    PHYSICS LETTERS A 379 7 738 - 742 2015年03月 [査読有り][通常論文]
     
    A novel method is presented for obtaining the distribution function of relaxation times G(tau) from power spectrum 1/f(alpha) (1 <= alpha <= 2). It is derived using McWhorter model and its inverse Stieltjes transform. Unlike the pre-assumed conventional g(tau) distribution, the extracted G(tau) has a peak whose width increases as the slope of the power spectrum alpha decreases. The peak position determines the dominant time constant of the system. Our method is unique because the distribution function is directly extracted from the measured power spectrum. We then demonstrate the validity of this method in the analysis of noise in transistor. (C) 2014 Elsevier B.V. All rights reserved.
  • Yukihiro Tadokoro, Seiya Kasai, Akihisa Ichiki
    DIGITAL SIGNAL PROCESSING 37 1 - 12 2015年02月 [査読有り][通常論文]
     
    Stochastic resonance offers the possibility of signal amplification by the addition of noise. This curious, interesting phenomenon has received considerable attention since the 1990s. Since such effect has the potential to improve the signal processing performance, intensive works have been done about this topic. One of the most effective implementations of stochastic resonance is in the Collins network, which can provide outstanding performance in that the network output consists of an amplified version of a weak, sub-threshold signal. In practical situations, the sub-threshold signal is easily buried in external noise from the environment. The present paper focuses on the discrete-time system (plus continuous-time system) and analyzes this situation to clarify the performance degradation of the amplification effect. As a countermeasure, we herein propose a novel delay network. The present analysis indicates that the proposed scheme produces an amplification effect in the presence of external noise. The results of the analysis are used to determine the condition for which the delay network is effective, and the results of an experimental evaluation verifies the validity of the analysis. (C) 2014 Elsevier Inc. All rights reserved.
  • Yuri Imai, Masaki Sato, Takayuki Tanaka, Seiya Kasai, Yosuke Hagiwara, Haruya Ishizaki, Sumio Kuwabara, Takahiko Arakawa
    JAPANESE JOURNAL OF APPLIED PHYSICS 53 6 2014年06月 [査読有り][通常論文]
     
    We investigated biological signal detection utilizing stochastic resonance (SR) in a GaAs-based nanowire field-effect transistor (FET) and its parallel summing network. The SR phenomenon, in which the response to a weak signal is optimized by noise, was caused in the nanowire FET having a nonlinear transfer characteristic. We confirmed that the SR occurred on weak aperiodic electromyogram (EMG) signals induced on the surface of the forearm of a human subject. The EMG contaminated with intrinsic noise from the body was successfully detected in a parallel summing network of nanowire FETs. The output signal-to-noise ratio (SNR) of the nanowire FET network was higher than those of the conventional detection techniques. We also showed that the FET network with multiple threshold voltages achieved a high SNR in a wide range of EMG intensities. (C) 2014 The Japan Society of Applied Physics
  • 巳波 弘佳, 青野 真士, 成瀬 誠, 葛西 誠也
    電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 113 488 77 - 82 一般社団法人電子情報通信学会 2014年03月10日 [査読無し][通常論文]
     
    これまで,計算困難問題に対する様々なメタヒューリスティックアルゴリズムが研究されてきた.その一つとして,粘菌アメーバの示す時空間振動ダイナミクスに着想を得た解探索アルゴリズムがある.このアルゴリズムは,高速な解探索能力を示し,さらに低消費エネルギーで超小型のナノデバイスにより実装することも比較的容易である.本稿では,計算困難問題の一つである充足可能性判定問題(SAT)を解く粘菌アメーバ型解探索アルゴリズムについて,粘菌アメーバ型解探索が安定状態に入ったことを判定するための条件を明らかにした.さらに,安定状態であることと,そのときSATの解が得られていることが等価であることを示した.これにより,安定条件を満たすことがわかれば直ちにSATの解を得ることができるため,粘菌アメーバ型解探索アルゴリズムを実装したデバイスによる厳密で高速な解到達判定が可能となった.
  • Y. Tadokoro, S. Kasai, A. Ichiki
    IEICE Proceeding Series 46 80 - 83 2014年 [査読有り][通常論文]
  • Masaki Sato, Xiang Yin, Seiya Kasai
    2014 IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2014年 [査読有り][通常論文]
     
    Surface dependence of the nonlinear voltage transfer characteristic in the GaAs-based three-branch nanowire junction (TBJ) is investigated both theoretically and experimentally. A simple model considering the surface-potential-dependent carrier density in the channel reveals a clear relationship between the surface potential and the curvature of the bell-shaped transfer curve. Based on this model, we analyze the behavior of the TBJ with a local conductance modulation by focused light irradiation.
  • Seiya Kasai
    2014 IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2014年 [査読有り][通常論文]
     
    Stochastic resonance (SR), in which response of a system is optimized or enhanced by adding noise, is electronically caused using nonlinear electron devices, such as comparator, semiconductor nanowire FET, and their networks. The unique behavior of the phenomenon is analyzed and understood in terms of signal processing techniques. The positive role of the variation in the nanodevice network in terms of SR is also mentioned.
  • Seiya Kasai, Yukihiro Tadokoro, Akihisa Ichiki
    PHYSICAL REVIEW E 88 6 2013年12月 [査読有り][通常論文]
     
    We design nonlinear functions for the transmission of a small signal with non-Gaussian noise and perform experiments to characterize their responses. Using statistical design theory [A. Ichiki and Y. Tadokoro, Phys. Rev. E 88, 012124 (2013)], a static nonlinear function is estimated from the probability density function of the given noise in order to maximize the signal-to-noise ratio of the output. Using an electronic system that implements the optimized nonlinear function, we confirm the recovery of a small signal from a signal with non-Gaussian noise. In our experiment, the non-Gaussian noise is a mixture of Gaussian noises. A similar technique is also applied to the optimization of the threshold value of the function. We find that, for non-Gaussian noise, the response of the optimized nonlinear systems is better than that of the linear system.
  • Xiang Yin, Seiya Kasai
    Physica Status Solidi (C) Current Topics in Solid State Physics 10 11 1485 - 1488 2013年11月 [査読有り][通常論文]
     
    A logic inverter utilizing a graphene-based three-branch nano-junction (TBJ) is proposed and demonstrated. Fabricated graphene TBJ exhibits parabolic voltage transfer characteristic and the polarity of the curvature can be switched by gate voltage owing to the change of the conduction type in the junction. Inversion of voltage signal is successfully realized in the graphene-based TBJ utilizing the polarity switch of the curvature. Obtained voltage gain is 0.013, which is small for applications. Analysis of the observed behaviours using a simple model suggests that the gain can be improved by increasing gate capacitance and by reducing residual carrier concentration. © 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
  • Seiya Kasai, Masashi Aono, Makoto Naruse
    APPLIED PHYSICS LETTERS 103 16 163703-163703-4  2013年10月 [査読有り][通常論文]
     
    We propose an electronic system for implementing a biologically inspired computing architecture, called "amoeba-inspired computing," for solving computationally demanding problems. The system consists of a parallel capacitance network. The spatiotemporal dynamics of an amoeboid organism exhibiting the sophisticated ability of exploring a solution space is mimicked using dynamics in charging the capacitors under charge conservation. The system for solving an instance of a four-variable constraint satisfaction problem (CSP) is implemented using an electronic circuit simulator, which successfully finds solutions. We also found that small fluctuations inherently involved in electronic devices can be used to explore solution space. (C) 2013 AIP Publishing LLC.
  • Masaki Sato, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 52 6 06GE08.1-06GE08.5  2013年06月 [査読有り][通常論文]
     
    Nonlinear voltage transfer characteristics in GaAs-based three-branch nanowire junction (TBJ) devices were investigated by a light-induced local conductance modulation method. In this measurement system, the conductance in the device was locally increased by focused laser light irradiation. The nonlinear transfer curve was greatly changed when the laser light was irradiated on the positively biased branch. The conductance domain was found to exist at the end of the positively biased branch of the TBJ by scanning the light position. When a SiNx thin layer was deposited on the nanowire surface, the surface potential was increased and the nonlinearity in the transfer curve was reinforced simultaneously. The obtained results suggest that the asymmetric channel depletion model is appropriate for the observed nonlinearity mechanism in the GaAs TBJ at room temperature. (c) 2013 The Japan Society of Applied Physics
  • Takayuki Tanaka, Yuki Nakano, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 52 6 06GE07.1-06GE07.6  2013年06月 [査読有り][通常論文]
     
    GaAs-based nanowire devices having multiple asymmetric gates for electrical Brownian ratchets were fabricated and characterized. From three-dimensional potential simulation results and current-voltage characteristics, we confirmed the formation of the asymmetric potential in our device design. Direct current was generated at room temperature by repeatedly switching the potential in a multiple-asymmetric-gate device on and off. Such current was not observed in either a single-asymmetric-gate device or a multiple-symmetric-gate device. The current direction and input frequency dependences of the net current indicated that the observed current was generated by the flashing-ratchet mechanism. (c) 2013 The Japan Society of Applied Physics
  • Yuta Kimura, Yi Sun, Toshihiko Maemoto, Shigehiko Sasa, Seiya Kasai, Masataka Inoue
    JAPANESE JOURNAL OF APPLIED PHYSICS 52 6 06GE09.1-06GE09.3  2013年06月 [査読有り][通常論文]
     
    Self-switching nanodiodes (SSDs) using zinc oxide (ZnO) were fabricated on glass substrates. The SSDs using ZnO have attracted significant attention as transparent devices because of their low cost, abundance in nature, and so on. Rectification characteristics in the SSDs were resemblance to the characteristics of conventional diodes with use of a doping junction or a barrier structure. The changes in characteristics depending on the shape of SSDs were investigated. Channel widths in the SSD of 230 and 190 nm and turn-on voltages of 5 and 8 V were obtained. On the other hand, it was found that the channel length influences the current strength. Moreover, after coating the devices with HfO2 to enhance the electric field coupling, the rectification behavior was maintained while the device current increased dramatically. The SSDs were fabricated using ZnO on flexible plastic substrates. For channel widths of 250 and 200 nm, turn-on voltages of 4 and 6 V were obtained, respectively. We also obtained clear rectification and observed the dependence of the turn-on voltage on the channel width. (c) 2013 The Japan Society of Applied Physics
  • Shaharin Fadzli Abd Rahman, Seiya Kasai, Abdul Manaf Hashim
    SAINS MALAYSIANA 42 2 187 - 192 2013年02月 [査読有り][通常論文]
     
    A graphene-based three-branch nanojunction (TBJ) device having nanowire width of 200 nm was successfully fabricated. The layer number of graphene prepared by mechanical exfoliation was determined using a simple optical contrast method which showed good agreement with theoretical value, n-type doping by Polyethylene imines (PEI) was done to control the position of Dirac point. Baking and PEI doping was found to decrease contact resistance and increase the carrier mobility. The chemically-doped TBJ graphene showed carrier mobility of 20000 cm(2)/Vs, which gave related mean free path of 175 nm.
  • Shaharin Fadzli Abd Rahman, Abdul Manaf Hashim, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 51 6 06FD09.1-06FD09.5  2012年06月 [査読有り][通常論文]
     
    Identification of the number of graphene layers using an optical microscope images taken at various magnifications is investigated from the viewpoint of simple wide-area inspection. For graphene on 300-nm-thick SiO2, combination of red and green color contrast gives more accurate contrast value and provides better contrast even at the low magnification as compared with the single color channel contrast. The color combination with suitable weighting factors taking account of light wavelength and intensity dependences of the system response results in the contrast that agrees well with the theoretical values from Fresnel's law. Simple image processing is also investigated to improve the signal-to-noise ratio (SNR) of the image. Median filtering improves the SNR of the image having high pixel density, whereas dithering is effective for the low magnification image having block noise due to low pixel density. (C) 2012 The Japan Society of Applied Physics
  • Toru Muramatsu, Kensuke Miura, Yuta Shiratori, Zenji Yatabe, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 51 6 06FE18.1-06FE18.5  2012年06月 [査読有り][通常論文]
     
    Low-frequency noise in SiNx insulator-gate GaAs-based etched nanowire field-effect transistors (FETs) is investigated, focusing on the device size dependence and the effect of electron traps in the insulator. Intensity of the drain current noise is found to systematically increase when the nanowire width and gate length decrease, as indicated by the conventional FET noise model. Noise spectrum also changes continuously from 1/f to 1/f(2) with the decrease of the device size, which is not observed in Schottky-gate nanowire FETs. Theoretical analysis shows that traps having short time constants mainly affect on the spectrum slope, whereas those having long time constants only shift the spectrum and do not affect on the slope. Observed size dependence of the spectrum slope is explained by broadening of the distribution of the time constant rather than the change in the combination of discrete traps having different time constants. (C) 2012 The Japan Society of Applied Physics
  • Shaharin Fadzli Abd Rahman, Seiya Kasai, Abdul Manaf Hashim
    APPLIED PHYSICS LETTERS 100 19 193116-193116-3  2012年05月 [査読有り][通常論文]
     
    A chemically doped graphene-based three-branch nanojunction device is fabricated on a SiO2/p-Si substrate, and its nonlinear operation is characterized at room temperature (RT). By polyethyleneimine doping, the fabricated device shows improved field effect mobility of 14 800 and 16 100 cm(2)/Vs for electron and holes, respectively. The device clearly exhibits nonlinearity in voltage transfer curves at RT. The curvature of the transfer curve can be controlled by using the back gate voltage, and its polarity abruptly switches near the Dirac point because of the carrier type change. The observed behaviour can be quantitatively explained in terms of the difference in the amounts of gate-induced carriers in the two input branches. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4711035]
  • Hong-Quan ZHao, Seiya Kasai
    JOURNAL OF NANOMATERIALS 2012年 [査読有り][通常論文]
     
    One-dimensional nanowire quantum devices and basic quantum logic AND and OR unit on hexagonal nanowire units controlled by wrap gate (WPG) were designed and fabricated on GaAs-based one-dimensional electron gas (1-DEG) regular nanowire network with hexagonal topology. These basic quantum logic units worked correctly at 35 K, and clear quantum conductance was achieved on the node device, logic AND circuit unit, and logic OR circuit unit. Binary-decision-diagram-(BDD-) based arithmetic logic unit (ALU) is realized on GaAs-based regular nanowire network with hexagonal topology by the same fabrication method as that of the quantum devices and basic circuits. This BDD-based ALU circuit worked correctly at room temperature. Since these quantum devices and circuits are basic units of the BDD ALU combinational circuit, the possibility of integrating these quantum devices and basic quantum circuits into the BDD-based quantum circuit with more complicated structures was discussed. We are prospecting the realization of quantum BDD combinational circuitries with very small of energy consumption and very high density of integration.
  • Yuta Shiratori, Kensuke Miura, Seiya Kasai
    MICROELECTRONIC ENGINEERING 88 8 2755 - 2758 2011年08月 [査読有り][通常論文]
     
    Programmable nano-switch arrays on GaAs-based nanowire networks are investigated for a reconfigurable binary-decision-diagram (BDD) logic circuit. A programmable switch was simply realized by inserting a SiN(x) thin layer between a metal gate and a nanowire. Fabricated switches were characterized in terms of hysteresis curve, program time dependences of off-state retention time, and on-state current. HCl treatment on SiN(x) prior to metal gate formation was found to remarkably improve the switching characteristics. We experimentally demonstrated correct and stable operation of a four-input reconfigurable BDD circuit integrating the switch array with HCl treatment. (C) 2010 Elsevier B.V. All rights reserved.
  • Hiromu Shibata, Yuta Shiratori, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 50 6 06GF03.1-06GF03.5  2011年06月 [査読有り][通常論文]
     
    A novel set-reset flip-flop (SR-FF) circuit integrating gate-controlled GaAs three-branch nanowire junctions (TBJs) is designed, fabricated, and characterized. Fundamental logic gates including AND, NOT, and NAND are constructed using Schottky wrap gate (WPG)-controlled TBJs together with inverter circuits that have the same configuration. The present SR-FF circuit is simply designed using a pair of cross-coupled TBJ-based NAND gates. The circuit is successfully fabricated on a GaAs-based hexagonal nanowire network. Its correct operation with a voltage transfer gain larger than unity is demonstrated. Reduction of circuit area and possible operation speed are also discussed. (C) 2011 The Japan Society of Applied Physics
  • Kensuke Miura, Yuta Shiratori, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 50 6 06GF18.1-06GF18.5  2011年06月 [査読有り][通常論文]
     
    Low-frequency noise in GaAs-based nanowire field-effect transistors (FETs) controlled by a Schottky wrap gate (WPG) is investigated focusing on the size dependence of 1/f noise and the basic behavior of a gentle slope of the noise spectrum at a relatively high frequency. 1/f noise is found to systematically depend on the nanowire width W and gate length L-G, which is explained by the conventional flicker noise model. The evaluated flicker noise coefficient K-F is on the order of 10(-23) V-2 F, comparable to that of Si metal-oxide-semiconductor (MOS) FETs. The gentle slope close to 1/f(0.5) frequently appears in the noise spectrum from the fabricated devices. Its intensity is found to be proportional to gate leakage current, suggesting that electrons flowing through the AlGaAs barrier layer induce generation-recombination (GR) noise in the gate region. (C) 2011 The Japan Society of Applied Physics
  • Chen Chen, Rui Jia, Haofeng Li, Yanlong Meng, Xinyu Liu, Tianchun Ye, Seiya Kasai, Hashizume Tamotsu, Nanjian Wu, Shanli Wang, Junhao Chu
    APPLIED PHYSICS LETTERS 98 14 143108  2011年04月 [査読有り][通常論文]
     
    In the case of the silicon (Si) nanowire (NW)-array-textured solar cells, the electrode-contact enhancement has been achieved using a simple and convenient double-step diffusion process to form a highly doped N+ region at the tips of a Si-NW array. The series resistance can be effectively reduced, leading to an increase in the short-circuit current density in the cell. We have studied the physical mechanism of the impact of an increase in doping level at the tips of a Si-NW array on the electrode-contact property, which would benefit in realizing an improvement in cell performance in such a nanostructure solar cell. (C) 2011 American Institute of Physics. [doi:10.1063/1.3576924]
  • Weilong Li, Rui Jia, Chen Chen, Haofeng Li, Xinyu Liu, Huihui Yue, Wuchang Ding, Tianchun Ye, Seiya Kasai, Tamotsu Hashizume, Nanjian Wu, Bingshe Xu
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 29 2 021018  2011年03月 [査読有り][通常論文]
     
    Annealing thin films of silicon containing HfO2 films deposited by an electron-beam coevaporation produces silicon nanocrystals embedded in high-kappa dielectric HfO2. Such films can be used to fabricate nonvolatile memory devices. By changing the Si content in the precursor HfSixO2 (x=1, 2, 3, or 4) film, the size and density of silicon nanocrystal could be controlled and high-density of silicon nanocrystals could be obtained. Transmission electron microscopy observations showed that the maximum density of silicon nanocrystals was as high as 1.3 x 10(13) cm(-2) for HfSi4O2 and the average nanocrystal diameter was 4.3 nm. The metal-oxide semiconductor capacitor memory structure with embedded silicon nanocrystals in HfSi4O2 exhibited the largest memory window, 3.94 V under +/- 5 V sweep voltage. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3554736]
  • Chen Chen, Rui Jia, Huihui Yue, Haofeng Li, Xinyu Liu, Tianchun Ye, Seiya Kasai, Hashizume Tamotsu, Nanjian Wu, Shanli Wang, Junhao Chu, Bingshe Xu
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 29 2 021014  2011年03月 [査読有り][通常論文]
     
    Silicon (Si) nanostructure solar cells have been synthesized using a nanowire (NW) array as the surface texturing. Optical-reflection measurement exhibits an excellent photon-harvesting property for the Si-NW-array texturization. Less than 2% reflection ratio at an 800 nm wavelength was achieved. Results show that an optimized 125 x 125 mm(2) Si nanostructure solar cell with an excellent photon-harvesting property has a 35.4% higher energy-conversion efficiency than the c-Si solar cell due to its enhanced optical-absorption characteristics. However, for the nanostructured solar cells, the decrease in external quantum efficiencies in the short-wavelength region proves that the surface recombination plays a critical role in determining the final quantum-efficiency performance, indicating that optimum surface passivation was a prerequisite in high-efficiency Si nanostructure solar cells. (C) 2011 American Vacuum Society. [DOI: 10.1116/1.3548876]
  • Chen Chen, Rui Jia, Huihui Yue, Haofeng Li, Xinyu Liu, Tianchun Ye, Seiya Kasai, Hashizume Tamotsu, Nanjian Wu, Shanli Wang, Junhao Chu, Bingshe Xu
    Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics 29 2 2011年 [査読有り][通常論文]
     
    Silicon (Si) nanostructure solar cells have been synthesized using a nanowire (NW) array as the surface texturing. Optical-reflection measurement exhibits an excellent photon-harvesting property for the Si-NW-array texturization. Less than 2% reflection ratio at an 800 nm wavelength was achieved. Results show that an optimized 125×125 mm2 Si nanostructure solar cell with an excellent photon-harvesting property has a 35.4% higher energy-conversion efficiency than the c -Si solar cell due to its enhanced optical-absorption characteristics. However, for the nanostructured solar cells, the decrease in external quantum efficiencies in the short-wavelength region proves that the surface recombination plays a critical role in determining the final quantum-efficiency performance, indicating that optimum surface passivation was a prerequisite in high-efficiency Si nanostructure solar cells. © 2011 American Vacuum Society.
  • Weilong Li, Rui Jia, Chen Chen, Haofeng Li, Xinyu Liu, Huihui Yue, Wuchang Ding, Tianchun Ye, Seiya Kasai, Tamotsu Hashizume, Nanjian Wu, Bingshe Xu
    Journal of Vacuum Science and Technology B:Nanotechnology and Microelectronics 29 2 2011年 [査読有り][通常論文]
     
    Annealing thin films of silicon containing HfO2 films deposited by an electron-beam coevaporation produces silicon nanocrystals embedded in high- κ dielectric HfO2. Such films can be used to fabricate nonvolatile memory devices. By changing the Si content in the precursor HfSix O2 (x=1, 2, 3, or 4) film, the size and density of silicon nanocrystal could be controlled and high-density of silicon nanocrystals could be obtained. Transmission electron microscopy observations showed that the maximum density of silicon nanocrystals was as high as 1.3× 1013 cm-2 for HfSi4 O2 and the average nanocrystal diameter was 4.3 nm. The metal-oxide semiconductor capacitor memory structure with embedded silicon nanocrystals in HfSi4 O2 exhibited the largest memory window, 3.94 V under ±5 V sweep voltage. © 2011 American Vacuum Society.
  • Seiya Kasai, Yuta Shiratori, Kensuke Miura, Yuta Nakano, Toru Muramatsu
    PHYSICA STATUS SOLIDI C: CURRENT TOPICS IN SOLID STATE PHYSICS, VOL 8, NO 2 8 2 2011年 [査読有り][通常論文]
     
    Control of stochastic resonance (SR) response in a GaAs-based nanowire FET is investigated for its application to nanoelectronics. The SR is a phenomenon in which the response to a weak signal is optimized by adding noise. Experiments clarify that the peak position is controlled by the gate offset voltage. The peak height also depends on the offset voltage and decreases when the peak position places in high noise region. Theoretical analysis indicates that the peak position depends only on the offset voltage whereas the height is also controlled by device dimensions. (C) 2010 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
  • Chen Chen, Rui Jia, Huihui Yue, Haofeng Li, Xinyu Liu, Deqi Wu, Wuchang Ding, Tianchun Ye, Seiya Kasai, Hashizume Tamotsu, Junhao Chu, Shanli Wang
    JOURNAL OF APPLIED PHYSICS 108 9 094318  2010年11月 [査読有り][通常論文]
     
    In this paper, a vertical-aligned silicon nanowires (Si NWs) array has been synthesized and implemented to the Si NW-array-textured solar cells for photovoltaic application. The optical properties of a Si NWs array on both the plane and pyramid-array-textured substrates were examined in terms of optical reflection property. Less than 2% reflection ratio at 800 nm wavelength was achieved. Using leftover monocrystalline Si (c-Si) wafer (125 x 125 mm(2)), a 16.5% energy conversion efficiency, with 35.4% enhancement compared to the pyramid-array-textured c-Si solar cells, was made by the Si NW-array-textured solar cells due to their enhanced optical absorption characteristics. However, without SiNx passivation, the short circuit current reduced due to the increased surface recombination when using Si NWs array as surface texturing, indicating that an optimum surface passivation was prerequisite in high-efficiency Si NW-array-textured solar cells. (C) 2010 American Institute of Physics. [doi:10.1063/1.3493733]
  • Yasufumi Hakamata, Yasuhide Ohno, Kenzo Maehashi, Seiya Kasai, Koichi Inoue, Kazuhiko Matsumoto
    JOURNAL OF APPLIED PHYSICS 108 10 104313  2010年11月 [査読有り][通常論文]
     
    Stochastic resonance (SR) in carbon nanotube field-effect transistors (CNT-FETs) was investigated to enhance their weak-signal response. When weak pulse trains were applied to the gate of a CNT-FET operating in a subthreshold region, the correlation between the input and output voltages increased upon addition of noise with optimized intensity. Virtual CNT-FET summing networks of N units were demonstrated to improve SR. When no noise was applied for N = 1, the correlation coefficient was nearly 0. While, the correlation coefficient at the peak intensity for N = 8 was estimated to be 0.58, indicating that significant enhancement of the correlation was observed in the summing network of the CNT-FETs. Moreover, as N increased, the larger correlation coefficient was obtained against large noise intensity, indicating that they are robust against a large amount of unintentional noise. Therefore, CNT-FET summing networks based on SR are promising candidates for highly sensitive label-free sensors. (C) 2010 American Institute of Physics. [doi: 10.1063/1.3514540]
  • Seiya Kasai, Kensuke Miura, Yuta Shiratori
    APPLIED PHYSICS LETTERS 96 19 194102  2010年05月 [査読有り][通常論文]
     
    Stochastic resonance in a summing network with varied thresholds was investigated using GaAs-based etched nanowire field-effect transistors having different threshold voltages. The network's response adapted to input offset fluctuations in the range of the threshold voltage variation and the network could detect a weak signal without any adjustment of the input offset or the addition of high noise. The observed adaptability resulted from a widened dynamic range of the system due to signal decomposition and reconstruction by multiple thresholds together with the output summation process. (C) 2010 American Institute of Physics. [doi:10.1063/1.3428784]
  • 葛西誠也
    計測と制御 49 4 229 - 235 計測自動制御学会 2010年04月10日 [査読無し][通常論文]
  • Daisuke Nakata, Hiromu Shibata, Yuta Shiratori, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 49 6 06GG03.1-06GG03.5  2010年 [査読有り][通常論文]
     
    Nonlinear voltage transfer characteristics in GaAs-based three-branch nanowire junctions (TBJs) controlled by Schottky wrap gates (WPGs) are investigated by characterization of the gate voltage and size dependences in detail. WPGs squeezed the nanowires only in the node portion and modulated the curve only in the low-input-voltage region. When the entire nanowire was narrowed geometrically, the voltage transfer curve became abrupt in a wide voltage range. On the other hand, the nanowire length affected only the curve in the high-input-voltage region. These results indicate that the voltage transfer characteristics of the WPG-controlled TBJ device in the low-and high-voltage regions are controlled by the junction node with WPGs and the end of the positively biased nanowire, respectively. The observed behaviors can be understood in terms of a surface-potential-induced field domain model. (C) 2010 The Japan Society of Applied Physics
  • Yuta Shiratori, Kensuke Miura, Rui Jia, Nan-Jian Wu, Seiya Kasai
    APPLIED PHYSICS EXPRESS 3 2 025002.1-025002.3  2010年 [査読有り][通常論文]
     
    We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation on a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect a small number of branches. This circuit has a compact structure with a small number of devices compared with the conventional look-up table architecture. A variable Boolean logic circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches, and its correct logic operation together with dynamic reconfiguration was demonstrated. (C) 2010 The Japan Society of Applied Physics DOI: 10.1143/APEX.3.025002
  • A. M. Hashim, S. Kasai, H. Hasegawa, Q. I. Alias
    INTERNATIONAL CONFERENCE ON ADVANCEMENT OF MATERIALS AND NANOTECHNOLOGY 2007 1217 19 - + 2010年 [査読有り][通常論文]
     
    Plasma waves are oscillations of electron density in time and space, and in deep submicron field effect transistors, typical plasma frequencies,omega(p), lie in the terahertz range and do not involve any quantum transitions. Hence, using plasma wave excitation for detection and/or generation of THz oscillations is a very promising approach. In this paper, the investigation of plasma wave interaction between the plasma waves propagating in a short-channel High-Electron-Mobility Transistor (HEMT) and the radiated electromagnetic waves was carried out. Experimentally, we have demonstrated the detection of the terahertz (THz) radiation by an AlGaAs/GaAs HEMT up to third harmonic at room temperature and their resonant responses show very good agreement with the calculated results.
  • Chen Chen, Rui Jia, Weilong Li, Haofeng Li, Tianchun Ye, Xinyu Liu, Ming Liu, Seiya Kasai, Hashizume Tamotsu, Nanjian Wu
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 27 6 2462 - 2467 2009年11月 [査読有り][通常論文]
     
    In this article, a simple and flexible electron-beam coevaporation (EBCE) technique has been reported of fabrication of the silicon nanocrystals (Si NCs) and their application to the nonvolatile memory. For EBCE, the Si and SiOx(x=1 or 2) were used as source materials. Transmission electron microscopy images and Raman spectra measurement verified the formation of the Si NCs. The average size and area density of the Si NCs can be adjusted by increasing the Si:O weight ratio in source material, which has a great impact on the crystalline volume fraction of the deposited film and on the charge storage characteristics of the Si NCs. A memory window as large as 6.6 V under +/- 8 V sweep voltage was observed for the metal-oxide-semiconductor capacitor structure with the embedded Si NCs.
  • 有田 正志, 菅原 陽, 植村 哲也, 足立 智, 菅原 広剛, 葛西 誠也, 松田 健一, 佐藤 威友, 高橋 庸夫, 福井 孝志
    応用物理教育 33 1 25 - 30 2009年07月31日 [査読無し][通常論文]
  • Hong-Quan Zhao, Seiya Kasai, Yuta Shiratori, Tamotsu Hashizume
    NANOTECHNOLOGY 20 24 245203  2009年06月 [査読有り][通常論文]
     
    A two-bit arithmetic logic unit (ALU) was successfully fabricated on a GaAs-based regular nanowire network with hexagonal topology. This fundamental building block of central processing units can be implemented on a regular nanowire network structure with simple circuit architecture based on graphical representation of logic functions using a binary decision diagram and topology control of the graph. The four-instruction ALU was designed by integrating subgraphs representing each instruction, and the circuitry was implemented by transferring the logical graph structure to a GaAs-based nanowire network formed by electron beam lithography and wet chemical etching. A path switching function was implemented in nodes by Schottky wrap gate control of nanowires. The fabricated circuit integrating 32 node devices exhibits the correct output waveforms at room temperature allowing for threshold voltage variation.
  • Shaharin Fadzli Bin Abd Rahman, Daisuke Nakata, Yuta Shiratori, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 48 6 06FD01.1-06FD01.4  2009年06月 [査読有り][通常論文]
     
    A GaAs-based three-branch nanowire junction (TBJ) with Schottky wrap gates (WPGs) is investigated to realize novel Boolean logic gates, The WPG-controlled TBJ shows a bell-shaped voltage input-output curve and is controlled by gate voltage on the WPGs. The observed characteristics are explained using a simple equivalent circuit model. AND gate operation is realized in the WPG-controlled TBJ and its output voltage swing is controlled using WPGs. It can also operate as a NOT gate by changing the measurement circuit. A NAND gate is fabricated by integrating two WPG-controlled TBJs, and correct operation with a voltage transfer gain of 2.2 is realized. (C) 2009 The Japan Society of Applied Physics
  • Investigation on Stochastic Resonance in A Quantum Dot and Its Summing Network
    S. Kasai
    International Journal of Nanotechnology and Molecular Computation 1 70 - 79 2009年 [査読無し][通常論文]
  • Investigation on Stochastic Resonance in A Quantum Dot and Its Summing Network
    Seiya Kasai
    International Journal of Nanotechnology and Molecular Computation 1 70 - 79 2009年 [査読無し][通常論文]
  • Abdul Manaf Hashim, Zon Fazlila Mohd Ahir, Seiya Kasai, Hideki Hasegawa
    FRONTIERS IN PHYSICS-BOOK 1150 328 - + 2009年 [査読有り][通常論文]
     
    Plasma waves are oscillations of electron density in time and space, and in deep submicron field effect transistors, typical plasma frequencies, omega(p), lie in the terahertz (THz) range and do not involve any quantum transitions. Hence, using plasma wave excitation for detection and/or generation of THz oscillations is a very promising approach. In this paper, the investigation of plasma wave interaction between the plasma waves propagating in a short-channel High-Electron-Mobility Transistor (HEMT) and the radiated electromagnetic waves was carried out. Experimentally, we have demonstrated the detection of the terahertz (THz) radiation by an AlGaAs/GaAs HEMT up to third harmonic at room temperature and their resonant responses show very good agreement with the calculated results.
  • Abdul Manaf Hashim, Zon Fazlila Mohd Ahir, Seiya Kasai, Tamotsu Hashizume, Hideki Hasegawa
    FRONTIERS IN PHYSICS-BOOK 1150 311 - + 2009年 [査読有り][通常論文]
     
    A theoretical three-dimensional transverse magnetic (TM) mode analysis to describe the presence of interactions between surface plasma waves of carriers in a two-dimensional electron gas (2DEG) at AlGaAs/GaAs heterostructure and electromagnetic space harmonics slow waves using the so-called interdigital-gated high-electron-mobility-transistor (HEMT) plasma wave devices is presented. First, the device structure and the outline of theoretical formulation to determine the admittance of the interdigital structure are described. Then, the analysis of the space harmonics propagating through the interdigital slow-wave structures is performed. Next, the numerical procedures to solve the integral equations which are used in determining the admittance are explained. Finally, we point out and discuss the main results of the theoretical analysis where an appearance of negative conductance is obtained.
  • Seiya Kasai, Yuta Shiratori, Kensuke Miura, Nan-Jian Wu
    ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC 331 - + 2009年 [査読有り][通常論文]
     
    Simple and compact multi-path switching devices for multi-valued decision diagram (MDD)-based logic circuits are designed, fabricated and characterized. The devices switch multiple exit branches for electrons entering from an entry branch, according to multi-valued input. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages. The gate threshold voltage is controlled by precise design of gate structures and sizes in nanometer scale. The operation principle of the device is described using a simple analytical model. Ternary-path switching devices are demonstrated using AlGaAs/GaAs etched nanowire junctions together with nanometer-scale Schottky wrap gates (WPGs) and in-plane gates (IPGs).
  • Wan-cheng Zhang, Nan-jian Wu, Tamotsu Hashizume, Seiya Kasai
    ISMVL: 2009 39TH IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC 337 - + 2009年 [査読有り][通常論文]
     
    This paper proposes novel multiple-valued (MV) logic gates by using asymmetric single-electron transistors (SETs). Asymmetric single-electron transistors have two tunneling junctions with largely different resistances and capacitances. We fully exploited the Unique Coulomb staircase characteristic of asymmetric SETs to compactly, finish logic operations. We build MV literal gates with wide range Of radixes by using a pair of asymmetric SETs. We showed that, arbitrary radix-4 literal gate can be realized using a pair of asymmetric SETs. We also proposed AN analog-digital conversion circuits. The MV logic gates have very compact structures and low power dissipation.
  • Seiya Kasai
    2009 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS 2009) 363 - 366 2009年 [査読有り][通常論文]
     
    Stochastic resonance (SR) in nanodevice parallel network systems is described. The SR is a phenomenon in which the response of the system is enhanced by adding noise. Parallel network of GaAs-based nanowire field-effect transistors (FETs) operating in subthreshold region exhibits enhanced signal response by noise addition. Input-output signal correlation shows a peak in optimal noise, confirming the appearance of the SR. Massive parallelism realizes robustness against fluctuation of noise intensity. For ultra-low-power electronic SR, a single-electron quantum dot (QD) parallel network system is investigated by simulation and theoretical analysis. The mechanism and detail behaviors are discussed.
  • Abdul Manaf Hashim, Seiya Kasai, Hideki Hasegawa
    SUPERLATTICES AND MICROSTRUCTURES 44 6 754 - 760 2008年12月 [査読有り][通常論文]
     
    Plasma waves are oscillations of electron density in time and space, and in deep submicron field effect transistors, typical plasma frequencies, omega(p), lie in the terahertz (THz) range and do not involve any quantum transitions. Hence, using plasma wave excitation for detection and/or generation of THz oscillations is a very promising approach. In this paper, the investigation of plasma wave interaction between the plasma waves propagating in a short-channel High-Electron-Mobility Transistor (HEMT) and the radiated electromagnetic waves was carried out. Experimentally, we have demonstrated the detection of the terahertz (THz) radiation by an AlGaAs/GaAs HEMT up to third harmonic at room temperature and their resonant responses show very good agreement with the calculated results. Crown Copyright (C) 2008 Published by Elsevier Ltd. All rights reserved.
  • Seiya Kasai, Tetsuya Asai
    APPLIED PHYSICS EXPRESS 1 8 083001.1-083001.3  2008年08月 [査読有り][通常論文]
     
    Investigation of stochastic resonance in GaAs-based nanowire field-effect transistors (FETs) controlled by Schottky wrap gate and their networks is described. When a weak pulse train is given to the gate of the FET operating in a subthreshold region, the correlation between the input-pulse and source-drain current increases by adding input noise. Enhancement of the correlation is observed in a summing network of the FETs. Measured correlation coefficient of the present system can be larger than that in a linear system in the wide range of noise. An analytical model based on the electron motion over a gate-induced potential barrier quantitatively explains the experimental behaviors. (C) 2008 The Japan Society of Applied Physics.
  • Hong-Quan Zhao, Seiya Kasai, Tamotsu Hashizume, Nan-Jian Wu
    IEICE TRANSACTIONS ON ELECTRONICS E91C 7 1063 - 1069 2008年07月 [査読有り][通常論文]
     
    For realization of hexagonal BDD-based digital systems, active and sequential circuits including inverters, flip flops and ring oscillators are designed and fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gates (WPGs), and their operations are characterized. Fabricated inverters show comparatively high transfer gain of more than 10. Clear and correct operation of hexagonal set-reset flip flops (SR-FFs) is obtained at room temperature. Fabricated hexagonal D-type flip flop (D-FF) circuits integrating twelve WPG field effect transistors (FETs) show capturing input signal by triggering although the output swing is small. Oscillatory output is successfully obtained in a fabricated 7-stage hexagonal ring oscillator. Obtained results confirm that a good possibility to realize practical digital systems can be implemented by the present circuit approach.
  • Seiya Kasai, Tatsuya Nakamura, Shaharin Fadzli Bin Abd Rahmani, Yuta Shiratori
    JAPANESE JOURNAL OF APPLIED PHYSICS 47 6 4958 - 4964 2008年06月 [査読有り][通常論文]
     
    The nonlinear electrical characteristics of GaAs-based three-branch nanowire junction (TBJ) devices having Schottky wrap Pies (WPGs) are investigated experimentally and theoretically, focusing on the nonlinear mechanism at room temperature in devices with large dimensions and the improvement of voltage transfer efficiency. Input-output voltage transfer curve, V(out)-V(in) is characterized by changing nanowire width, W, temperature, T, and WPG gate voltage, V(G), systematically. At room temperature, a bell-shaped V(out)-V(in) curve is observed even in the device having a nanowire width of 1,500 nm, which is ten times larger than the electron mean free path. With decreasing wire width or temperature, the output curves are sharpened and curvature in the low-input-voltage region increases. The curvature rapidly increases and voltage transfer efficiency, Delta V(out)/Delta V(in), approaches unity when V(G) is decreased into the subthreshold region. A simple and compact model for the nonlinear characteristics in the nonballistic regime is introduced. The rapid change of the curvature and complex curve in the subthreshold region under V(G) control is due to the switching of the branch condition from resistive to capacitive by depletion underneath the WPG.
  • Yuta Shiratori, Seiya Kasai
    JAPANESE JOURNAL OF APPLIED PHYSICS 47 4 3086 - 3090 2008年04月 [査読有り][通常論文]
     
    The effect of size reduction on switching characteristics is investigated experimentally for the low-switching-power operation of GaAs-based quantum wire transistors (QWRTr's) utilizing etched AlGaAs/GaAs nanowires controlled by Schottky wrap gates (WPGs). WPG QWRTr's in which the wire width, W, and gate length, L(G), are systematically changed are fabricated and characterized with respect to operation temperature, switching voltage, Delta V(G), gate voltage to Fermi energy scaling factor, a, and power-delay product, PDP. When W is less than 200nm, more than 80% of the fabricated devices exhibit quantized conductance at 30 K. The device with W = 40 mm shows a large alpha of 0.7. Decreasing L(G) into the sub- 100-nm range is found to be effective for improving power consumption, since the short channel effect is suppressed by tight potential control in the WPG structure.
  • Takahiro Tamura, Junji Kotani, Seiya Kasai, Tamotsu Hashizume
    APPLIED PHYSICS EXPRESS 1 2 023001.1-023001.3  2008年02月 [査読有り][通常論文]
     
    We fabricated a multi-mesa-channel (MMC) structure by forming a periodic trench just under a gate electrode to improve the uniformity of effective electric field in the channel in an AlGaN/GaN high electron mobility transistor (HEMT). A unique performance, i.e., a nearly temperature-independent saturation drain current, was observed in the MMC device in a wide temperature range. A two-dimensional (2D) potential calculation indicates that the mesa-side gate effectively modulates the potential, resulting in a field surrounding 2D electron gas. Such a surrounding-field effect and a relatively lower source access resistance may be related to a unique current behavior in the MMC HEMT. (C) 2008 The Japan Society of Applied Physics.
  • Abdul Manaf Hashim, Seiya Kasai, Kouichi Iizuka, Tamotsu Hashizume, Hideki Hasegawa
    MICROELECTRONICS JOURNAL 38 12 1268 - 1272 2007年12月 [査読有り][通常論文]
     
    Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc 1-V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the de-connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10-40 GHz showed the conductance modulation by drain-source voltage. These results indicate the existence of plasma wave interactions. (C) 2007 Elsevier Ltd. All rights reserved.
  • Abdul Manaf Hashim, Seiya Kasai, Tamotsu Hashizume, Hideki Hasegawa
    MICROELECTRONICS JOURNAL 38 12 1263 - 1267 2007年12月 [査読有り][通常論文]
     
    Interdigital-gated AlGaAs/GaAs high-electron-mobility transistor (HEMT) structure was used to investigate the interaction between the drifting carrier plasma waves and electromagnetic (EM) waves. It was shown theoretically that the interaction in the range from microwave to terahertz (THz) at room temperature should produce negative conductance characteristics when the carrier drift velocity slightly exceeds the phase velocity of EM waves. S-parameter reflection measurements were carried out at room temperature for a frequency range from 1 to 20 GHz and a drastic change in conductance was observed at 5 and 10 GHz with the increase of drain-source voltage. Large conductance change over 1000mS/mm was obtained and it showed a peak at a certain frequency. The peak position could be controlled by changing the pitch size of the interdigital gates. These characteristics can be used for high-frequency applications such as high-speed switching devices although a feature size of our interdigital-gated HEMT device is much larger than conventional HEMT device. (C) 2007 Elsevier Ltd. All rights reserved.
  • Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori, Takahiro Tamura
    JOURNAL OF COMPUTATIONAL AND THEORETICAL NANOSCIENCE 4 6 1120 - 1132 2007年09月 [査読有り][通常論文]
     
    Novel quantum-nanodevice-integrated logic circuits by the combination of binary decision diagram (BDD) logic architecture and semiconductor nanowire networks controlled by Schottky wrap gates (WPGs) are presented. Simple, small and flexible structure with fine gate control of the WPG gives opportunity to implement a directed graph of a Boolean function on the nanowire network topologically. Quantum wire- and single electron-type WPG-based node device are designed for BDD circuits and their operations are investigated experimentally. WPG BDD logic circuits from elemental logic functions to subsystems using GaAs-based nanowire networks with hexagonal and 2D hypercube topologies are demonstrated. Feasibility of the WPG BDD circuits is confirmed by successful implementation of an ultra-small and ultra-low-power digital system, nanoprocessor, on a hexagonal network. Device and circuit performances of the present approach are also discussed.
  • Junji Kotani, Masafumi Tajima, Seiya Kasai, Tamotsu Hashizume
    APPLIED PHYSICS LETTERS 91 9 093501-1-093501-3  2007年08月 [査読有り][通常論文]
     
    Lateral surface leakage current (I-S) on an AlGaN/GaN heterostructure was systematically investigated by using a two-parallel gate structure with a gap distance (L-GG) of 200 nm-5 mu m. The surface current I-s systematically increased as LGG decreased. A simple resistive layer conduction that should show 1/L-GG dependence failed to account for the drastic increase in Is when LGG was reduced to less than 1 mu m. However, no dependence on L-GG was seen in vertical current that flows in the Schottky interface. The I-s showed a clear temperature dependence proportional to exp(-T (-1/ 3)), indicating two-dimensional variable-range hopping through high-density surface electronic states in AlGaN. A pronounced reduction in surface current of almost four orders of magnitude was observed in a sample with SiNx passivation. (c) 2007 American Institute of Physics.
  • Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori
    APPLIED PHYSICS LETTERS 90 20 203504  2007年05月 [査読無し][通常論文]
     
    A multipath-switching device using a multiterminal nanowire junction with size-controlled dual gates is proposed and demonstrated experimentally. The device switches a number of output terminals according to multiple-valued input voltages for electrons entering from a root terminal. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages V-th. Systematic V-th shift is made by changing gate lengths in nanometer scale. A triple-path-switching device is fabricated using AlGaAs/GaAs etched nanowires and nanometer-scale Schottky wrap gates. Its correct operation is confirmed at room temperature. Obtained results are explained by a simple analytical model. (C) 2007 American Institute of Physics.
  • Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori
    APPLIED PHYSICS LETTERS 90 20 203504  2007年05月 [査読無し][通常論文]
     
    A multipath-switching device using a multiterminal nanowire junction with size-controlled dual gates is proposed and demonstrated experimentally. The device switches a number of output terminals according to multiple-valued input voltages for electrons entering from a root terminal. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages V-th. Systematic V-th shift is made by changing gate lengths in nanometer scale. A triple-path-switching device is fabricated using AlGaAs/GaAs etched nanowires and nanometer-scale Schottky wrap gates. Its correct operation is confirmed at room temperature. Obtained results are explained by a simple analytical model. (C) 2007 American Institute of Physics.
  • Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori
    APPLIED PHYSICS LETTERS 90 20 203504-203504-3  2007年05月 [査読有り][通常論文]
     
    A multipath-switching device using a multiterminal nanowire junction with size-controlled dual gates is proposed and demonstrated experimentally. The device switches a number of output terminals according to multiple-valued input voltages for electrons entering from a root terminal. The switching function is implemented by dual gating on multiple nanowires with different threshold voltages V-th. Systematic V-th shift is made by changing gate lengths in nanometer scale. A triple-path-switching device is fabricated using AlGaAs/GaAs etched nanowires and nanometer-scale Schottky wrap gates. Its correct operation is confirmed at room temperature. Obtained results are explained by a simple analytical model. (C) 2007 American Institute of Physics.
  • Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, Seiya Kasai
    IEEE TRANSACTIONS ON NANOTECHNOLOGY 6 2 146 - 157 2007年03月 [査読無し][通常論文]
     
    This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.
  • Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, Seiya Kasai
    IEEE TRANSACTIONS ON NANOTECHNOLOGY 6 2 146 - 157 2007年03月 [査読無し][通常論文]
     
    This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.
  • Wancheng Zhang, Nan-Jian Wu, Tamotsu Hashizume, Seiya Kasai
    IEEE TRANSACTIONS ON NANOTECHNOLOGY 6 2 146 - 157 2007年03月 [査読有り][通常論文]
     
    This paper proposes two kinds of novel hybrid voltage controlled ring oscillators (VCO) using a single electron transistor (SET) and metal-oxide-semiconductor (MOS) transistor. The novel SET/MOS hybrid VCO circuits possess the merits of both the SET circuit and the MOS circuit. The novel VCO circuits have several advantages: wide frequency tuning range, low power dissipation, and large load capability. We use the SPICE compact macro model to describe the SET and simulate the performances of the SET/MOS hybrid VCO circuits by HSPICE simulator. Simulation results demonstrate that the hybrid circuits can operate well as a VCO at room temperature. The oscillation frequency of the VCO circuits could be as high as 1 GHz, with a -71 dBc/Hz phase noise at 1 MHz offset frequency. The power dissipations are lower than 2 uW. We studied the effect of fabrication tolerance, background charge, and operating temperature on the performances of the circuits.
  • Tatsuya Nakamura, Seiya Kasai, Yuta Shiratori, Tamotsu Hashizume
    APPLIED PHYSICS LETTERS 90 10 102104-102104-3  2007年03月 [査読有り][通常論文]
     
    A three-terminal nanowire junction device controlled by double nanometer-sized Schottky wrap gates (WPGs), which control left and right branches independently, are fabricated utilizing AlGaAs/GaAs etched nanowires and characterized experimentally. Fabricated device exhibits clear nonlinear characteristics of output voltage at the center terminal by applying voltages to left and right terminals in push-pull fashion. Applying asymmetric gate voltages to left and right WPGs provides clear asymmetry in the output voltage. The nonlinearity in the low voltage regions is greatly enhanced by squeezing both left and right branches using WPGs. (c) 2007 American Institute of Physics.
  • Rui Jia, Seiya Kasai, Qing Wang, Shi Bing Long, Jie Bin Niu, Zhi Gang Li, Ming Liu
    APPLIED PHYSICS LETTERS 90 13 132124-132124-3  2007年03月 [査読有り][通常論文]
     
    Side-gating behaviors of GaAs-based quantum wire transistors (QWRTr's) were investigated. Using AlGaAs/GaAs high electron mobility transistor wafer, the QWRTr was fabricated with a nanosized side gate beside the nanowire. Anomalous large side-gating effect was found for the QWRTr. Experiments showed that the large side-gating effect was owing to the strong surface Fermi level pinning around the nanowire, which is caused by a thin layer of deep traps located at the surface. Then, Si interface control layer passivation technology was performed to remove the large side gating. (c) 2007 American Institute of Physics.
  • Seiya Kasai, Tatsuya Nakamura, Yuta Shiratori
    JOURNAL OF MULTIPLE-VALUED LOGIC AND SOFT COMPUTING 13 3 267 - 277 2007年 [査読有り][通常論文]
     
    A novel simple and compact multiple-path-switching device for multiple-valued decision diagram (MDD) is proposed and investigated theoretically in order to realize high-performance nanowire-network-based logic circuits with advanced functionality. The device is designed on multi-semiconductor-nanowire branches having a couple of size-controlled nanometer-scale Schottky wrap gates (WPGs). The device selects an exit branch for messenger electrons according to gate voltage as a multiple-valued input variable. The path-switching function is realized by multiple assign of gate threshold voltages and applying complementary gate voltages to the two WPGs. Theoretical investigation based on three-dimensional potential simulation confirms that clear current path switching takes place in the proposed device.
  • Abdul Manaf Hashim, Seiya Kasai, Kouichi Iizuka, Tamotsu Hashizume, Hideki Hasegawa
    SOLID STATE SCIENCE AND TECHNOLOGY 909 180 - + 2007年 [査読有り][通常論文]
     
    Theoretical analysis of potential distribution in the interdigital-gated high electron mobility transistor (HEMT) plasma wave device was carried out. The dc I-V characteristics of capacitively coupled interdigital structure showed that uniformity of electric field under the interdigital gates was improved compared to the dc connected interdigital gate structure. Admittance measurements of capacitively coupled interdigital gate structure in the microwave region of 10-40 GHz showed the conductance modulation by drain-source voltage. These results indicate the existence of plasma wave interactions.
  • Rui Jia, Hideki Hasegawa, Naoko Shiozaki, Seiya Kasai
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 24 4 2060 - 2068 2006年07月 [査読無し][通常論文]
     
    In order to establish feasibility of high density integration of gate-controlled GaAs nanodevices, this article investigates device interference in GaAs-based quantum wire transistors (QWRTrs) by using a side-gating test structure and attempts to suppress the observed anomalously large side-gating with surface passivation using a silicon interface control layer (Si ICL). QWRTrs were formed on AlGaAs/GaAs etched quantum wires (QWRs) and were controlled by nanometer sized Schottky wrap gates. A Schottky side gate was formed at a distance d(sg) from the QWR. When d(sg) was large, the QWRTr showed weak side gating which can be explained by the electrostatic side gating. However, when the side gates was placed close to the nanowire with d(sg) < 500 nm, anomalously large side gating started to take place which cannot be explained by the electrostatic side gating. On the basis of detailed measurements of side-gating behavior and side-gate leakage currents at various temperatures, the anomalous side gating was explained by a model in which occupation of deep traps at the back AlGaAs/GaAs interface of the QWR is modulated by tunneling injection of electrons from the side-gate edge resulting from strong Fermi level pinning by surface states. Based on this model, attempts to reduce surface states by surface passivation were made. Formation of the Si ICL structure on a regrown thin GaAs cap layer completely removed the anomalous side-gating effect. (c) 2006 American Vacuum Society.
  • Rui Jia, Hideki Hasegawa, Naoko Shiozaki, Seiya Kasai
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 24 4 2060 - 2068 2006年07月 [査読無し][通常論文]
     
    In order to establish feasibility of high density integration of gate-controlled GaAs nanodevices, this article investigates device interference in GaAs-based quantum wire transistors (QWRTrs) by using a side-gating test structure and attempts to suppress the observed anomalously large side-gating with surface passivation using a silicon interface control layer (Si ICL). QWRTrs were formed on AlGaAs/GaAs etched quantum wires (QWRs) and were controlled by nanometer sized Schottky wrap gates. A Schottky side gate was formed at a distance d(sg) from the QWR. When d(sg) was large, the QWRTr showed weak side gating which can be explained by the electrostatic side gating. However, when the side gates was placed close to the nanowire with d(sg) < 500 nm, anomalously large side gating started to take place which cannot be explained by the electrostatic side gating. On the basis of detailed measurements of side-gating behavior and side-gate leakage currents at various temperatures, the anomalous side gating was explained by a model in which occupation of deep traps at the back AlGaAs/GaAs interface of the QWR is modulated by tunneling injection of electrons from the side-gate edge resulting from strong Fermi level pinning by surface states. Based on this model, attempts to reduce surface states by surface passivation were made. Formation of the Si ICL structure on a regrown thin GaAs cap layer completely removed the anomalous side-gating effect. (c) 2006 American Vacuum Society.
  • Hideki Hasegawa, Seiya Kasai, Taketomo Sato, Tamotsu Hashizume
    IEICE TRANSACTIONS ON ELECTRONICS E89C 7 874 - 882 2006年07月 [査読有り][通常論文]
     
    With advent of the ubiquitous network era and due to recent progress of III-V nanotechnology, the present III-V heterostructure microelectronics will turn into what one might call III-V heterostructure nanoelectronics, and may open up a new future in much wider application areas than today, combining information technology, nanotechnology and biotechnology. Instead of the traditional top-down approach, new III-V heterostructure nanoelectronics will be formed on nanostructure networks formed by combination of top-down and bottom-up approaches. In addition to communication devices, emerging devices include high speed digital LSIs, various sensors, various smart-chips, quantum LSIs and quantum computation devices covering varieties of application areas. Ultra-low power quantum LSIs may become brains of smart chips and other nanospace systems. Achievements of new functions and higher performances and their on chip integration are key issues. Key processing issue remains to be understanding and control of nanostructure surfaces and interfaces in atomic scale.
  • Rui Jia, Hideki Hasegawa, Naoko Shiozaki, Seiya Kasai
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 24 4 2060 - 2068 2006年07月 [査読有り][通常論文]
     
    In order to establish feasibility of high density integration of gate-controlled GaAs nanodevices, this article investigates device interference in GaAs-based quantum wire transistors (QWRTrs) by using a side-gating test structure and attempts to suppress the observed anomalously large side-gating with surface passivation using a silicon interface control layer (Si ICL). QWRTrs were formed on AlGaAs/GaAs etched quantum wires (QWRs) and were controlled by nanometer sized Schottky wrap gates. A Schottky side gate was formed at a distance d(sg) from the QWR. When d(sg) was large, the QWRTr showed weak side gating which can be explained by the electrostatic side gating. However, when the side gates was placed close to the nanowire with d(sg) < 500 nm, anomalously large side gating started to take place which cannot be explained by the electrostatic side gating. On the basis of detailed measurements of side-gating behavior and side-gate leakage currents at various temperatures, the anomalous side gating was explained by a model in which occupation of deep traps at the back AlGaAs/GaAs interface of the QWR is modulated by tunneling injection of electrons from the side-gate edge resulting from strong Fermi level pinning by surface states. Based on this model, attempts to reduce surface states by surface passivation were made. Formation of the Si ICL structure on a regrown thin GaAs cap layer completely removed the anomalous side-gating effect. (c) 2006 American Vacuum Society.
  • Takahide Oya, Tetsuya Asai, Ryo Kagaya, Seiya Kasai, Yoshihito Amemiya
    International Congress Series 1291 213 - 216 2006年06月 [査読無し][通常論文]
     
    Neuromorphic computing based on single-electron circuit technology has become widely noticed because of the recent claim about its massively increased computational efficiency and its increasing relevance between computer technology and nanotechnology. Its impact will be strongly felt when single-electron circuits based on a fault- and noise-tolerant neural structure are able to operate in a room-temperature environment. To fabricate such robust single-electron devices, we investigated stochastic resonance in an ensemble of single-electron boxes. We here employ a single-electron transistor on a Schottky wrap-gate device, instead of a single-electron box, as a neuron, and examine statistical results of the network by numerical simulation. © 2006 Elsevier B.V. All rights reserved.
  • T Tamura, Tamai, I, S Kasai, T Sato, H Hasegawa, T Hashizume
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 4B 3614 - 3620 2006年04月 [査読無し][通常論文]
     
    The basic feasibility of constructing hexagonal binary decision diagram (BDD) quantum circuits on GaAs-based selectively grown (SG) nanowires was investigated front viewpoints of electrical connections through embedded nanowires and electrical-uniformity of devices formed on nanowires. For this, <(1) over bar 10 >- and < 510 >-oriented nanowires and hexagonal network structures combining these nanowires were formed on (001) GaAs substrates by selective molecular beam epitaxy (MBE) growth. The width and vertical position of the nanowires could be controlled by growth conditions for both <(1) over bar 10 >- and < 510 >-directions. By current-voltage (I-V) measurements, good electrical connection was confirmed at the node point where vertical alignment of embedded GaAs nanowire pieces was found to be important. SG quantum wire (QWR) switches formed on the nanowires showed good gate control over a wide temperature range with clear conductance quantization at low temperatures. Good device uniformities were obtained on the test chips, providing a good prospect for future integration. BDD node devices using SG QWR switches showed clear path switching characteristics. Estimated power-delay product values were very small, confirming the feasibility of ultra low-power operation of future circuits.
  • T Tamura, Tamai, I, S Kasai, T Sato, H Hasegawa, T Hashizume
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 4B 3614 - 3620 2006年04月 [査読無し][通常論文]
     
    The basic feasibility of constructing hexagonal binary decision diagram (BDD) quantum circuits on GaAs-based selectively grown (SG) nanowires was investigated front viewpoints of electrical connections through embedded nanowires and electrical-uniformity of devices formed on nanowires. For this, <(1) over bar 10 >- and < 510 >-oriented nanowires and hexagonal network structures combining these nanowires were formed on (001) GaAs substrates by selective molecular beam epitaxy (MBE) growth. The width and vertical position of the nanowires could be controlled by growth conditions for both <(1) over bar 10 >- and < 510 >-directions. By current-voltage (I-V) measurements, good electrical connection was confirmed at the node point where vertical alignment of embedded GaAs nanowire pieces was found to be important. SG quantum wire (QWR) switches formed on the nanowires showed good gate control over a wide temperature range with clear conductance quantization at low temperatures. Good device uniformities were obtained on the test chips, providing a good prospect for future integration. BDD node devices using SG QWR switches showed clear path switching characteristics. Estimated power-delay product values were very small, confirming the feasibility of ultra low-power operation of future circuits.
  • S Kasai, J Kotani, T Hashizume, H Hasegawa
    JOURNAL OF ELECTRONIC MATERIALS 35 4 568 - 575 2006年04月 [査読無し][通常論文]
     
    Gate control properties together with gate leakage currents in AlGaN/GaN heterostructure field effect transistors (HFETs) with nanometer-scale Schottky gates were investigated, focusing on the effects of AlGaN surfaces at the gate periphery. Fabricated AlGaN/GaN HFETs showed unexpectedly small gate length (L-G) dependence of transconductance, g(m). Comparing the transfer characteristics from theory and experiment, effective L-G values in the fabricated devices were found to be much longer than the geometrical size on the order of 100 nm, indicating the formation of virtual gates. Detailed analysis of the gate leakage current behaviors based on a thin surface barrier model showed the presence of a strong electric field at the gate periphery. The mechanism of the virtual gate formation was discussed based on the obtained nanometer-scale Schottky gate behaviors.
  • S Kasai, J Kotani, T Hashizume, H Hasegawa
    JOURNAL OF ELECTRONIC MATERIALS 35 4 568 - 575 2006年04月 [査読無し][通常論文]
     
    Gate control properties together with gate leakage currents in AlGaN/GaN heterostructure field effect transistors (HFETs) with nanometer-scale Schottky gates were investigated, focusing on the effects of AlGaN surfaces at the gate periphery. Fabricated AlGaN/GaN HFETs showed unexpectedly small gate length (L-G) dependence of transconductance, g(m). Comparing the transfer characteristics from theory and experiment, effective L-G values in the fabricated devices were found to be much longer than the geometrical size on the order of 100 nm, indicating the formation of virtual gates. Detailed analysis of the gate leakage current behaviors based on a thin surface barrier model showed the presence of a strong electric field at the gate periphery. The mechanism of the virtual gate formation was discussed based on the obtained nanometer-scale Schottky gate behaviors.
  • T Tamura, Tamai, I, S Kasai, T Sato, H Hasegawa, T Hashizume
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 4B 3614 - 3620 2006年04月 [査読無し][通常論文]
     
    The basic feasibility of constructing hexagonal binary decision diagram (BDD) quantum circuits on GaAs-based selectively grown (SG) nanowires was investigated front viewpoints of electrical connections through embedded nanowires and electrical-uniformity of devices formed on nanowires. For this, <(1) over bar 10 >- and < 510 >-oriented nanowires and hexagonal network structures combining these nanowires were formed on (001) GaAs substrates by selective molecular beam epitaxy (MBE) growth. The width and vertical position of the nanowires could be controlled by growth conditions for both <(1) over bar 10 >- and < 510 >-directions. By current-voltage (I-V) measurements, good electrical connection was confirmed at the node point where vertical alignment of embedded GaAs nanowire pieces was found to be important. SG quantum wire (QWR) switches formed on the nanowires showed good gate control over a wide temperature range with clear conductance quantization at low temperatures. Good device uniformities were obtained on the test chips, providing a good prospect for future integration. BDD node devices using SG QWR switches showed clear path switching characteristics. Estimated power-delay product values were very small, confirming the feasibility of ultra low-power operation of future circuits.
  • T Tamura, Tamai, I, S Kasai, T Sato, H Hasegawa, T Hashizume
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 45 4B 3614 - 3620 2006年04月 [査読無し][通常論文]
     
    The basic feasibility of constructing hexagonal binary decision diagram (BDD) quantum circuits on GaAs-based selectively grown (SG) nanowires was investigated front viewpoints of electrical connections through embedded nanowires and electrical-uniformity of devices formed on nanowires. For this, <(1) over bar 10 >- and < 510 >-oriented nanowires and hexagonal network structures combining these nanowires were formed on (001) GaAs substrates by selective molecular beam epitaxy (MBE) growth. The width and vertical position of the nanowires could be controlled by growth conditions for both <(1) over bar 10 >- and < 510 >-directions. By current-voltage (I-V) measurements, good electrical connection was confirmed at the node point where vertical alignment of embedded GaAs nanowire pieces was found to be important. SG quantum wire (QWR) switches formed on the nanowires showed good gate control over a wide temperature range with clear conductance quantization at low temperatures. Good device uniformities were obtained on the test chips, providing a good prospect for future integration. BDD node devices using SG QWR switches showed clear path switching characteristics. Estimated power-delay product values were very small, confirming the feasibility of ultra low-power operation of future circuits.
  • Tatsuya Nakamura, Yuji Abe, Seiya Kasai, Hideki Hasegawa, Tamotsu Hashizume
    SEVENTH INTERNATIONAL CONFERENCE ON NEW PHENOMENA IN MESOSCOPIC STRUCTURES AND FIFTH INTERNATIONAL CONFERENCE ON SURFACES AND INTERFACES OF MESOSCOPIC DEVICES, 2005 38 1 104 - + 2006年 [査読有り][通常論文]
     
    A new single electron (SE) binary-decision diagram (BDD) node device having a single quantum dot connected to three nanowire branches through tunnel barriers was fabricated using etched AlGaAs/GaAs nanowires and nanometer-sized Schottky wrap gates (WPGs), and their operation was characterized experimentally, for the hexagonal BDD quantum circuit. Fabricated devices showed clear and steep single electron pass switching by applying only an input voltage signal, which was completely different from switching properties in the previous SE BDD node devices composed of two single electron switches. As the possible switching mechanism, the correlation between the probabilities of tunnelling thorough a single quantum dot in exit branches was discussed.
  • Hideki Hasegawa, Taketomo Sato, Seiya Kasai, Boguslawa Adamowicz, Tamotsu Hashizume
    SOLAR ENERGY 80 6 629 - 644 2006年 [査読有り][通常論文]
     
    Characterization methods and fundamental aspects of surface/interface states and recombination process in Si and III-V materials are reviewed. Various measurement considerations are pointed out for the conventional metal-insulator-semiconductor (MIS) capacitance-voltage (C-P) method, a contactless C-V method, and the microscopic scanning tunneling spectroscopy (STS) method, and general features of surface states are discussed. Surface states are shown to have U-shaped distributions of donor acceptor continuum with a characteristic charge neutrality level, E-HO. Rigorous simulation of dynamics of surface recombination process has shown that the effective surface recombination velocity, S-eff, is not a constant of the surface, but its value changes by many orders of magnitude with the incident light intensity and the polarity and amount of fixed charge. From this, new methods of surface state characterization based on photoluminescence and cathodoluminescence are derived. Attempts to control surface states and Fermi level pinning at metal semiconductor interface and free surfaces of nano-structures are presented as efforts toward "nano-photovoltaics". (c) 2006 Elsevier Ltd. All rights reserved.
  • Hideki Hasegawa, Seiya Kasai, Taketomo Sato
    Frontiers in Electronics 41 421 - 436 2006年 [査読有り][通常論文]
     
    In an attempt to realize tiny "knowledge vehicles" called intelligent quantum (IQ) chips for use in the coming ubiquitous network society, this paper presents the present status and future prospects of ultra-small-size and ultra-low-power III-V quantum logic large scale integrated circuits based on a novel hexagonal binary-decision diagram (BDD) quantum circuit architecture. Here, quantum transport in path switching node devices formed on Ill-V semiconductor-based hexagonal nanowire networks is controlled by nanometer scale Schottky wrap gates (WPGs) to realize arbitrary combinational logic function. Feasibility of the approach is shown through fabrication of basic node devices and various small-scale circuits, and approaches for higher density integration and larger scale circuits are discussed.
  • Abdul Manaf Hashim, Seiya Kasai, Tamotsu Hashizume, Hideki Hasegawa
    2006 INTERNATIONAL RF AND MICROWAVE CONFERENCE, PROCEEDINGS 262 - + 2006年 [査読有り][通常論文]
     
    Interdigital-gated AlGaAs/GaAs high electron mobility transistor (HEMT) structure was used to investigate the interaction between the drifting carrier plasma waves and electromagnetic (EM) waves. It was shown theoretically that the interaction in the range from microwave to terahertz (THz) at room temperature should produce negative conductance characteristics when the carrier drift velocity slightly exceeds the phase velocity of EM waves. S-parameter reflection measurements were carried out at room temperature for a frequency range from 1 to 20 GHz and a drastic change in conductance was observed at 5GHz and 10GHz with the increase of drain-source voltage. Large conductance change over 1000 mS/mm was obtained and it showed a peak at a certain frequency. The peak position could be controlled by changing the pitch size of the interdigital gates. These characteristics can be used for high frequency applications such as high-speed switching devices although a feature size of our interdigital-gated HEMT device is much larger than conventional HEMT device.
  • Junji Kotani, Seiya Kasai, Hideki Hasegawa, Tamotsu Hashizume
    e-Journal of Surface Science and Nanotechnology 3 433 - 438 2005年12月09日 [査読無し][通常論文]
     
    Gate leakage currents in AlGaN/GaN HFETs were investigated by comparing experiments with computer simulations based on the thin surface barrier (TSB) model involving unintentional surface donors. Leakage currents in large area Schottky diodes were explained by the TSB model involving nitrogen vacancy related deep donors and oxygen shallow donors. On the other hand, in AlGaN/GaN HFETs with nanometer scale Schottky gates, gate leakage currents include an additional leakage component due to lateral electron injection through tunneling at the gate edge where the barrier thinning is mainly controlled by oxygen donors. By combining vertical and lateral tunneling components, experiments could be reproduced on computer. Lateral components may be responsible for current collapse. © 2005 The Surface Science Society of Japan.
  • Junji Kotani, Seiya Kasai, Hideki Hasegawa, Tamotsu Hashizume
    e-Journal of Surface Science and Nanotechnology 3 433 - 438 2005年12月09日 [査読無し][通常論文]
     
    Gate leakage currents in AlGaN/GaN HFETs were investigated by comparing experiments with computer simulations based on the thin surface barrier (TSB) model involving unintentional surface donors. Leakage currents in large area Schottky diodes were explained by the TSB model involving nitrogen vacancy related deep donors and oxygen shallow donors. On the other hand, in AlGaN/GaN HFETs with nanometer scale Schottky gates, gate leakage currents include an additional leakage component due to lateral electron injection through tunneling at the gate edge where the barrier thinning is mainly controlled by oxygen donors. By combining vertical and lateral tunneling components, experiments could be reproduced on computer. Lateral components may be responsible for current collapse. © 2005 The Surface Science Society of Japan.
  • Rui Jia, Nanako Shiozaki, Seiya Kasai, Hideki Hasegawa
    e-Journal of Surface Science and Nanotechnology 3 332 - 337 2005年11月27日 [査読無し][通常論文]
     
    For ultra-high-density integration of gate-controlled quantum devices, one possible phenomenon limiting the ultimate integration density is a side-gating effect which has not been properly addressed so far for nanodevices. The purpose of this paper is to attempt to remove the side-gating effect from the GaAs quantum wire transistors where we recently have found presence of anomalously large side-gating effect. We first present data on the side-gating and we explain its mechanism in terms of tunneling injection of electrons by field concentration at gate edges caused by Fermi level pinning. Then, we apply our Si interface control layer (Si ICL) passivation process to reduce the pinning. By applying the Si ICL technique via thin GaAs cap layer, the anomalously large side-gating was completely suppressed, and only electrostatic side-gating theoretically expected from the device structure remained. © 2005 The Surface Science Society of Japan.
  • Rui Jia, Nanako Shiozaki, Seiya Kasai, Hideki Hasegawa
    e-Journal of Surface Science and Nanotechnology 3 332 - 337 2005年11月27日 [査読無し][通常論文]
     
    For ultra-high-density integration of gate-controlled quantum devices, one possible phenomenon limiting the ultimate integration density is a side-gating effect which has not been properly addressed so far for nanodevices. The purpose of this paper is to attempt to remove the side-gating effect from the GaAs quantum wire transistors where we recently have found presence of anomalously large side-gating effect. We first present data on the side-gating and we explain its mechanism in terms of tunneling injection of electrons by field concentration at gate edges caused by Fermi level pinning. Then, we apply our Si interface control layer (Si ICL) passivation process to reduce the pinning. By applying the Si ICL technique via thin GaAs cap layer, the anomalously large side-gating was completely suppressed, and only electrostatic side-gating theoretically expected from the device structure remained. © 2005 The Surface Science Society of Japan.
  • 古川拓也, 木村健, 佐藤威友, 葛西誠也, 長谷川英機, 橋詰保
    電子情報通信学会技術研究報告. ED, 電子デバイス 105 326(ED2005 139-156) 39 - 42 一般社団法人電子情報通信学会 2005年10月07日 [査読無し][通常論文]
     
    Al_<0.24>Ga_<0.76>N/GaNヘテロ構造を用いたゲートレスHEMTを作製し、pH応答を含む各種溶液に対する応答特性を調べた。このためにHEMT表面をSiO_2膜で保護し、窓開けしたゲート部を溶液に曝した。溶液中ではデバイスは、飽和カロメル参照電極でゲート制御された。各種溶液中で、通常のショットキーゲートHEMTと同様のドレインI-V特性が得られ、溶液を介しての良好なゲート制御が観測された。線形領域でのドレイン電流は、溶液のpH値の変化に対して線形的に変化し、pH値に対する表面ポテンシャルの変化率として50.4mV/pHという理論値に近い値が得られた。エタノールやアセトンなどの有極性溶液の中でも、溶液の種類に応じて、ゲートレスHEMTのドレイン電流が変化を示し、溶液のダイポール測定の可能性を示した。
  • TAMAURA Takahiro, TAMAI Isao, KASAI Seiya, SATO Taketomo, HASEGAWA Hideki, HASHIZUME Tamotsu
    Extended abstracts of the ... Conference on Solid State Devices and Materials 2005 152 - 153 2005年09月13日 [査読無し][通常論文]
  • J Kotani, S Kasai, T Hashizume, H Hasegawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 23 4 1799 - 1807 2005年07月 [査読無し][通常論文]
     
    The gate leakage and gate control characteristics of AlGaN/GaN heterostructure field effect transistors (HFETs) were systematically investigated in an attempt to clarify possible effects of surface states. The experiments were compared to rigorous computer simulations. We observed large amounts of leakage currents in the Schottky diodes fabricated on the AlGaN epitaxial layers. By the calculation based on a thin surface barrier model in which the effects of surface defect donor were taken into account, this large leakage was well explained by enhancement of tunneling transport processes due to the barrier thinning associated with ionization of surface-defect donor. On the other hand, the analysis on the current-voltage characteristics for the nanometer-scale Schottky contacts on AlGaN/GaN HFETs, indicated additional lateral leakage components. The comparison of the gate control characteristics between experiment and calculation clearly showed that the effective lateral expansion of gate length significantly impeded the g,, enhancement by the reduction of geometrical gate length. This can be explained by the lateral electron tunneling process at the AlGaN surface stimulated by the pronounced gate leakage currents. Due to frequent tunneling transfer at the gate periphery, surface state occupancy near the gate becomes governed by the metal Fermi level, causing the dynamic surface state charging effects. This resulted in effective widening of the gate length, leading to degradation of gate control performance in AlGaN/GaN HFETs. (c) 2005 American Vacuum Society.
  • J Kotani, S Kasai, T Hashizume, H Hasegawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 23 4 1799 - 1807 2005年07月 [査読無し][通常論文]
     
    The gate leakage and gate control characteristics of AlGaN/GaN heterostructure field effect transistors (HFETs) were systematically investigated in an attempt to clarify possible effects of surface states. The experiments were compared to rigorous computer simulations. We observed large amounts of leakage currents in the Schottky diodes fabricated on the AlGaN epitaxial layers. By the calculation based on a thin surface barrier model in which the effects of surface defect donor were taken into account, this large leakage was well explained by enhancement of tunneling transport processes due to the barrier thinning associated with ionization of surface-defect donor. On the other hand, the analysis on the current-voltage characteristics for the nanometer-scale Schottky contacts on AlGaN/GaN HFETs, indicated additional lateral leakage components. The comparison of the gate control characteristics between experiment and calculation clearly showed that the effective lateral expansion of gate length significantly impeded the g,, enhancement by the reduction of geometrical gate length. This can be explained by the lateral electron tunneling process at the AlGaN surface stimulated by the pronounced gate leakage currents. Due to frequent tunneling transfer at the gate periphery, surface state occupancy near the gate becomes governed by the metal Fermi level, causing the dynamic surface state charging effects. This resulted in effective widening of the gate length, leading to degradation of gate control performance in AlGaN/GaN HFETs. (c) 2005 American Vacuum Society.
  • J Kotani, S Kasai, T Hashizume, H Hasegawa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 23 4 1799 - 1807 2005年07月 [査読無し][通常論文]
     
    The gate leakage and gate control characteristics of AlGaN/GaN heterostructure field effect transistors (HFETs) were systematically investigated in an attempt to clarify possible effects of surface states. The experiments were compared to rigorous computer simulations. We observed large amounts of leakage currents in the Schottky diodes fabricated on the AlGaN epitaxial layers. By the calculation based on a thin surface barrier model in which the effects of surface defect donor were taken into account, this large leakage was well explained by enhancement of tunneling transport processes due to the barrier thinning associated with ionization of surface-defect donor. On the other hand, the analysis on the current-voltage characteristics for the nanometer-scale Schottky contacts on AlGaN/GaN HFETs, indicated additional lateral leakage components. The comparison of the gate control characteristics between experiment and calculation clearly showed that the effective lateral expansion of gate length significantly impeded the g,, enhancement by the reduction of geometrical gate length. This can be explained by the lateral electron tunneling process at the AlGaN surface stimulated by the pronounced gate leakage currents. Due to frequent tunneling transfer at the gate periphery, surface state occupancy near the gate becomes governed by the metal Fermi level, causing the dynamic surface state charging effects. This resulted in effective widening of the gate length, leading to degradation of gate control performance in AlGaN/GaN HFETs. (c) 2005 American Vacuum Society.
  • JIA Rui, KASAI Seiya, SATO Taketomo, HASEGAWA Hideki
    電子情報通信学会技術研究報告. ED, 電子デバイス 105 110 31 - 36 一般社団法人電子情報通信学会 2005年06月03日 [査読無し][通常論文]
     
    Side-gating effects inhibiting the high-density integration of devices GaAs-based quantum wire transistors (QWRTrs) with nanosized Schottky gates controlling etched nanowires were investigated experimentally. Side-gating behaviors depended on the distance between the side-gate and nanowire edge d_<sg>, and when d_<sg><500nm and nanowire mesa etching was shallow, the large side-gating effect occurred, which could not be explained by the electrostatic effect. At the same time, anomalously large side-gate leakage current due to electron tunneling was observed. Here, we propose a model for the ...
  • AM Hashim, S Kasai, T Hashizume, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 44 4B 2729 - 2734 2005年04月 [査読無し][通常論文]
     
    To investigate the presence of interactions between surface plasma waves of carriers in a two-dimensional electron gas (2DEG) at AlGaAs/GaAs heterostructure and electromagnetic space harmonic slow waves, interdigital-gated high-electron-mobility transistor (HEMT) devices were fabricated, and their input admittances were measured in the microwave region of 1-15GHz. A large modulation of conductance, more than 1000 mS/mm, was observed. The conductance modulation was controlled by a drain-source voltage and showed a peak at a certain frequency whose position could be controlled by changing the pitch of the interdigital gates. The observed conductance and capacitance characteristics were in good agreement with the transverse magnetic (TM) mode analysis taking into account a nonuniform field distribution along the 2DEG channel. The result seems to prove the existence of surface plasma wave interactions even under the strongly collision-dominant situation in the microwave region and provides great hope for increased interactions at THz frequencies under nearly collision-free conditions.
  • AM Hashim, S Kasai, T Hashizume, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 44 4B 2729 - 2734 2005年04月 [査読無し][通常論文]
     
    To investigate the presence of interactions between surface plasma waves of carriers in a two-dimensional electron gas (2DEG) at AlGaAs/GaAs heterostructure and electromagnetic space harmonic slow waves, interdigital-gated high-electron-mobility transistor (HEMT) devices were fabricated, and their input admittances were measured in the microwave region of 1-15GHz. A large modulation of conductance, more than 1000 mS/mm, was observed. The conductance modulation was controlled by a drain-source voltage and showed a peak at a certain frequency whose position could be controlled by changing the pitch of the interdigital gates. The observed conductance and capacitance characteristics were in good agreement with the transverse magnetic (TM) mode analysis taking into account a nonuniform field distribution along the 2DEG channel. The result seems to prove the existence of surface plasma wave interactions even under the strongly collision-dominant situation in the microwave region and provides great hope for increased interactions at THz frequencies under nearly collision-free conditions.
  • AM Hashim, S Kasai, T Hashizume, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 44 4B 2729 - 2734 2005年04月 [査読無し][通常論文]
     
    To investigate the presence of interactions between surface plasma waves of carriers in a two-dimensional electron gas (2DEG) at AlGaAs/GaAs heterostructure and electromagnetic space harmonic slow waves, interdigital-gated high-electron-mobility transistor (HEMT) devices were fabricated, and their input admittances were measured in the microwave region of 1-15GHz. A large modulation of conductance, more than 1000 mS/mm, was observed. The conductance modulation was controlled by a drain-source voltage and showed a peak at a certain frequency whose position could be controlled by changing the pitch of the interdigital gates. The observed conductance and capacitance characteristics were in good agreement with the transverse magnetic (TM) mode analysis taking into account a nonuniform field distribution along the 2DEG channel. The result seems to prove the existence of surface plasma wave interactions even under the strongly collision-dominant situation in the microwave region and provides great hope for increased interactions at THz frequencies under nearly collision-free conditions.
  • 田村隆博, 湯元美樹, 玉井功, 葛西誠也, 佐藤威友, 長谷川英機
    電子情報通信学会技術研究報告 104 624(SDM2004 222-228) 19 - 24 一般社団法人電子情報通信学会 2005年01月20日 [査読無し][通常論文]
     
    ヘキサゴナル二分決定グラフ(BDD)量子集積回路の実現に向け、MBE選択成長量子細線(SG QWR)ネットワーク技術を適用した量子細線スイッチおよびBDD量子節点デバイスの試作と評価を行った。作製したSG QWRスイッチは、<-011>、<510>両方向とも室温から低温まで通常のFETと同様な動作を示し、低温においては明瞭なコンダクタンスステップが確認された。詳細なゲート制御性を評価するためシュブニコフ-ド-ハース振動測定を行った結果、作製したSG QWRスイッチにおいてはショットキーラップゲート(WPG)の制御により良好なゲート制御性が得られた。2つの方向の細線を組合わせたY字型のBDD節点デバイスを試作し、明確なパススイッチング動作を実現した。また、デバイスのスイッチング速度と電力遅延時間積(PDP)の見積もりを行い、スイッチング速度τ=50ps、PDP=10^<-18>Jを得た。
  • JAPANESE JOURNAL OF APPLIED PHYSICS PART 1 44 (4B): 2729-2734 2005年 [査読無し][通常論文]
  • R Jia, S Kasai, H Hasegawa
    COMPOUND SEMICONDUCTORS 2004, PROCEEDINGS 184 21 - 26 2005年 [査読無し][通常論文]
     
    Investigation of gate control and current-voltage (I-V) characteristics of nanometer scale Schottky electrodes is in an attempt to clarify the possible effects of surface states. HEMT devices having nanometer-sized Schottky gate showed a gate controllability so that the effective gate length was extended, as well as Schottky gate's anomalous I-V characteristics different from the prediction of thermionic emission theory. QWRTrs having an additional side gate exhibited large side-gating effect that was much larger than that by side gate depletion with anomalous side gate leakage current. The origin of obtained gate control anomalies is understood by the high-density surface state charging in gate peripheries that produces strong electric field and induces excess surface state charging by carrier injection from the gate.
  • M Yumoto, S Kasai, H Hasegawa
    COMPOUND SEMICONDUCTORS 2004, PROCEEDINGS 184 213 - 216 2005年 [査読無し][通常論文]
     
    This paper investigates the basic speed-power performance of Schottky wrap gate (WPG) controlled GaAs quantum wire (QWR) switches for hexagonal BDD quantum circuits. The estimated power-delay products (PDPs) of the switches were less than 10(-20) J at low temperatures, being smaller than those of the latest Si CMOSFETs. Direct microwave measurements and equivalent circuit analysis confirmed capability of GHz clock operation.
  • R Jia, S Kasai, H Hasegawa
    COMPOUND SEMICONDUCTORS 2004, PROCEEDINGS 184 21 - 26 2005年 [査読無し][通常論文]
     
    Investigation of gate control and current-voltage (I-V) characteristics of nanometer scale Schottky electrodes is in an attempt to clarify the possible effects of surface states. HEMT devices having nanometer-sized Schottky gate showed a gate controllability so that the effective gate length was extended, as well as Schottky gate's anomalous I-V characteristics different from the prediction of thermionic emission theory. QWRTrs having an additional side gate exhibited large side-gating effect that was much larger than that by side gate depletion with anomalous side gate leakage current. The origin of obtained gate control anomalies is understood by the high-density surface state charging in gate peripheries that produces strong electric field and induces excess surface state charging by carrier injection from the gate.
  • M Yumoto, S Kasai, H Hasegawa
    COMPOUND SEMICONDUCTORS 2004, PROCEEDINGS 184 213 - 216 2005年 [査読無し][通常論文]
     
    This paper investigates the basic speed-power performance of Schottky wrap gate (WPG) controlled GaAs quantum wire (QWR) switches for hexagonal BDD quantum circuits. The estimated power-delay products (PDPs) of the switches were less than 10(-20) J at low temperatures, being smaller than those of the latest Si CMOSFETs. Direct microwave measurements and equivalent circuit analysis confirmed capability of GHz clock operation.
  • 量子細線ネットワークと論理回路応用
    応用物理 第74巻、第3号、p.0320-0326 2005年 [査読無し][通常論文]
  • H Hasegawa, S Kasai
    2005 International Conference on MEMS, NANO and Smart Systems, Proceedings 399 - 399 2005年 [査読有り][通常論文]
  • H Hasegawa, S Kasai, T Sato
    IEICE TRANSACTIONS ON ELECTRONICS E87C 11 1757 - 1768 2004年11月 [査読無し][通常論文]
     
    A new approach for ultra-low-power LSIs based on quantum devices is presented and its present status and critical issues are discussed with a brief background review on the semiconductor nanotechnology. It is a hexagonal binary decision diagram (BDD) quantum logic circuit approach suitable for realization of ultra-low-power logic/mernory circuits to be used in new applications such as intelligent quantum (IQ) chips embedded in the ubiquitous network environment. The basic concept of the approach, circuit examples showing its feasibility, growth of high density nanostructure networks by molecular beam epitaxy (NIBE) for future LSI implementation, and the key processing issues including the device isolation issue are addressed.
  • H Hasegawa, S Kasai, T Sato
    IEICE TRANSACTIONS ON ELECTRONICS E87C 11 1757 - 1768 2004年11月 [査読無し][通常論文]
     
    A new approach for ultra-low-power LSIs based on quantum devices is presented and its present status and critical issues are discussed with a brief background review on the semiconductor nanotechnology. It is a hexagonal binary decision diagram (BDD) quantum logic circuit approach suitable for realization of ultra-low-power logic/mernory circuits to be used in new applications such as intelligent quantum (IQ) chips embedded in the ubiquitous network environment. The basic concept of the approach, circuit examples showing its feasibility, growth of high density nanostructure networks by molecular beam epitaxy (NIBE) for future LSI implementation, and the key processing issues including the device isolation issue are addressed.
  • Design and implementation of ultra-small and ultra-low-power digital systems on GaAs-based hexagonal nanowire networks utlizing an hexagonal BDD quantum circuit approach
    ECS PROCEEDINGS VOLUME 2004-13: 125-146 2004年 [査読無し][通常論文]
  • KASAI S.
    ECS PROCEEDINGS VOLUME 2004-13: 125-146 125 - 146 2004年 [査読無し][通常論文]
  • T Kakumu, F Ishikawa, S Kasai, T Hashizume, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 42 4B 2230 - 2236 2003年04月 [査読無し][通常論文]
     
    For the <001>-oriented In0.5Ga0.5P/GaAs beterostructure grown by gas source molecular beam epitaxy (GSMBE) using tertiarybutylphosphine (TBP), presence of the natural ordering of group III atoms and its effect on heterointerface properties are investigated for the first time. Using in situ reflection high energy electron diffraction (RHEED) observation and photoluminescence (PL) measurements, growth temperature and growth sequence were optimized to grow high-quality InGaP layers with defect-free heterointerfaces. By PL measurements on <001>- and <311>-oriented samples simultaneously grown under the same growth conditions, existence of natural ordering in <001>-oriented samples was found. The so-called long-range order parameter, eta, of the InGaP layer increased with increase of the TBP flow rate and with decrease of the growth rate. 77 could be changed in the range of 0.06-0.29 by changing the growth conditions, corresponding to the band gap change of 43 meV. The valence band offset (DeltaE(V)) measured by in situ XPS method was 0.29 eV and was independent of the value of eta. The change of conduction band offset (DeltaE(C)) due to ordering caused a corresponding change in the sheet carrier density of two-dimensional electron gas at the heterointerface. No significant contribution from piezoelectric or spontaneous polarization was seen up to q = 0.29.
  • H Hasegawa, T Muranaka, S Kasai, T Hashizume
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 42 4B 2375 - 2381 2003年04月 [査読無し][通常論文]
     
    Attempts were made to fabricate AlGaN/GaN quantum nanostructures by dry etching, and to assess etching damage through characterization of their electrical properties. An electron-cyclotron-resonance-assisted reactive ion beam,etching (ECR-RIBE) process using a CH4-based gas mixture was applied to AlGaN/GaN heterostructure wafers, and the process was characterized and optimized using in situ X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM) and photoluminescence (PL) measurements. Addition of nitrogen gas to the standard gas mixture of CH4/H-2/Ar was found to be extremely effective in improving the etching characteristics, etched surface morphology and surface stoichiometry, and in preventing accumulation of Ga and Al metallic clusters. After testing the fabrication feasibility of various nanostructures, AlGaN/GaN quantum wire (QWR) structures of various widths were fabricated, and their electrical characteristics were investigated to detect etching damage. Clear Shubnikov-de Haas (SdH) oscillations were observed at 1.6 K in the QWR structures under strong magnetic fields. A nonlinear Landau plot indicated the presence of a one-dimensional confinement potential with a subband energy spacing of 1.4 meV. The measured wire conductance can be well explained by a simple theory, taking account of the sidewall depletion of 23 nm due to Fermi level pinning. No clear changes in sheet carrier concentration and mobility due to plasma damage were detected.
  • T Kakumu, F Ishikawa, S Kasai, T Hashizume, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 42 4B 2230 - 2236 2003年04月 [査読無し][通常論文]
     
    For the <001>-oriented In0.5Ga0.5P/GaAs beterostructure grown by gas source molecular beam epitaxy (GSMBE) using tertiarybutylphosphine (TBP), presence of the natural ordering of group III atoms and its effect on heterointerface properties are investigated for the first time. Using in situ reflection high energy electron diffraction (RHEED) observation and photoluminescence (PL) measurements, growth temperature and growth sequence were optimized to grow high-quality InGaP layers with defect-free heterointerfaces. By PL measurements on <001>- and <311>-oriented samples simultaneously grown under the same growth conditions, existence of natural ordering in <001>-oriented samples was found. The so-called long-range order parameter, eta, of the InGaP layer increased with increase of the TBP flow rate and with decrease of the growth rate. 77 could be changed in the range of 0.06-0.29 by changing the growth conditions, corresponding to the band gap change of 43 meV. The valence band offset (DeltaE(V)) measured by in situ XPS method was 0.29 eV and was independent of the value of eta. The change of conduction band offset (DeltaE(C)) due to ordering caused a corresponding change in the sheet carrier density of two-dimensional electron gas at the heterointerface. No significant contribution from piezoelectric or spontaneous polarization was seen up to q = 0.29.
  • H Hasegawa, T Muranaka, S Kasai, T Hashizume
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 42 4B 2375 - 2381 2003年04月 [査読無し][通常論文]
     
    Attempts were made to fabricate AlGaN/GaN quantum nanostructures by dry etching, and to assess etching damage through characterization of their electrical properties. An electron-cyclotron-resonance-assisted reactive ion beam,etching (ECR-RIBE) process using a CH4-based gas mixture was applied to AlGaN/GaN heterostructure wafers, and the process was characterized and optimized using in situ X-ray photoelectron spectroscopy (XPS), scanning electron microscopy (SEM), atomic force microscopy (AFM) and photoluminescence (PL) measurements. Addition of nitrogen gas to the standard gas mixture of CH4/H-2/Ar was found to be extremely effective in improving the etching characteristics, etched surface morphology and surface stoichiometry, and in preventing accumulation of Ga and Al metallic clusters. After testing the fabrication feasibility of various nanostructures, AlGaN/GaN quantum wire (QWR) structures of various widths were fabricated, and their electrical characteristics were investigated to detect etching damage. Clear Shubnikov-de Haas (SdH) oscillations were observed at 1.6 K in the QWR structures under strong magnetic fields. A nonlinear Landau plot indicated the presence of a one-dimensional confinement potential with a subband energy spacing of 1.4 meV. The measured wire conductance can be well explained by a simple theory, taking account of the sidewall depletion of 23 nm due to Fermi level pinning. No clear changes in sheet carrier concentration and mobility due to plasma damage were detected.
  • Seiya Kasai, Miki Yumoto, Hideki Hasegawa
    Solid-State Electronics 47 2 199 - 204 2003年02月 [査読無し][通常論文]
     
    Feasibility of a novel hexagonal binary decision diagram (BDD) quantum circuit approach based on Schottky wrap gate (WPG) control of GaAs/AlGaAs hexagonal nanowire network has been demonstrated through fabrication of half adders and full adders. Quantum BDD node devices were designed and realized utilizing WPG-controlled quantum wire (QWR) and single electron switches. BDD half sum and carry elements of a half adder were fabricated by integrating the WPG BDD node devices and they operated correctly through either quantum transport at low temperature or many electron classical transport at room temperature. Successful design of hexagonal BDD full adders for arbitrary bits on a hexagonal network without nanowire crossover and fabrication of QWR-based BDD 2-bit full adder on the AlGaAs/GaAs etched hexagonal nanowire network with node density of 107 cm-2 clearly indicated the capability of the present approach for large scale quantum device integration. © 2002 Elsevier Science Ltd. All rights reserved.
  • A Kameda, S Kasai, T Sato, H Hasegawa
    SOLID-STATE ELECTRONICS 47 2 323 - 331 2003年02月 [査読無し][通常論文]
     
    Effects of surface states on gate control characteristics of nano-meter scale Schottky gates formed on GaAs are investigated both theoretically and experimentally. Special sample structures are used. They are metal-insulator-semiconductor structures having nano-meter scale Schottky dot arrays for capacitance-voltage (C-V) measurements and metal-semi-conductor field effect transistor structures having nano-meter scale grating Schottky gates for current-voltage (I-V) measurements. Measured C-V and I-V results are compared with results of theoretical calculation on a computer. The effects of surface states are found to be two-fold. Namely, it is shown that control characteristics of nano-meter scale Schottky gates are strongly degraded by the presence of Fermi level pinning caused by surface states on the free surface surrounding the gate. It is also shown that a significant amount of gate-induced lateral charging of surface states takes place around the gate periphery, effectively increasing the gate dimension. These results indicate the critical importance of control of surface states in nano-devices using nano-meter scale Schottky gates. (C) 2002 Elsevier Science Ltd. All rights reserved.
  • S Kasai, M Yumoto, H Hasegawa
    SOLID-STATE ELECTRONICS 47 2 199 - 204 2003年02月 [査読無し][通常論文]
     
    Feasibility of a novel hexagonal binary decision diagram (BDD) quantum circuit approach based on Schottky wrap gate (WPG) control of GaAs/AlGaAs hexagonal nanowire network has been demonstrated through fabrication of half adders and full adders. Quantum BDD node devices were designed and realized utilizing WPG-controlled quantum wire (QWR) and single electron switches. BDD half sum and carry elements of a half adder were fabricated by integrating the WPG BDD node devices and they operated correctly through either quantum transport at low temperature or many electron classical transport at room temperature. Successful design of hexagonal BDD full adders for arbitrary bits on a hexagonal network without nanowire crossover and fabrication of QWR-based BDD 2-bit full adder on the AlGaAs/GaAs etched hexagonal nanowire network with node density of 10(7) cm(-2) clearly indicated the capability of the present approach for large scale quantum device integration. (C) 2002 Elsevier Science Ltd. All rights reserved.
  • A Kameda, S Kasai, T Sato, H Hasegawa
    SOLID-STATE ELECTRONICS 47 2 323 - 331 2003年02月 [査読無し][通常論文]
     
    Effects of surface states on gate control characteristics of nano-meter scale Schottky gates formed on GaAs are investigated both theoretically and experimentally. Special sample structures are used. They are metal-insulator-semiconductor structures having nano-meter scale Schottky dot arrays for capacitance-voltage (C-V) measurements and metal-semi-conductor field effect transistor structures having nano-meter scale grating Schottky gates for current-voltage (I-V) measurements. Measured C-V and I-V results are compared with results of theoretical calculation on a computer. The effects of surface states are found to be two-fold. Namely, it is shown that control characteristics of nano-meter scale Schottky gates are strongly degraded by the presence of Fermi level pinning caused by surface states on the free surface surrounding the gate. It is also shown that a significant amount of gate-induced lateral charging of surface states takes place around the gate periphery, effectively increasing the gate dimension. These results indicate the critical importance of control of surface states in nano-devices using nano-meter scale Schottky gates. (C) 2002 Elsevier Science Ltd. All rights reserved.
  • S Kasai, WH Han, M Yumoto, H Hasegawa
    2ND INTERNATIONAL CONFERENCE ON SEMICONDUCTOR QUANTUM DOTS Volume 0, Issue 4, pp. 1329-1332 1329 - 1332 2003年 [査読無し][通常論文]
     
    THz responses of Schottky wrap gate (WPG)-controlled quantum dots were investigated. Normal incidence THz irradiation on single-dot and multi-dot devices with a CH3OH laser (2.54 THz) changed the conductance behavior and produced an additional conductance peak in the I-V characteristics of WPG single electron transistors (SETs) at 5-20 K. The effect depended on the THz electric field polarization. The observed behavior was explained by photon assisted tunneling based on the Tien-Gordon theory.
  • Solid-State Electronics vol. 47, pp.323-331 2003年 [査読無し][通常論文]
  • S Kasai, WH Han, M Yumoto, H Hasegawa
    2ND INTERNATIONAL CONFERENCE ON SEMICONDUCTOR QUANTUM DOTS Volume 0, Issue 4, p 1329-1332 1329 - 1332 2003年 [査読無し][通常論文]
     
    THz responses of Schottky wrap gate (WPG)-controlled quantum dots were investigated. Normal incidence THz irradiation on single-dot and multi-dot devices with a CH3OH laser (2.54 THz) changed the conductance behavior and produced an additional conductance peak in the I-V characteristics of WPG single electron transistors (SETs) at 5-20 K. The effect depended on the THz electric field polarization. The observed behavior was explained by photon assisted tunneling based on the Tien-Gordon theory.
  • S Kasai, WH Han, M Yumoto, H Hasegawa
    2ND INTERNATIONAL CONFERENCE ON SEMICONDUCTOR QUANTUM DOTS vol. 0, pp.1329-1332 1329 - 1332 2003年 [査読無し][通常論文]
     
    THz responses of Schottky wrap gate (WPG)-controlled quantum dots were investigated. Normal incidence THz irradiation on single-dot and multi-dot devices with a CH3OH laser (2.54 THz) changed the conductance behavior and produced an additional conductance peak in the I-V characteristics of WPG single electron transistors (SETs) at 5-20 K. The effect depended on the THz electric field polarization. The observed behavior was explained by photon assisted tunneling based on the Tien-Gordon theory.
  • Seiya Kasai, Taketomo Sato, Hideki Hasegawa
    2003 International Semiconductor Device Research Symposium, ISDRS 2003 - Proceedings 482 - 483 2003年 [査読有り][通常論文]
     
    Explosive growth of intemets and wireless telephones starting in the late 20th century has opened up prospects towards an advanced ubiquitous network society. This also opens up new directions in the device research in addition to the continued efforts of scale down of Si CMOS device along the roadmap.
  • S. Kasai, M. Yumoto, T. Tamura, H. Hasegawa
    Device Research Conference - Conference Digest, DRC 2003- 97 - 98 2003年 [査読有り][通常論文]
     
    In this paper investigate the feasibility of design and fabrication of digital processors based on our hexagonal BDD quantum circuit approach. Circuits were fabricated on AlGaAs/GaAs etched nanowires, using EB lithography and wet chemical etching, and their characteristics were evaluated.
  • H Hasegawa, S Kasai
    QUANTUM SENSING: EVOLUTION AND REVOLUTION FROM PAST TO FUTURE 4999 96 - 105 2003年 [査読有り][通常論文]
     
    The present status and future prospects of compound semiconductor quantum nanostructures for sensing terahertz (THz) signals a re reviewed. Various THz detectors reported in recent publications are reviewed first. They include infrared photodetectors based on quantum wells, superlattices and quantum dots, resonant tunneling diodes, single electron transistors and plasma resonators using,high mobility electron transistor structures. Then, a novel approach by the authors utilizing planar arrays of quantum dots controlled by nano-scale Schottky wrap gates is presented and discussed. It is based on photon assisted resonant tunneling of single electrons. The novel device structure allows normal incidence of THz radiation as well as high density planar integration. A large responsivity of 0.3 A/W was obtained at 20K for 2.5 THz laser beam.
  • J Chao, S Kasai, H Hasegawa
    2003 INTERNATIONAL CONFERENCE INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS 429 - 432 2003年 [査読有り][通常論文]
     
    Gate-control characteristics of photoluminescence (PL) were investigated for InGaAs quantum well (QW) and ridge quantum wire (QWR) structures grown by molecular beam epitaxy (MBE). Semi-transparent Au Schottky gates were formed on sample surfaces. Large modulations of PL intensity were seen for both QWR and QWs with different gate-voltage dependence. The results were explained in terms of electric field sweeping of photo-generated carriers.
  • YG Xie, K Takahashi, H Takahashi, JA Chao, S Kasai, H Hasegawa
    ELECTRONICS AND COMMUNICATIONS IN JAPAN PART II-ELECTRONICS 85 10 17 - 28 2002年10月 [査読有り][通常論文]
     
    A novel method for surface passivation of epitaxial multilayer structures for InP-based high-speed devices by an ultrathin silicon interface control layer (Si ICL) is discussed. Theoretical design and optimization of the surface passivation structure with and without an InGaAs cap layer is performed by taking account of the strain effect and quantized states in the Si ICL. Then the formation process of a SiNx/Si ICL structure utilizing a novel partial-nitridation technique is optimized. It is clarified that the InGaAs cap layer is important for Si ICL-based surface passivation on the InP-based materials. Planar metal-insulator-semiconductor (MIS) diodes are studied to characterize the insulator-semiconductor (I-S) interface fabricated on semi-insulating InP substrates, also showing that the Si ICL method is useful for the surface passivation of InP-based multilayer structures. (C) 2002 Wiley Periodicals, Inc.
  • M Yumoto, S Kasai, H Hasegawa
    MICROELECTRONIC ENGINEERING 63 1-3 287 - 291 2002年08月 [査読無し][通常論文]
     
    A novel approach for quantum logic circuits is described. In this approach, graph-based circuits are directly constructed on nanowire networks and controlled by multiple quantum wire branch switches. Potential advantages of the approach are briefly discussed. A novel GaAs branch switch using a nano-scale Schottky wrap gates (WPGs) on etched AlGaAs/GaAs nanowire was fabricated and its basic control characteristics were investigated. WPG realizes tight gate control of quantum transport near wire pinch off and shows clear conductance quantization at low temperatures. Simple circuits for BDD path switching and AND logic function were then fabricated, and they showed correct operation at low temperature. They could be operated at room temperature by increasing power consumption. (C) 2002 Elsevier Science B.V. All rights reserved.
  • M Yumoto, S Kasai, H Hasegawa
    MICROELECTRONIC ENGINEERING 63 1-3 287 - 291 2002年08月 [査読無し][通常論文]
     
    A novel approach for quantum logic circuits is described. In this approach, graph-based circuits are directly constructed on nanowire networks and controlled by multiple quantum wire branch switches. Potential advantages of the approach are briefly discussed. A novel GaAs branch switch using a nano-scale Schottky wrap gates (WPGs) on etched AlGaAs/GaAs nanowire was fabricated and its basic control characteristics were investigated. WPG realizes tight gate control of quantum transport near wire pinch off and shows clear conductance quantization at low temperatures. Simple circuits for BDD path switching and AND logic function were then fabricated, and they showed correct operation at low temperature. They could be operated at room temperature by increasing power consumption. (C) 2002 Elsevier Science B.V. All rights reserved.
  • S Kasai, H Hasegawa
    IEEE ELECTRON DEVICE LETTERS 23 8 446 - 448 2002年08月 [査読無し][通常論文]
     
    A novel hexagonal binary-decision-diagram (BDD) quantum logic circuit approach for III-V quantum large scale integrated circuits is proposed and its basic feasibility is demonstrated. In this approach, a III-V hexagonal nanowire network is controlled by Schottky wrap gates (WPGs) to implement BDD logic architecture by path switching. A novel single electron BDD OR logic circuit is successfully fabricated on a GaAs nanowire hexagon and correct circuit operation has been confirmed from 1.5 K to 120 K, showing that the WPG BDD circuit can operate over a wide temperature range by trading off between the power-delay product and the operation temperature.
  • Yumoto Miki, Kasai Seiya, Hasegawa Hideki
    Applied Surface Science 190 1 242 - 246 Elsevier 2002年05月08日 
    A novel approach for quantum logic circuits is described. In this approach, graph-based circuits are directly constructed on nanowire networks and controlled by multiple quantum wire branch switches. Potential advantages of the approach are briefly discussed. A novel GaAs branch switch using a nano-scale Schottky wrap gates (WPGs) on etched AlGaAs/GaAs nanowire was fabricated and its basic control characteristics were investigated. WPG realizes tight gate control of quantum transport near wire pinch off and shows clear conductance quantization at low temperatures. Simple circuits for BDD path switching and AND logic function were then fabricated, and they showed correct operation at low temperature. They could be operated at room temperature by increasing power consumption.
  • ZW Fu, S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 190 1-4 298 - 301 2002年05月 [査読無し][通常論文]
     
    In order to investigate the effectiveness of a novel oxide-free surface passivation approach for InP, using an ultrathin silicon interface control layer (Si ICL), gated photoluminescence characteristics of the Si3N4/Si ICL/n-InP metal-semi-conductor-insulator (MIS) structure were studied at room temperature. As compared with gated PL spectra of Si3N4/n-InP MIS without Si ICL, PL intensities of the sample with Si ICL were much more strongly modulated by the gate voltage. The interface state density distribution was estimated by an optical analog of the Terman's C-V analysis and a good agreement with the C-V analysis was obtained. The result indicates complete removal of Fermi level pinning over the entire bandgap in the novel oxide-free MIS structure. (C) 2002 Elsevier Science B.V. All rights reserved.
  • N Negoro, S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 190 1-4 269 - 274 2002年05月 [査読無し][通常論文]
     
    Microscopic topological and spectroscopic properties of MBE-grown GaAs c(4 x 4) surfaces without and with monolayer Si deposition were investigated by the scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS). Empty state STM images on as-grown surface showed bright and dark cells, and they exhibited strong correlation with the spatial distribution of normal and anomalous conductance gaps of the STS spectra. Bias dependent STM images indicated presence of pinning areas with continuous space and energy distribution of surface gap states. By deposition of monolayer Si, dark areas reduced a great deal and the rate of finding normal STS spectra increased, indicating large reduction of surface states. (C) 2002 Elsevier Science B.V. All rights reserved.
  • M Yumoto, S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 190 1-4 242 - 246 2002年05月 [査読無し][通常論文]
     
    Gate control characteristics of GaAs-based quantum wire transistors (QWRTrs) controlled by a nanometer-scale Schottky wrap gate (WPG) are investigated theoretically and experimentally. Gate bias dependence of the effective wire width of fabricated WPG QWRTrs determined theoretically as well as experimentally from Landau plots showed that the nanometer-scale WPG controls the potential very tightly near channel pinch-off and that the pinch-off threshold voltage is strongly dependent on the gate length, L-G, when L-G is shorter than 400 nm. The theory based on the three-dimensional (3D) potential simulation pointed out that Fermi level pinning on the semiconductor surface around the WPGs strongly affects the gate controllability in the nanometer-scale Schottky WPG structure. (C) 2002 Elsevier Science B.V. All rights reserved.
  • N Negoro, S Kasai, H Hasegawa
    Applied Surface Science 190 1-4 269 - 274 2002年05月 [査読無し][通常論文]
     
    Microscopic topological and spectroscopic properties of MBE-grown GaAs c(4 x 4) surfaces without and with monolayer Si deposition were investigated by the scanning tunneling microscopy (STM) and scanning tunneling spectroscopy (STS). Empty state STM images on as-grown surface showed bright and dark cells, and they exhibited strong correlation with the spatial distribution of normal and anomalous conductance gaps of the STS spectra. Bias dependent STM images indicated presence of pinning areas with continuous space and energy distribution of surface gap states. By deposition of monolayer Si, dark areas reduced a great deal and the rate of finding normal STS spectra increased, indicating large reduction of surface states. (C) 2002 Elsevier Science B.V. All rights reserved.
  • ZW Fu, S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 190 1-4 298 - 301 2002年05月 [査読無し][通常論文]
     
    In order to investigate the effectiveness of a novel oxide-free surface passivation approach for InP, using an ultrathin silicon interface control layer (Si ICL), gated photoluminescence characteristics of the Si3N4/Si ICL/n-InP metal-semi-conductor-insulator (MIS) structure were studied at room temperature. As compared with gated PL spectra of Si3N4/n-InP MIS without Si ICL, PL intensities of the sample with Si ICL were much more strongly modulated by the gate voltage. The interface state density distribution was estimated by an optical analog of the Terman's C-V analysis and a good agreement with the C-V analysis was obtained. The result indicates complete removal of Fermi level pinning over the entire bandgap in the novel oxide-free MIS structure. (C) 2002 Elsevier Science B.V. All rights reserved.
  • S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 190 1-4 176 - 183 2002年05月 [査読無し][通常論文]
     
    The concept, the present status, key issues and future prospects of a novel hexagonal binary decision diagram (BDD) quantum circuit approach for III-V quantum large-scale integrated circuits (QLSIs) are presented and discussed. In this approach, the BDD logic circuits are implemented on III-V semiconductor-based hexagonal nanowire networks controlled by nanoscale Schottky gates. The hexagonal BDD QLSIs can operate at delay-power products near the quantum limit in the quantum regime as well as in the many-electron classical regime. To demonstrate the feasibility of the present approach, GaAs Schottky wrap gate (WPG)-based single-electron BDD node devices and their integrated circuits were fabricated and their proper operations were confirmed. Selectively grown InGaAs sub-10 nm quantum wires and their hexagonal networks have been investigated to form high-density hexagonal BDD QLSIs operating in the quantum regime at room temperature. (C) 2002 Elsevier Science B.V. All rights reserved.
  • M Yumoto, S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 190 1-4 242 - 246 2002年05月 [査読無し][通常論文]
     
    Gate control characteristics of GaAs-based quantum wire transistors (QWRTrs) controlled by a nanometer-scale Schottky wrap gate (WPG) are investigated theoretically and experimentally. Gate bias dependence of the effective wire width of fabricated WPG QWRTrs determined theoretically as well as experimentally from Landau plots showed that the nanometer-scale WPG controls the potential very tightly near channel pinch-off and that the pinch-off threshold voltage is strongly dependent on the gate length, L-G, when L-G is shorter than 400 nm. The theory based on the three-dimensional (3D) potential simulation pointed out that Fermi level pinning on the semiconductor surface around the WPGs strongly affects the gate controllability in the nanometer-scale Schottky WPG structure. (C) 2002 Elsevier Science B.V. All rights reserved.
  • M Yumoto, S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 41 4B 2671 - 2674 2002年04月 [査読無し][通常論文]
     
    A novel binary decision diagram (BDD) node device based on wrap-gate (WPG) control of AlGaAs/GaAs nanowires is described and fabricated, and its basic operation is characterized. The node device consists of one entry-nanowire branch and two exit-nanowire branches where each of two exit-branches is switched by a Schottky WPG in a complimentary fashion so as to realize path switching for electrons. Basic branch switches as well as BDD node devices were fabricated on AlGaAs/GaAs nanowires formed by electron beam lithography and wet chemical etching of molecular beam epitaxy (MBE)-grown heterostructures. A detailed analysis of gate control characteristics was carried out by magneto tran sport measurements. A three-dimensional potential simulation showed that Fermi level pinning on the semiconductor free surface should be carefully taken into consideration for accurate device design. The branch-switch exhibited excellent gate control from low temperatures up to room temperature. showing clear conductance quantization at low temperatures, The fabricated BDD node device realized clear path switching from low temperatures up to room temperature.
  • M Endo, Z Jin, S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 41 4B 2689 - 2693 2002年04月 [査読無し][通常論文]
     
    The basic etching characteristics of electron cyclotron resonance reactive ion beam etching (ECR-RIBE) of GaN and AlGaN/GaN using methane-based mixtures have been studied in view of application to nanostructure fabrication. GaN could be etched by using a gas mixture of CH4/H-2/Ar at a rate of about 10 nm/min, which is suitable for nanostructure fabrication. The etching process was also applicable to the standard AlGaN/GaN heterostructure. Etching along <1100> and <2110> stripe patterns revealed {0111} and {1121} sidewall facets, respectively, indicating that the etching is a facet-revealing process, being dominated by chemical reactions with low physical damage. However, the etching depth showed anomalous saturation at 400-500 nm, and the toughness of the surface increased with time. An in situ X-ray photoelectron spectroscopy (XPS) study detected the formation of Ga droplets. By adding N-2 into the gas mixture, Ga droplet formation was suppressed, etch depth saturation disappeared and a smooth etched surface was obtained. Using the optimized etching conditions with N-2 addition, an AlGaN/GaN nanowire structure with a wire width of 110 nm has been successfully fabricated.
  • M Yumoto, S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 41 4B 2671 - 2674 2002年04月 [査読無し][通常論文]
     
    A novel binary decision diagram (BDD) node device based on wrap-gate (WPG) control of AlGaAs/GaAs nanowires is described and fabricated, and its basic operation is characterized. The node device consists of one entry-nanowire branch and two exit-nanowire branches where each of two exit-branches is switched by a Schottky WPG in a complimentary fashion so as to realize path switching for electrons. Basic branch switches as well as BDD node devices were fabricated on AlGaAs/GaAs nanowires formed by electron beam lithography and wet chemical etching of molecular beam epitaxy (MBE)-grown heterostructures. A detailed analysis of gate control characteristics was carried out by magneto tran sport measurements. A three-dimensional potential simulation showed that Fermi level pinning on the semiconductor free surface should be carefully taken into consideration for accurate device design. The branch-switch exhibited excellent gate control from low temperatures up to room temperature. showing clear conductance quantization at low temperatures, The fabricated BDD node device realized clear path switching from low temperatures up to room temperature.
  • M Endo, Z Jin, S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 41 4B 2689 - 2693 2002年04月 [査読無し][通常論文]
     
    The basic etching characteristics of electron cyclotron resonance reactive ion beam etching (ECR-RIBE) of GaN and AlGaN/GaN using methane-based mixtures have been studied in view of application to nanostructure fabrication. GaN could be etched by using a gas mixture of CH4/H-2/Ar at a rate of about 10 nm/min, which is suitable for nanostructure fabrication. The etching process was also applicable to the standard AlGaN/GaN heterostructure. Etching along <1100> and <2110> stripe patterns revealed {0111} and {1121} sidewall facets, respectively, indicating that the etching is a facet-revealing process, being dominated by chemical reactions with low physical damage. However, the etching depth showed anomalous saturation at 400-500 nm, and the toughness of the surface increased with time. An in situ X-ray photoelectron spectroscopy (XPS) study detected the formation of Ga droplets. By adding N-2 into the gas mixture, Ga droplet formation was suppressed, etch depth saturation disappeared and a smooth etched surface was obtained. Using the optimized etching conditions with N-2 addition, an AlGaN/GaN nanowire structure with a wire width of 110 nm has been successfully fabricated.
  • T Muranaka, S Kasai, C Jiang, H Hasegawa
    PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES 13 2-4 1185 - 1189 2002年03月 [査読無し][通常論文]
     
    Growth controllabilities of morphology and wire width are systematically investigated for the InGaAs ridge quantum wires (QWRs) grown by the atomic hydrogen (H*)-assisted selective molecular beam epitaxy (MBE) growth. Detailed scanning electron microscopy (SEM), photoluminescence (PL) and magneto-transport measurements have been made. The optimal H* cleaning remarkably improves the surface morphology of the InGaAs ridge structure on which QWR is formed. The geometrical width of the wire, TV, can be controlled by changing the MBE growth time of the lower InAlAs barrier layer, t(lnAlAs). A simple relationship, W = 9.5 nm/min t(lnAlAs) min, has been obtained. Gate-dependent Shubnikov-de Haas (SdH) measurements on quantum wire transistor (QWRTr) structure having wrap gate (WPG) have indicated tight gate control with a maximum subband spacing of 15 meV. (C) 2002 Elsevier Science B.V. All rights reserved.
  • S Kasai, H Hasegawa
    PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES 13 2-4 925 - 929 2002年03月 [査読無し][通常論文]
     
    The feasibility of a novel approach for single electron quantum LSIs (Q-LSIs) is investigated. It is based on the binary decision diagram (BDD) logic architecture, using arrays of GaAs and InGaAs single electron BDD node devices formed on hexagonal nanowire networks. Single electron branch switches using nanometer-scale Schottky wrap gates on AlGaAs/GaAs etched nanowires and on InGaAs nanowires by selective MBE growth were fabricated. They showed clear conductance oscillation characteristics controlled by a single electron lateral resonant tunneling. Successful design and fabrication of GaAs-based single electron BDD node devices and circuits including OR logic elements and a 2 bit adder indicates the basic feasibility of realizing single electron Q-LSIs by the novel approach, (C) 2002 Elsevier Science B.V. All rights reserved.
  • T Muranaka, S Kasai, C Jiang, H Hasegawa
    PHYSICA E-LOW-DIMENSIONAL SYSTEMS & NANOSTRUCTURES 13 2-4 1185 - 1189 2002年03月 [査読無し][通常論文]
     
    Growth controllabilities of morphology and wire width are systematically investigated for the InGaAs ridge quantum wires (QWRs) grown by the atomic hydrogen (H*)-assisted selective molecular beam epitaxy (MBE) growth. Detailed scanning electron microscopy (SEM), photoluminescence (PL) and magneto-transport measurements have been made. The optimal H* cleaning remarkably improves the surface morphology of the InGaAs ridge structure on which QWR is formed. The geometrical width of the wire, TV, can be controlled by changing the MBE growth time of the lower InAlAs barrier layer, t(lnAlAs). A simple relationship, W = 9.5 nm/min t(lnAlAs) min, has been obtained. Gate-dependent Shubnikov-de Haas (SdH) measurements on quantum wire transistor (QWRTr) structure having wrap gate (WPG) have indicated tight gate control with a maximum subband spacing of 15 meV. (C) 2002 Elsevier Science B.V. All rights reserved.
  • ZW Fu, H Takahashi, S Kasai, F Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 41 2B 1062 - 1066 2002年02月 [査読無し][通常論文]
     
    Attempts were made to characterize and optimize the novel oxide-free insulated gate structure for InP, having an ultrathin Si interface control layer (Si ICL). An in situ X-ray photoelectron spectroscopy (XPS) study indicated that P deficiency took place on the InP surface by the irradiation of a high-energy Si beam during the MBE growth of Si ICL. Based on this, a modified gate structure having an In0.53Ga0.47As cap layer on the InP surface for prevention of phosphorus loss was proposed and its interface proper-ties were investigated. A careful design for quantum state control indicated that the Si ICL thickness should be reduced down to 0.5 nm for the InGaAs cap thickness of 3 nm. In situ XPS spectra showed that no pronounced desorption of As or P took place from the surface in the new gate structure, In situ contactless C-V measurement showed a low and wide interface state density distribution with a minimum of 2 x 10(10) cm(-2) eV(-1). An InP MISFET test device with a Gate length of 2 mum exhibited a maximum gm of 123 mS/mm and a high drain current of 389 mA/mm. These results indicated the effectiveness of the novel oxide-free insulated gate structure for application to InP power MISFETs as well as to surface passivation.
  • ZW Fu, H Takahashi, S Kasai, F Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 41 2B 1062 - 1066 2002年02月 [査読無し][通常論文]
     
    Attempts were made to characterize and optimize the novel oxide-free insulated gate structure for InP, having an ultrathin Si interface control layer (Si ICL). An in situ X-ray photoelectron spectroscopy (XPS) study indicated that P deficiency took place on the InP surface by the irradiation of a high-energy Si beam during the MBE growth of Si ICL. Based on this, a modified gate structure having an In0.53Ga0.47As cap layer on the InP surface for prevention of phosphorus loss was proposed and its interface proper-ties were investigated. A careful design for quantum state control indicated that the Si ICL thickness should be reduced down to 0.5 nm for the InGaAs cap thickness of 3 nm. In situ XPS spectra showed that no pronounced desorption of As or P took place from the surface in the new gate structure, In situ contactless C-V measurement showed a low and wide interface state density distribution with a minimum of 2 x 10(10) cm(-2) eV(-1). An InP MISFET test device with a Gate length of 2 mum exhibited a maximum gm of 123 mS/mm and a high drain current of 389 mA/mm. These results indicated the effectiveness of the novel oxide-free insulated gate structure for application to InP power MISFETs as well as to surface passivation.
  • APPL SURF SCI 190 (1-4): 176-183 2002年 [査読無し][通常論文]
  • PHYSICA E 13 (2-4): 925-929 2002年 [査読無し][通常論文]
  • IEEE Electron Device Letter 23 (8): 446-448 2002年 [査読無し][通常論文]
  • H Hasegawa, S Kasai
    PHYSICA E 11 2-3 149 - 154 2001年10月 [査読無し][通常論文]
     
    Previously quantum device research has been done on discrete device levels and lacks a clear vision for high density integration, This paper proposes a new., simple and realistic approach for quantum large scale integrated circuits (QLSIs) where a binary-decision diagram (BDD) logic architecture is implemented by BDD node devices based on quantum wire transistors (QWTrs) and single electron transistors (SETs) realized by the Schottky in-plane gate (IPG) and wrap-gate (WPG) control of III-V hexagonal nanowire networks, To investigate the feasibility of the proposed approach, BDD devices having QWTrs were formed on GaAs/AlGaAs etched nanowire patterns. They showed expected complimentary quantized conductance switching as required to achieve operation at delay-power products near the quantum limit. The use of embedded InGaAs honeycomb wire networks grown by selective MBE on InP substrates is proposed for constructing circuits operating in quantum regime at room temperature. (C) 2001 Elsevier Science BN. All rights reserved.
  • YG Xie, S Kasai, H Takahashi, C Jiang, H Hasegawa
    IEICE TRANSACTIONS ON ELECTRONICS E84C 10 1335 - 1343 2001年10月 [査読有り][通常論文]
     
    A novel InGaAs/InAlAs insulated gate (IG) pseudomorphic high electron mobility transistor (PHEMT) having a silicon interface control layer (Si ICL) is successfully fabricated and characterized. Systematic efforts to characterize and optimize the insulated gate structure and the PHEMT fabrication process were made by using in-situ X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques. This led to successful fabrication of a novel IG-PHEMT showing excellent stable DC characteristics with a good pinch off and a high transconductance (177 mS/mm), very small gate leakage currents, very high gate breakdown voltages (about 40 V) and respectable RF characteristics f(T) = 9 GHz and f(max) = 38 GHz.
  • H Takahashi, M Yamada, YG Xie, S Kasai, H Hasegawa
    IEICE TRANSACTIONS ON ELECTRONICS E84C 10 1344 - 1349 2001年10月 [査読有り][通常論文]
     
    The fabrication process of a novel Si interface control layer (Si ICL)-based oxide-free insulated gate structure for InP metal-insulator-semiconductor field effect transistors (MISFETs) was successfully characterized and optimized using in-situ reflection of high-energy electron diffraction (RHEED), Raman scattering spectroscopy, X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques, and applied for fabrication of MISFETs. RHEED observation indicated that the optimum initial thickness of the Si ICL with single crystal pseudomorphic growth of Si on InP is 10 Angstrom. Raman scattering spectroscopy showed existence of surface strain on InP covered with the Si ICL without changing LO-phonon peak width, indicating that the Si ICL is grown in a pseudomorphic fashion. A detailed XPS analysis showed that Fermi level pinning was largely reduced by the growth of the Si ICL and its partial electron cyclotron resonance (ECR) plasma nitridation realizing an optimum Si ICL thickness of 5 Angstrom with a good interface to SiNx. C-V measurement confirmed that the optimum Si ICL-based gate formation process realized a full swing of Fermi level almost over the entire bandgap. The fabricated MISFET using the optimum gate structure exhibited excellent gate controllability and stable operation with a low gate leakage currents.
  • YG Xie, S Kasai, H Takahashi, C Jiang, H Hasegawa
    IEEE ELECTRON DEVICE LETTERS 22 7 312 - 314 2001年07月 [査読無し][通常論文]
     
    A novel InGaAs/InAlAs insulated gate pseudomorphic HEMT (IG-PHEMT) utilizing a silicon interface control layer (Si ICL) was successfully fabricated and its DC and RF performances were characterized. The device showed high transconductance of 177 mS/mm even for a gate length of 1.6 mum As compared with the conventional Schottky gate PHEMTs, the gate leakage current was reduced by 4 orders of magnitudes and the gate breakdown voltage was increased up to 39 V. Well-behaved RF characteristics with the current gain cutoff frequency, f(T), of 9 GHz and the maximum oscillation frequency, f(max), of 38 GHz were obtained for the 1.6 mum-gate-length device.
  • T Yamada, Y Kinoshita, S Kasai, H Hasegawa, Y Amemiya
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 40 7 4485 - 4488 2001年07月 [査読有り][通常論文]
     
    We propose a method of constructing quantum-dot logic circuits that can be used to develop large digital systems with ultralow power consumption. These dot circuits consist of dot arrays fabricated using a wrap-gate structure, and they perform logic operations on the basis of the binary decision diagram. Sample dot circuits such as elementary logic gates and adder subsystems are designed. The operation of the designed circuits is confirmed by computer simulation.
  • Taketomo Sato, Seiya Kasai, Hideki Hasegawa
    Applied Surface Science 175-176 176/ 181 - 186 2001年05月15日 [査読無し][通常論文]
     
    The electrical properties of nanometer-sized Schottky contacts which were successfully formed on n-GaAs and n-InP substrates by a combination of an electrochemical process and an electron-beam (EB) lithography, were characterized both experimentally and theoretically. The detailed I-V measurements using a conductive AFM system showed nonlinear log I-V characteristics with large n value in range of 1.2-2.0 which cannot be explained by a standard 1D thermionic emission model. A computer simulation showed that this nonlinear characteristics can be explained by a new 3D thermionic emission model where Fermi-level pinning on the surrounding free surface modifies the potential distribution underneath the nano-contact. Calculation of C-V characteristics showed an extremely small change of the depletion layer width with bias due to the environmental Fermi-level pinning. On the other hand, it was also found that Fermi-level pinning at the metal-semiconductor interface itself is greatly reduced, resulting in a strong dependence of barrier height on the metal workfunction. © 2001 Elsevier Science B.V.
  • S Kasai, N Negoro, H Hasegawa
    APPLIED SURFACE SCIENCE 175 176/ 255 - 259 2001年05月 [査読無し][通常論文]
     
    A scanning-tunneling-spectroscopy (STS) study was performed on MBE-grown (0 0 1) surfaces of GaAs, Al(0.3)Ga(0.7)AS and In0.53Ga0.47As in an ultrahigh vacuum (UHV) STS system to clarify microscopic behavior of surface states causing Fermi level pinning on these III-V compound semiconductor surfaces. On all the sample surfaces, there existed spots which showed anomalous STS spectra showing conductance gaps much larger than the energy gap of the material. The rates of finding such spots as well as the magnitudes of the anomalous conductance gap were strongly material-dependent, increasing in the order of InGaAs, GaAs and AlGaAs. Scanning tunneling microscope (STM) images under low-positive sample biases showed dark areas which gradually decreased with the increase of the positive sample bias, and correlated with the spatial variation of conductance gaps of the STS spectra. On the basis of a detailed computer simulation, the conductance gap anomaly is explained by a tip-induced local charging of surface states where the apparent gap width depends on surface state distribution shape and density. The result shows that an extremely high density of surface states exist on the AlGaAs surface, but not so much on the InGaAs surface with the GaAs surface in between. (C) 2001 Elsevier Science B.V. All rights reserved.
  • T Sato, S Kasai, H Hasegawa
    APPLIED SURFACE SCIENCE 175 176 181 - 186 2001年05月 [査読無し][通常論文]
     
    The electrical properties of nanometer-sized Schottky contacts which were successfully formed on n-GaAs and n-InP substrates by a combination of an electrochemical process and an electron-beam (EB) lithography. were characterized both experimentally and theoretically. The detailed I-ri measurements using a conductive AFM system showed nonlinear log I-ii characteristics with large n value in range of 1.2-2.0 which cannot be explained by a standard 1D thermionic emission model. A computer simulation showed that this nonlinear characteristics can be explained by a new 3D thermionic emission model where Fermi-level pinning on the surrounding free surface modifies the potential distribution underneath the nano-contact. Calculation of C-V characteristics showed an extremely small change of the depletion layer width with bias due to the environmental Fermi-level pinning. On the other hand, it was also found that Fermi-level pinning at the metal-semiconductor interface itself is greatly reduced, resulting in a strong dependence of barrier height on the metal workfunction. (C) 2001 Elsevier Science B.V. All rights reserved.
  • S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 40 3B 2029 - 2032 2001年03月 [査読無し][通常論文]
     
    GaAs-based single electron transistors (SETs) and their logic inverters were successfully designed and fabricated using a Schottky wrap-gate (WPG) quantum wire and dot formation technology. Three-gate WPG SETs, which have two tunnel barrier gates and a center gate for a quantum dot-potential control, showed voltage gains larger than unity due to tight dot-potential control of the center WPG. The conductance peak position of the SET could be systematically controlled by changing the tunnel-barrier-control WPG voltages. A resistive-load single electron inverter utilizing a 3-gate WPG SET as a driver and a WPG quantum wire transistor as an active load was fabricated and it showed a proper inverter operation at 1.6 K and realized a logic transfer gain of larger than unity (1.3) for the first time in III-V semiconductor-based SET inverters. A III-V semiconductor-based complimentary inverter utilizing two 3-gate WPG SETs was also successfully fabricated for the first time and the inverter operation was also confirmed at 1.7 K.
  • T Sato, S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 40 3B 2021 - 2025 2001年03月 [査読有り][通常論文]
     
    The electrical properties of nanometer-sized Schottky contacts formed on n-GaAs and n-InP substrates by an in situ electrochemical process were studied both experimentally and theoretically to understand and improve their gate control behavior in single electron devices and quantum devices. From the current-voltage (I-V) measurements using a conductive atomic force microscope (AFM) system, the nano-Schottky contacts showed nonlinear log I-V characteristics with large and voltage-dependent n values which cannot be explained by the 1D thermionic emission model. The behavior was explained by a novel 3D thermionic emission model including 3D potential distribution modified by an environmental Fermi-level pinning. The depletion characteristics were calculated on the basis of the new model including the environmental effects. The results showed small changes of the depletion layer width with a bias underneath the nano-Schottky contacts due to the environmental Fermi-level pinning. Control of Fermi-level pinning is thus crucial to obtain nano devices in the quantum regime that exhibit good behavior.
  • N Negoro, S Kasai, H Hasegawa
    PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, PTS I AND II 87 441 - 442 2001年 [査読無し][通常論文]
     
    Microscopic topological and spectroscopic properties on MBE-grown (001) surfaces of III-V compound semiconductors with and without covering by ultrathin Si layers were investigated by the scanning tunneling microscope (STM) and scanning tunneling spectroscopy (STS) techniques. Spots with anomalously large STS conductance gaps existed on all the sample surfaces. The rate of finding such spots was strongly material-dependent, increasing in the order of InGaAs, GaAs and AlGaAs. The rate remarkably decreased after Si deposition. On the basis of a detailed computer simulation, anomaly was explained by a tip-induced local charging of surface states. Empty state STM images showed light and dark areas, and they exhibited strong correlation with the spatial distribution of normal and anomalous conductance gaps of the STS spectra, indicating presence of pinning areas with continuous space and energy distribution of surface gap states.
  • Coupled Mode Propagation in a Novel Coupled Quantum Wire Transistor Based on Schottky In-Plane Gate Control of AlGaAs/GaAs Double Quantum Well(jointly worked)
    Proceedings of 25th Int. Conf. Phys. Semicond.(ICPS) 1819 - 1820 2001年 [査読無し][通常論文]
  • S Kasai, H Hasegawa
    PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, PTS I AND II 87 1817 - 1818 2001年 [査読無し][通常論文]
     
    Conductance oscillation characteristics of a Schottky wrap-gate controlled single electron transistor (WPG SET) were investigated. The device showed a small number of high conductance peaks and they were visible up to 30 K. These features were explained by a lateral single electron resonant tunneling. The line width of the resonant state was estimated to be 1.5 meV and indicated the strong coupling between dot and leads, In low temperatures where kT was much smaller than addition energy, the device showed an unusual temperature dependence of the peak width, whose behavior was different from that expected from the theory.
  • Jpn. J. Appl. Phys 40 2021 - 2025 2001年 [査読無し][通常論文]
  • Jpn. J. Appl. Phys 40 2029 - 2032 2001年 [査読無し][通常論文]
  • S Kasai, M Yumoto, H Hasegawa
    2001 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, PROCEEDINGS Volume 47, Issue 2, Pages 199-204 622 - 625 2001年 [査読無し][通常論文]
  • A Kameda, S Kasai, T Sato, H Hasegawa
    2001 INTERNATIONAL SEMICONDUCTOR DEVICE RESEARCH SYMPOSIUM, PROCEEDINGS 626 - 629 2001年 [査読無し][通常論文]
  • ZW Fu, H Takahashi, T Hashizume, S Kasai, H Hasegawa
    2001 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS 413 - 416 2001年 [査読有り][通常論文]
     
    Attempts were made to clarify the cause for the poor reproducibility of successful processing accompanied with a low the transconductance in the previous oxide-free InP MISFET having an ultrathin Si interface control layer(Si ICL). A detailed in-situ XPS study made for each step of processing indicated that deficiency of P on the InP surface took place by the irradiation of high energy Si beam during the growth of Si ICL. Then, a modified passivation structure having an In0.53Ga0.47As cap layer was proposed and investigated. In-situ XPS study indicated that the novel gate structure prevents desorption of P from the InP surface. In-situ contactless C-V method showed a low and wide interface state density distribution with a minimum of 2x10(11) cm(-2)eV(-1). A long-gate InP MISFET test device with a gate length of 2 mum exhibited a maximum gn, of 123 mS/mm and a high drain current of 389 mA/mm.
  • A Ito, T Muranaka, S Kasai, H Hasegawa
    2001 INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS, CONFERENCE PROCEEDINGS 521 - 524 2001年 [査読有り][通常論文]
     
    Novel hexagonal quantum circuits based on the binary-decision diagram (BDD) architecture have been recently proposed by our group towards next generation quantum LSIs (Q-LSIs) operating at room temperature. In this paper, feasibility of InGaAs ridge quantum wire (QWR) honeycomb network structures for such quantum circuits is investigated using atomic hydrogen (H*)-assisted selective MBE. The fabricated structures were characterized in detail by SEM, AFM, PL and CL measurements. By using patterned substrates with wire directions of < 100 >-<(1) over bar 10 > and < 510 >-<(1) over bar 10 > together with optimized H*-assisted selective MBE, honeycomb networks of the sharp and uniform InGaAs ridge structures were realized. Embedded InGaAs QWR honeycomb networks were successfully formed on the ridge structures. The growth technique was further optimized for formation of sub-micron pitch honeycomb structures, which corresponds to integration of BDD node devices up to 10(8) devices/cm(2).
  • M Iwaya, N Yumoto, S Kasai, H Hasegawa
    PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE ON THE PHYSICS OF SEMICONDUCTORS, PTS I AND II 87 1813 - 1814 2001年 [査読有り][通常論文]
     
    Double quantum well (DQW) quantum wire transistors (QWTrs) controlled by Schottky in-plane gate (SIPG) electrodes are proposed and fabricated, and their conductance and magnetoresistance properties were investigated. The observed dependence of quantized conductance plateau in the DQW QWTr indicated presence of symmetric and anti-symmetric mode splitting due to strong tunneling coupling. The magnetoresistance measurement of DQW QWTrs showed complicated peak shifts of the longitudinal resistance with peak-splitting and peak-merging under negative SIPG voltages, and they can be interpreted again as clear evidence for presence of a strong tunneling coupling between two wells.
  • H Hasegawa, T Sato, S Kasai
    APPLIED SURFACE SCIENCE 166 1-4 92 - 96 2000年10月 [査読無し][通常論文]
     
    Transport properties of two types of electrochemically produced nanometer-sized GaAs and InP Schottky contacts were investigated. One is macroscopic contacts containing many nano-dots and the other is isolated single-dot contacts. Macroscopic contacts showed near ideal thermionic emission characteristics with ideality factors close to unity. I-V characteristics of single nano-dor, contacts directly measured by a conductive AFM probe showed nonlinear log I-V behavior with large and voltage-dependent ideality factors. The latter was explained by potential profile modification due to Fermi level pinning on surrounding free surfaces. Both types of contacts indicated that Fermi level pinning disappears as the dot size is reduced, indicating that strong Fermi level pinning is not intrinsic to Schottky contacts. (C) 2000 Elsevier Science B.V. All rights reserved.
  • M Iwaya, S Kasai, N Okada, J Nakamura, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 39 7B 4651 - 4652 2000年07月 [査読無し][通常論文]
     
    Chemical and electrochemical nanofabrication processes used fur fabricating GaAs-based single and coupled quantum wire transistors (QWTrs) utilizing Schottky in-plane gate (IPG) structures are described. IPG and metal dot formation processes using a wet chemical etching and an in situ electrochemical process were optimized for a novel nanodevice fabrication. Fabricated single and coupled QWTrs showed conductance quantization and oscillation characteristics at low temperatures, demonstrating the tight gate control capability.
  • T Sato, S Kasai, H Okada, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 39 7B 4609 - 4615 2000年07月 [査読無し][通常論文]
     
    The current transport characteristics of nanometer-sized Schottky contacts were investigated from theoretical and experimental viewpoints. A theoretical calculation of the three dimensional (3D) potential distributions showed that the potential shape underneath the nano-Schottky contacts was considerably modified by the surface Fermi level pinning on the air exposed free surfaces, producing a saddle point in the potential. The curl ent-voltage (I-V) curves were strongly influenced by this saddle point potential and resulted in nonlinear log I-V characteristics. Experimentally, the Pt nano-particles were selectively formed using the in situ electrochemical process on n-type GaAs and n-type InP substrates patterned using electron-beam (EB) lithography. Their I-V measurements were carried out using an atomic force microscopy (AFM) system equipped with a conductive probe. The log I-V curves of the nano-Schottky contacts showed nonlinear characteristics with large n values of 1.96 for n-GaAs and 1.27 for n-InP and could be very well explained by the theoretical I-V curves considering the "environmental" Fermi level pinning.
  • M Iwaya, S Kasai, N Okada, J Nakamura, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 39 7B 4651 - 4652 2000年07月 [査読無し][通常論文]
     
    Chemical and electrochemical nanofabrication processes used fur fabricating GaAs-based single and coupled quantum wire transistors (QWTrs) utilizing Schottky in-plane gate (IPG) structures are described. IPG and metal dot formation processes using a wet chemical etching and an in situ electrochemical process were optimized for a novel nanodevice fabrication. Fabricated single and coupled QWTrs showed conductance quantization and oscillation characteristics at low temperatures, demonstrating the tight gate control capability.
  • H Hasegawa, N Negoro, S Kasai, Y Ishikawa, H Fujikuwa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 18 4 2100 - 2108 2000年07月 [査読無し][通常論文]
     
    In an attempt to understand and control Fermi level pinning on GaAs surfaces, an ultrahigh vacuum (UHV) scanning tunneling spectroscopy (STS) study was made on (110) and (001) clean surfaces and Si covered (001) surfaces of n-type GaAs prepared by molecular beam epitaxy. Normal STS spectra showing conductance gaps corresponding to GaAs energy gap and anomalous spectra showing much larger gaps coexisted on all samples. The rate of finding normal spectra was very low on the initial surfaces, but it greatly increased after Si deposition particularly on the c(4x4) surface. A previous explanation of the gap anomaly by tip-induced electrostatic bend bending change is invalid. A new model based on a band bending change due to tip-induced local charging of surface states is presented where tunneling proximity makes occupancy of surface states in equilibrium with the scanning tunneling microscopy (STM) tip. Spots with anomalous spectra correspond to Fermi level pinning centers when the tip directly "writes" or "erases" single or a few electrons to and from the surface states. Away from the pinning center, such charge transfer does not take place, and normal STS spectra are obtained with Fermi level positions consistent with macroscopic band bending measured by x-ray photoelectron spectroscopy and by an UHV contactless capacitance-voltage system. No direct one-to-one correlation existed between the pinning center and any specific visual STM defect features such as vacancies, dimer-desorbed holes, dimer kinks, step etc. Pinning centers make up inhomogeneous distributions of spatially extended pinning areas of universal nature surrounding any kind of structural disorder. Si deposition is shown to be very effective in reducing the number, spatial extension and state density of such pinning areas, particularly on the initially c(4x4) reconstructed surface. (C) 2000 American Vacuum Society. [S0734-211X(00)02704-9].
  • H Hasegawa, N Negoro, S Kasai, Y Ishikawa, H Fujikuwa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY B 18 4 2100 - 2108 2000年07月 [査読無し][通常論文]
     
    In an attempt to understand and control Fermi level pinning on GaAs surfaces, an ultrahigh vacuum (UHV) scanning tunneling spectroscopy (STS) study was made on (110) and (001) clean surfaces and Si covered (001) surfaces of n-type GaAs prepared by molecular beam epitaxy. Normal STS spectra showing conductance gaps corresponding to GaAs energy gap and anomalous spectra showing much larger gaps coexisted on all samples. The rate of finding normal spectra was very low on the initial surfaces, but it greatly increased after Si deposition particularly on the c(4x4) surface. A previous explanation of the gap anomaly by tip-induced electrostatic bend bending change is invalid. A new model based on a band bending change due to tip-induced local charging of surface states is presented where tunneling proximity makes occupancy of surface states in equilibrium with the scanning tunneling microscopy (STM) tip. Spots with anomalous spectra correspond to Fermi level pinning centers when the tip directly "writes" or "erases" single or a few electrons to and from the surface states. Away from the pinning center, such charge transfer does not take place, and normal STS spectra are obtained with Fermi level positions consistent with macroscopic band bending measured by x-ray photoelectron spectroscopy and by an UHV contactless capacitance-voltage system. No direct one-to-one correlation existed between the pinning center and any specific visual STM defect features such as vacancies, dimer-desorbed holes, dimer kinks, step etc. Pinning centers make up inhomogeneous distributions of spatially extended pinning areas of universal nature surrounding any kind of structural disorder. Si deposition is shown to be very effective in reducing the number, spatial extension and state density of such pinning areas, particularly on the initially c(4x4) reconstructed surface. (C) 2000 American Vacuum Society. [S0734-211X(00)02704-9].
  • S Kasai, Y Satoh, H Hasegawa
    COMPOUND SEMICONDUCTORS 1999 166,219-222 166 219 - 222 2000年 [査読無し][通常論文]
     
    Basic electrical properties of Schottky wrap-gate (WPG) controlled GaAs quantum wire transistors (QWTrs) and single electron transistors (SETs) are investigated to clarify their applicability to future quantum integrated circuits. The fabricated WPG QWTrs showed excellent gate-control characteristics and conductance quantization, indicating that the WPG can produce a strong lateral confinement potential. The WPG SETs showed clear and high conductance peaks that were suitable for switching device application. A WPG SET-based inverter logic circuits combining a WPG QWTr active load with a WPG SET was fabricated and it showed a clear inverter action, whose inverter gain was in reasonable agreement with the voltage gain of the driver two-gate WPG SET estimated from the Coulomb diamond plot.
  • Jpn.J.Appl.Phys. 39,4609-4615 2000年 [査読無し][通常論文]
  • S Kasai, Y Amemiya, H Hasegawa
    INTERNATIONAL ELECTRON DEVICES MEETING 2000, TECHNICAL DIGEST 585 - 588 2000年 [査読有り][通常論文]
     
    Novel single electron binary-decision-diagram (BDD) node devices and circuits based on Schottky wrap-gate (WPG) control of AlGaAs/GaAs nanowires were designed, fabricated and characterized for the first time. The WPG BDD node device showed clear path switching as well as conductance oscillation by WPG voltage control. WPG-based BDD OR logic circuits were also successfully fabricated. It is also shown that more complex-functional BDD circuits can be realized by suitable layouts of WPGs and nanowires.
  • S Kasai, Y Satoh, H Hasegawa
    PHYSICA B 272 1-4 88 - 91 1999年12月 [査読無し][通常論文]
     
    Conductance oscillation characteristics in GaAs-based Schottky wrap gate (WPG) single-electron transistors (SETs) were investigated both experimentally and theoretically in view of application as a key switching device in future quantum-integrated circuits. Fabricated WPG SETs showed that clear conductance oscillation characteristics with a small number of high conductance peaks. A simple theory based on a quantum mechanical treatment reproduced qualitatively the features of the experimentally observed conductance peaks, indicating that the resonant tunneling contributes to currents in the WPG SETs. However, quantitatively, a discrepancy existed between theory and experiment on the temperature dependence of peak heights. (C) 1999 Elsevier Science B.V. All rights reserved.
  • Y Satoh, S Kasai, K Jinushi, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 37 3B 1584 - 1590 1998年03月 [査読有り][通常論文]
     
    Characteristics of GaAs-based single electron transistors (SETs) based on Schottky wrap gate (WPG) control of the two dimensional electron gas were studied. The two-gate and the newly proposed three-gate devices with different WPG sizes and channel widths were theoretically analyzed on a computer and experimentally fabricated and characterized. The computer simulation showed that dots and tunneling barriers could be formed in both the two-and the three-gate SETs. In the case of the two-gate SETs, both the dot size and the tunnel barriers were changed simultaneously by the gate voltage. On the other hand, in the case of the newly proposed three-gate SET, the dot size and the potential profile of the tunneling barrier could be separately controlled. Experimentally fabricated the two-and the three-gate SETs with narrow channel widths showed conductance oscillation characteristics which were consistent with the results of potential simulation.
  • H Hasegawa, T Sato, H Okada, K Jinushi, S Kasai, Y Satoh
    APPLIED SURFACE SCIENCE 123 335 - 338 1998年01月 [査読有り][通常論文]
     
    In order to realize high temperature operating quantum devices, this paper attempts to form nm-size Schottky in-plane gate (IPG) and wrap gate (WPG) structures on GaAs- and InP-based nanostructures by an in-situ electrochemical process. Pulsed electrodeposition of Pt was found to be optimal, realizing nearly pinning-free high Schottky barrier heights as well as fine and highly uniform nm-size grains with minimal stress. Using the optimized process, quantum wire transistors and single electron transistors were successfully realized on GaAs etched 2DEG bars and on MBE grown InGaAs ridge quantum wires. (C) 1998 Elsevier Science B.V.
  • S Kasai, K Jinushi, H Tomozawa, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 36 3B 1678 - 1685 1997年03月 [査読無し][通常論文]
     
    Single-dot and multiple (2, 3, 18, and 37)-dot single electron transistors (SETs) based on the control of a two-dimensional electron gas (2DEG) with a recently proposed Schottky in-plane gate (IPG) and a newly introduced Schottky wrap gate (WPG) were successfully fabricated on AlGaAs/GaAs wafers using electron beam (EB) Lithography and their transport properties were investigated. Each of the fabricated SETs showed Coulomb blockade-like conductance oscillation. In single-dot SETs, a strong correlation was found between the device dimensions and the temperature limit of the conductance oscillation. Conductance oscillation characteristics of multiple-dot SETs were complicated, and were not explained by the classical Coulomb blockade theory. Based on a simplified theoretical analysis using computer simulation, it was shown that quantized energy due to electron confinement and dot-coupling can dominate the charging effect in the fabricated SETs.
  • S Kasai, K Jinushi, H Tomozawa, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 36 3B 1678 - 1685 1997年03月 [査読無し][通常論文]
     
    Single-dot and multiple (2, 3, 18, and 37)-dot single electron transistors (SETs) based on the control of a two-dimensional electron gas (2DEG) with a recently proposed Schottky in-plane gate (IPG) and a newly introduced Schottky wrap gate (WPG) were successfully fabricated on AlGaAs/GaAs wafers using electron beam (EB) Lithography and their transport properties were investigated. Each of the fabricated SETs showed Coulomb blockade-like conductance oscillation. In single-dot SETs, a strong correlation was found between the device dimensions and the temperature limit of the conductance oscillation. Conductance oscillation characteristics of multiple-dot SETs were complicated, and were not explained by the classical Coulomb blockade theory. Based on a simplified theoretical analysis using computer simulation, it was shown that quantized energy due to electron confinement and dot-coupling can dominate the charging effect in the fabricated SETs.
  • S Kasai, T Hashizume, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 35 12B 6652 - 6658 1996年12月 [査読無し][通常論文]
     
    The electron beam induced current (EBIC) technique was used for characterization of novel GaAs quantum nanostructures based on potential modulation of two-dimensional electron gas (2DEG) by Schottky in-plane gates (IPGs). A simple theory on the EBIC signal from the basic Schottky IPG structure was developed and it was compared to experimental results. Excellent agreement between theoretical and experimental results was obtained, indicating that the EBIC technique is a powerful means to detect electric field profiles in depletion layers of quantum nanostructures. The EBIC technique was also applied to Schottky IPG-based quantum wires, lateral superlattices and multi-quantum dot chains. The EBIC study revealed that effective potential control and electron confinement can be achieved by suitable design of Schottky IPG electrodes.
  • S Kasai, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 35 2B 1340 - 1347 1996年02月 [査読無し][通常論文]
     
    A novel lateral surface superlattice (LSSL) structure based on the Schottky barrier height (SBH) difference produced by periodic insertion of Si interface control layer (Si ICL) stripes is proposed, fabricated and characterized. Two-dimensional computer simulation was first performed to gain information on basic design considerations. An electron-beam-induced current (EBIC) study on the fabricated device directly confirmed SBH modulation by Si ICL stripes. The devices showed periodic oscillations of drain conductance and transconductance at low temperatures up to 10 K. This behavior is distinctly different from that of previous split-gate devices. The mechanism of these oscillations was explained by a sequential resonant tunneling model. According to a quantitative analysis of the data, SBH difference of 70-150 meV was produced at the metal-semiconductor interface, which produced quantized levels with a separation of 2-3 meV at the heterointerface.
  • S Uno, T Hashizume, S Kasai, NJ Wu, H Hasegawa
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS SHORT NOTES & REVIEW PAPERS 35 2B 1258 - 1263 1996年02月 [査読有り][通常論文]
     
    Pt Schottky barrier diodes (SBDs) with a high Schottky barrier height of 0.86 eV and an ideality factor of near unity were successfully realized by a novel in situ electrochemical process. Applying this novel technique to InP metal semiconductor field effect transistors (MESFETs), good gate control of drain current with pinch-off, an effective channel mobility of 1,840 cm(2)V(-1)s(-1) and no drain current drift behavior were achieved. The InP MESFET operates even under a positive gate bias, showing feasibility of enhancement-mode operation as well as depletion-mode operation.
  • S KASAI, H HASEGAWA
    SIXTH INTERNATIONAL CONFERENCE ON INDIUM PHOSPHIDE AND RELATED MATERIALS: CONFERENCE PROCEEDINGS 220 - 223 1994年 [査読有り][通常論文]
  • K KOYANAGI, S KASAI, H HASEGAWA
    JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS 32 1B 502 - 510 1993年01月 [査読有り][通常論文]
     
    An attempt is made to control the Schottky barrier height (SBH) of Al/GaAs(100) Schottky barrier diodes by inserting an ultrathin Molecular beam epitaxy (MBE) Si interface control layer (Si ICL). A theory for SBH control including an ideal case and a relaxed case is presented based on the disorder-induced gap state (DIGS) model. The Schottky barrier height (SBH) is measured by the X-ray photoelectron spectroscopy (XPS), current-voltage (I-V) and capacitance-voltage (C-V) techniques. Theory and experiment show that the SBH can be varied precisely over a wide range of about 400 meV by the use of pseudomorphic Si ICL with suitable As doping. When the Si ICL is above the critical thickness of 10 A, SBH control becomes more difficult due to competition between the ionized dopant atoms and the ionized interface states at the Si ICL-GaAs interface.

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  • Yukihiro Tadokoro, Seiya Kasai, Akihisa Ichiki, Hiroya Tanaka R&D Review of Toyota CRDL 47 (2) 61 -69 2016年04月14日 [査読有り][通常論文]
  • 殷 翔, 劉 柏麟, 田中 啓文, 前元 利彦, 葛西 誠也 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 115 (469) 27 -32 2016年03月03日
  • 藤井逸人, SETIADI Agung, 赤井恵, 葛西誠也, 金井康, 松本和彦, 桑原裕司 応用物理学会春季学術講演会講演予稿集(CD-ROM) 63rd ROMBUNNO.21P-S421-11 2016年03月03日 [査読無し][通常論文]
  • 佐々木 健太郎, 黒田 亮太, 殷 翔, 佐藤 将来, 葛西 誠也 電子情報通信学会ソサイエティ大会講演論文集 2015 (2) 39 -39 2015年08月25日
  • Aono Masashi, Kim Song-Ju, Kasai Seiya 理工研報告特集号 : ASTE : advances in science, technology and environmentology : special issue 11 37 -40 2015年03月
  • 若宮 遼, 葛西 誠也, 青野 真士, 成瀬 誠, 巳波 弘佳 電子情報通信学会総合大会講演論文集 2015 (2) 57 -57 2015年02月24日
  • 若宮 遼, 葛西 誠也, 青野 真士, 成瀬 誠, 巳波 弘佳 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 (443) 81 -85 2015年02月05日 
    粘菌アメーバは単純な構造ながら自律分散的な運動により計算能力を有することが知られている.粘菌アメーバの光刺激回避行動とゆらぎを利用し,制約充足問題(CSP)や充足可能性問題(SAT)を解くアルゴリズムが開発されている.我々は,電子回路によってCSPやSATを解くアメーバ型アルゴリズムを実装し,解探索機能を実現した.本報告ではその回路アーキテクチャと実験結果について述べる.
  • 若宮 遼, 葛西 誠也, 青野 真士, 成瀬 誠, 巳波 弘佳 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 (442) 81 -85 2015年02月05日 
    粘菌アメーバは単純な構造ながら自律分散的な運動により計算能力を有することが知られている.粘菌アメーバの光刺激回避行動とゆらぎを利用し,制約充足問題(CSP)や充足可能性問題(SAT)を解くアルゴリズムが開発されている.我々は,電子回路によってCSPやSATを解くアメーバ型アルゴリズムを実装し,解探索機能を実現した.本報告ではその回路アーキテクチャと実験結果について述べる.
  • 井上慎也, 葛西誠也, SETIADI Agung, 赤井恵 電子情報通信学会技術研究報告 114 (442(ED2014 138-152)) 57 -61 2015年01月29日 [査読無し][通常論文]
  • 黒田 亮太, 殷 翔, 佐藤 将来, 葛西 誠也 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 114 (56) 91 -96 2014年05月28日 
    SiNおよびAl_2O_3をゲート絶縁膜として絶縁ゲート型GaAsエッチングナノワイヤFETのヒステリシス特性とダイナミック信号に対する応答の評価解析を行った.いずれの素子もヒステリシス特性を示したが,Al_2O_3ゲート素子ではゲートバイアスに白色ガウス雑音を重畳すると顕著な平均ドレイン電流分散が観測された.その特徴はしきい値電圧を変えずに電流が減少する特異なものであり,SiNゲート素子では観測されなかった.離散的なドレイン電流状態間の遷移のもとでの電流期待値によって実験結果の解釈を試みた.
  • 阿部 遊子, 田中 貴之, 葛西 誠也 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報 113 (449) 47 -50 2014年02月27日 
    生体の動力源である分子モーターは熱ゆらぎを利用することで高効率駆動することが知られている.生体分子モーターの高効率動作の原理として考えられているのがブラウンラチェットである.我々はブラウンラチェットを電子的に利用するデバイスとしてGaAsナノワイヤに非対称ゲートを周期的に配置したデバイスを作製し,フラッシングラチェットによる電流生成に成功した.本報告では,生成電流を増大すべくフラッシングラチェット動作における入力信号と生成電流の関係を調査し,これら支配要因について検討を行った結果について述べる.
  • 葛西 誠也, 田所 幸浩, 一木 輝久 電子情報通信学会総合大会講演論文集 2013 37 -37 2013年03月05日
  • 殷 翔, 葛西 誠也 電子情報通信学会技術研究報告 : 信学技報 112 (445) 35 -38 2013年02月27日 
    グラフェン3分岐接合デバイス(TBJ)は特異な非線形伝達特性を示し、電界効果による伝導型制御との組合せによりANDゲートとORゲートとして動作可能である。一方、論理関数表現完全系を構成するにはNOTゲートが必要である。本報告では、非線形特性とバックゲートによる伝導型の切替えを利用したグラフェンTBJインバータを提案し、試作評価を行った結果について述べる。試作したグラフェンTBJは非線形伝達特性とともに伝導型切替えによる出力極性反転を示し、バックゲートを入力とすることでインバータ動作を実現した伝達利得として0.013を得た.
  • 中野 雄紀, 田中 貴之, 葛西 誠也 電子情報通信学会技術研究報告. ED, 電子デバイス 112 (154) 55 -59 2012年07月19日 
    化合物半導体ナノワイヤネットワークを母体構造とした省面積・低消費電力論理回路の実現を進めているが,その集積システム化においてはネットワーク中を伝搬する信号の同期化が必要である.本報告では,GaAsネットワーク上に実装可能な同期化素子としてナノワイヤ電荷結合素子(CCD)を取りあげ,クロック同期化した信号伝送およびその効率について検討を行った結果について述べる.試作素子においてMHzオーダーの信号転送を実現した.一方,動的信号に対する転送効率はナノワイヤ表面状態に強く依存し,少数電子転送に大きな影響を及ぼす.SiNを用いた表面不活性化による転送効率の改善を図った.
  • 田所 幸浩, 葛西 誠也, 一木 輝久 電子情報通信学会技術研究報告. NLP, 非線形問題 112 (117) 97 -102 2012年06月28日 
    微弱信号に強雑音が重畳された入力信号から微弱信号のみを取り出す手法として、確率共鳴現象を応用した経路長変調ネットワークが提案されている。ここでは精度良く微弱信号を取り出すために、入力信号に雑音の相関時間以上の遅延を与えて無相関な雑音成分を複数作成し、それらの統計平均を取ることで雑音の影響を抑えている。白色雑音を仮定すると雑音の相関時間は無視できるため、与える遅延量は限りなく短く設定すればよい。しかし、実環境では必ずしも白色雑音となるとは限らない。そこで本報告では、1/f雑音という有色雑音環境下で経路長変調ネットワークを評価し、その有効性を検証する。さらに、経路長変調ネットワークを線形フィルタと非線形素子の混合系として解析・考察を行い、提案手法がノイズシェーピングと同様な効果を持つことを述べる。
  • 佐藤 将来, 村松 徹, 葛西 誠也 電子情報通信学会総合大会講演論文集 2012 (2) 64 -64 2012年03月06日
  • 田所 幸浩, 葛西 誠也, 一木 輝久 電子情報通信学会総合大会講演論文集 2012 78 -78 2012年03月06日
  • 佐藤 将来, 村松 徹, 葛西 誠也 電子情報通信学会技術研究報告 : 信学技報 111 (425) 95 -99 2012年02月07日 
    半導体ナノワイヤ3分岐接合(TBJ)デバイスは,単純な構造ながら室温において特異な非線形特性を示し,アナログ回路やディジタル回路などへの様々な応用が期待されている.応用のためには動作機構に対する理解を深めることが不可欠である.本研究では,エッチングで形成したGaAsナノワイヤTBJデバイスへの光照射により局所的にコンダクタンスを増加させ構造中のコンダクタンスのドメイン箇所を同定する方法で非線形特性の評価を行い,これに基づき非線形動作の機構について検討する.
  • 葛西誠也 第回応用物理学関係速合講演会講演予稿集,2012 6 2012年
  • 村松 徹, 葛西 誠也, 谷田部 然治 電子情報通信学会技術研究報告. ED, 電子デバイス 111 (425) 89 -93 2012年01月 [査読無し][通常論文]
     
    FETの微細化がすすむと素子自身が発する雑音が増加するといわれており,系統的評価や理解が必要である.本研究では次世代集積回路スイッチングデバイスの1つであるIII-V族化合物半導体絶縁ゲートナノワイヤトランジスタをとりあげ,低周波雑音の素子サイズ依存性の評価及びその解析を行った.本素子ではゲート絶縁膜であるSiN中の電子トラップ充放電による雑音が観測された.ナノワイヤ幅の微細化にともない雑音強度が増加すると同時に,スペクトル形状が1/fから1/f^2に連続的に変化した.電子トラップ分布を仮定したスペクトル計算を行い,特定の時定数を有するトラップの時定数分布広がりによってスペクトルの形状が連続的に変化することを説明する.
  • 村松 徹, 三浦 健輔, 白鳥 悠太, 葛西 誠也 電子情報通信学会技術研究報告. ED, 電子デバイス 111 (167) 31 -34 2011年07月22日 
    半導体電界効果トランジスタ(FET)の微細化に伴い素子自身が発する雑音が増大しており,雑音特性の理解と制御が重要になっている.本研究では,絶縁ゲートGaAsナノワイヤFETを試作し,低周波雑音特性の評価を行った.エッチングで形成したGaAsナノワイヤFETにSiN_x絶縁ゲートを設けることで導入した電子トラップの影響,および,素子サイズと低周波雑音強度やスペクトルの相関を実験的に検討した.SiN_x絶縁ゲートの挿入により低周波雑音は増大した.観測された雑音スペクトルは1/f^2であり,離散トラップの充放電によるランダムテレグラフシグナル(RTS)が主である.雑音スペクトルと強度はナノワイヤ幅に依存し,サイズ縮小にともないスペクトルは1/fから1/f^2へ遷移した.
  • 三浦 健輔, 白鳥 悠太, 村松 徹, 葛西 誠也 電子情報通信学会総合大会講演論文集 2011 (2) 58 -58 2011年02月28日
  • 柴田 啓, 白鳥 悠太, 葛西 誠也 電子情報通信学会総合大会講演論文集 2011 (2) 59 -59 2011年02月28日
  • 葛西 誠也 電子情報通信学会総合大会講演論文集 2011 (2) "SS -23"-"SS-26" 2011年02月28日
  • 葛西 誠也, 白鳥 悠太, 三浦 健輔, 中野 雄紀 電子情報通信学会技術研究報告. ED, 電子デバイス 110 (423) 79 -82 2011年02月16日 
    熱ゆらぎによって駆動される量子ドット並列加算ネットワークにおける単電子確率共鳴に関し,ドットばらつきの効果についてシミュレーションを中心とした検討を行った.ドットがばらつくと個々の確率共鳴応答もばらつく.しかし,ネットワーク全体の応答は,均一ドットネットワークの応答に収束する様子が見いだされた.この振舞いはFETしきい値分散ネットワークの挙動とは異なっている.
  • 中野 雄紀, 三浦 健輔, 白鳥 悠太, 葛西 誠也 電子情報通信学会技術研究報告. ED, 電子デバイス 110 (423) 49 -52 2011年02月16日 
    同期型ナノワイヤ集積回路の構成要素として,GaAs系ナノワイヤをショットキーラップゲートで制御した電荷結合素子(Charge CoupledDevice: CCD)の試作とその電荷転送動作について述べる.2つのラップゲートを設け,ゲート電圧をクロック制御することでドットを介した電荷パケットの転送を行う.試作デバイスにおいてクロック周波数に応じたDC電流が観測された.得られた電流は温度に依存しないことから,ゲートクロックによる同期電荷転送が実現されていることが確認された.
  • 葛西 誠也, 三浦 健輔, 白鳥 悠太 電子情報通信学会技術研究報告. ED, 電子デバイス 110 (203) 13 -17 2010年09月06日 
    GaAsエッチングナノワイヤFETによるTHz信号センシングについて述べる.デバイスを低温で動作させ量子化コンダクタンスを発現させると,その強い非線形性によりTHzフォトカレントが生じることを実験的に確認した.実験結果とフォトカレントのメカニズムにもとづき,FET並列加算ネットワーク上で確率共鳴を引き起こすことで微弱THz信号センシング能力の獲得とデバイス動作温度の向上の可能性について検討する.
  • 中野 雄紀, 三浦 健輔, 白鳥 悠太, 葛西 誠也 電子情報通信学会ソサイエティ大会講演論文集 2010 (2) 53 -53 2010年08月31日
  • 白鳥 悠太, 三浦 健輔, 葛西 誠也 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 109 (423) 71 -76 2010年02月15日 
    半導体ナノワイヤネットワークを主体とした,再構成可能な二分決定グラフ(BDD)論理回路について述べる.この回路では,シャノン展開にもとづき一般化されたプール関数をグラフで表現し,そのグラフを物理ネットワーク上に直接実装する.回路の再構成は,プログラマブルスイッチを用いてナノワイヤの導通と非導通を電気的に制御することで行う.また,BDD回路は,関数をコンパクトに表現するグラフ構造にもとづいているため,一般的な再構成回路であるSi CMOSルックアップテーブルと比べて,素子数と面積を減らすことができる.エッチングにより形成したGaAsヘキサゴナルナノワイヤネットワーク上に,ショットキーラップゲートで構成したノードデバイスとSiN電荷トラップ層を用いたプログラマブルスイッチを集積化することで,2入力再構成回路を試作し,その正しい動作と動的な再構成を実証した.
  • 葛西 誠也, 白鳥 悠太, 三浦 健輔 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 109 (423) 17 -21 2010年02月15日 
    量子ドットの単電子充放電プロセスにおける確率共鳴的挙動を理論的に解析した.確率共鳴とはゆらぎによって系の応答が高まる現象で,生体機能にも関与している.単電子系に確率共鳴を取り入れることで,大きな問題である熱ゆらぎの影響を緩和できる可能性がある.単電子ダイナミクスをポアソン型トンネルレートとマスター方程式で記述し解析的に解くことにより,量子ドットでの単電子確率共鳴を理論的に証明した.得られた解析式は単電子デバイスシミュレーションの結果と一致し,現象を定量的に説明する.本解析に基づき系パラメータと確率共鳴応答の関係を明らかにした.また現象の実験的観測方法についても言及する.
  • 柴田 啓, 中田 大輔, 白鳥 悠太, 葛西 誠也 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 109 (423) 65 -70 2010年02月15日 
    ゲート制御したナノワイヤ3分岐接合(TBJ)集積による新しい順序回路について述べる。TBJは3本のナノワイヤを接合しただけの非常にシンプルな構造だが、特異な非線形電圧伝達特性を示し、単体でANDゲートとして動作する。TBJにインバータを接続することで順序回路の構成要素であるNANDゲートを実現できる。独自のゲート配置によりTBJの電圧伝達効率を改善するとともに、同構造をDCFL型インバータとして機能させる。GaAsエッチングナノワイヤネットワークをショットキーラップゲートで制御する回路実装法により順序回路の基本形であるSet-Resetフリップフロップ(SR-FF)を設計・試作し、正しい動作を実証した。
  • 袴田 靖文, 大野 恭秀, 前橋 兼三, 葛西 誠也, 井上 恒一, 松本 和彦 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 109 (423) 11 -15 2010年02月15日 
    微弱信号の応答を増幅することを目的として,カーボンナノチューブ電界効果トランジスタ(CNT-FETs)を用いた確率共鳴現象の研究を行っている.サブスレッショルド領域のCNT-FETのバックゲートに適切な大きさの雑音を加えた微弱入力パルス列を印加したとき,入力パルス列とソース・ドレイン電流間の相関が増大した.さらに,CNT-FETの疑似的加算ネットワークにおいて,相関の増大が観察された.また,相関係数のピーク幅が広がったことから,疑似的加算CNT-FETネットワークが雑音に対してロバストな系であることが示された.従って,確率共鳴現象を基礎とした加算CNT-FETネットワークは高感度非標識センサヘの応用が期待できる.
  • Kasai Seiya, Asai Tetsuya, Shiratori Yuta, NAKATA Daisuke 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 109 (98) 125 -128 2009年06月17日 
    Stochastic resonance phenomenon in GaAs-based nanowire field effect transistors (FETs) and their summing network is studied experimentally. Response to a weak signal of a nanowire FET operating in subthreshold region is enhanced by adding noise to gate. The response is further improved by forming a FET summing network and strong input-output correlation is obtained in wide noise voltage range. The effect of device variation in the network is also investigated and it is found to make the system respond the weak signal without tuning noise intensity.
  • 葛西 誠也, 浅井 哲也, 白鳥 悠太, 趙 洪泉 電子情報通信学会技術研究報告. ED, 電子デバイス 108 (437) 75 -79 2009年02月19日 
    雑音により系の応答が向上する確率共鳴現象を,GaAsナノワイヤネットワーク上に形成したトランジスタを用いて観測することに成功した.しきい値を越えない微弱入力信号に無相関雑音を付加しゲートに与え,ドレイン電流を出力とすると,特定の雑音下において入出力相関値がピークをもつ応答特性が得られた.ピーク点での相関値は,線形系の平均化処理を上回る.また,加算ネットワークを構成すると,並列素子数の増加とともに入出力相関はさらに強くなった.観測された一連の振る舞いを,確率微分方程式を解析することで説明を試みた.
  • 中田 大輔, アブドゥール ラーマン シャハリン ファズリ, 白鳥 悠太, 葛西 誠也 電子情報通信学会技術研究報告. ED, 電子デバイス 108 (437) 63 -68 2009年02月19日 
    ナノワイヤ3分岐接合デバイスは,低温から室温までの広い温度領域において特異な非線形特性を示し,論理回路や高周波回路への応用が期待されている.回路応用においては,メカニズムの理解と目的に応じた特性制御が必要である.本稿ではショットキーラップゲートを備えたGaAsナノワイヤ3分岐接合のデバイスの試作とその詳細評価を行い,ショットキーラップゲートやナノワイヤ長が非線形特性および動作速度に与える効果を調べ,非線形特性メカニズムや特性制御について検討を行った.
  • 葛西 誠也, 浅井 哲也 電子情報通信学会ソサイエティ大会講演論文集 2008 (2) 66 -66 2008年09月02日
  • Zhao Hong-Quan, Kasai Seiya, Hashizume Tamotsu 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 108 (122) 139 -144 2008年07月02日 
    2-bit arithmetic logic unit (ALU) utilizing the binary-decision diagram (BDD) logic architecture for nanoprocessor is fabricated on GaAs hexagonal nanowire networks with Schottky wrap gates (WPGs) and their operation is characterized. The ALU integrates 32 node devices and implements 4 instructions. They are fabricated by 3M or 16M nodes/cm^2 fabrication processes. Fabricated ALU shows correct operations experimentally obtained in classical transport domain at room temperature. Supply voltage and input voltage swing dependences of the circuit operation are characterized. Discrete node devices are also investigated from viewpoint of integration, including path switching, threshold voltage variation and gate leakage current.
  • アブドゥール ラーマン シャハリン ファズリ, 白鳥 悠太, 葛西 誠也 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 107 (474) 33 -38 2008年01月23日 
    ナノワイヤ3分岐接合は,室温において非線形な電気的特性を示し,ナノワイヤを適用した論理集積回路の構成要素として有用である.本研究ではGaAsナノワイヤ3分岐接合デバイスの試作と評価を通し,非線形特性のメカニズムについて検討する.また,デバイス特性をショットキーラップゲート(WPG)により制御することを試みる.さらに,3分岐接合の論理回路応用として,NAND回路の試作評価を行った結果について述べる.
  • 葛西 誠也, 趙 洪泉, 橋詰 保 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 107 (474) 63 -68 2008年01月23日 
    特定のトポロジおよび周期性を有する半導体ナノワイヤネットワーク構造上への能動回路・順序回路の実装について検討を行った.基本回路コンセプト,設計手法について説明し,AlGaAs/GaAsヘテロ構造を用いたエッチングナノワイヤネットワークとショットキーラップゲート(WPG)を利用し各種フリップフロップやリング発振器を設計・試作・評価した結果について述べる.また本回路実装手法の問題点や展開について触れる.
  • 田村 隆博, 橋詰 保, 小谷 淳二, 葛西 誠也 電気学会研究会資料. EFM, 電子材料研究会 2007 (15) 11 -14 2007年11月30日
  • 田村 隆博, 小谷 淳二, 葛西 誠也, 橋詰 保 電子情報通信学会技術研究報告. MW, マイクロ波 106 (460) 179 -182 2007年02月10日
  • 葛西 誠也, 中村 達也, 白鳥 悠太 電子情報通信学会技術研究報告. ED, 電子デバイス 106 (520) 29 -34 2007年01月25日 
    多様な材料により形成されるナノワイヤネットワークに論理情報処理機能を付与する手法について検討する.決定グラフに基づく表現により論理関数を可視化し,これとナノワイヤネットワークとの間トポロジの共通性に着目し,論理関数をナノワイヤネットワーク上に直接実装する.ネットワークの伝導をゲート制御することにより論理演算が可能な回路が実現される.GaAs系エッチングナノワイヤを微細ショットキーゲートで制御するハードウェア化手法によりデモンストレーションを行う.
  • 中村 達也, 葛西 誠也, 白鳥 悠太, 橋詰 保 電子情報通信学会技術研究報告. ED, 電子デバイス 106 (520) 73 -77 2007年01月25日 
    2つの微細ショットキーラップゲート(WPG)を有するGaAs系3分岐ナノワイヤ接合デバイスを試作し、その特性評価を行った。左右ブランチ端にプッシュプル形式で電圧を印加すると、中央ブランチ端の電位は明瞭な非線形な特性を示した。さらに、各WPGに左右非対称のゲート電圧を印加し、左右のブランチのポテンシャルを独立して制御することで、中央ブランチ端の電位に非対称性が認められた。WPGによりナノワイヤの実効綿綿幅を狭窄することで、バリスティック領域における非線形性がより顕著になることを実験的に確認した。
  • 葛西誠也 http://www.mat-bcmos.jst.go.jp/kenkyu/01-01kasai.html 2007年
  • 葛西 誠也, バジール アルベルト, 橋詰 保 電子情報通信学会技術研究報告. R, [信頼性] 106 (377) 33 -38 2006年11月17日 
    ナノメートルショットキーゲートGaN系ヘテロ接合電界効果トランジスタ(HFET)における相互コンダクタンス(g_m)のゲート長依存性劣化について,ゲートリーク電流との相関に注目し,実験的検討を行った.AlGaN表面制御プロセスとゲート周囲へのSiN不活性化膜形成を施したHFETを試作し,未処理の場合と比較して2桁のゲート電流低減を図った.これらの素子では,相互コンダクタンスのゲート長依存性は回復し,ゲート長を1000nmから300nmに短縮することでg_mは30%向上した.ゲート端からの横方向リーク電流がゲート周囲の表面を帯電することで実効的なゲート長を延長する仮想ゲートモデルに基づき,実験結果の解釈を試みた.
  • Kasai Seiya, Shiratori Yuta, Nakamura Tatsuya, TAMURA Takahiro 電子情報通信学会技術研究報告. ED, 電子デバイス 106 (137) 205 -209 2006年06月26日 
    Binary conductance switching at the first quantized conductance step in Schottky-wrap-gate (WPG)-controlled quantum wire transistors was characterized for the low power operation of the hexagonal binary-decision diagram (BDD) logic quantum circuits. The fabricated devices showed clear conductance quantization and their trace survived up to 80 K. They also exhibited non-linear dependence of logic swing and conductance step height on temperature, which were not explained by the standard one-dimensional transport theory. Analysis on the observed behaviors indicated the appearance of charge-spin separation under a low-electron-density condition in the quantum wire. This also suggests the possibility of 0.5G_0 switching, corresponding to single electron switching, even in quantum wire transistors.
  • 阿部 裕二, 中村 達也, 田村 隆博, 葛西 誠也, 橋詰 保, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 105 (550) 21 -26 2006年01月20日 
    超低消費電力単電子論理回路の実現を目指し、独自のヘキサゴナルBDD量子論理回路を実装する単電子節点デバイスについて検討を行った。Y字型のGaAsエッチングナノ細線構造をナノサイズのショットキーラップゲートで制御する構造を用い、2つの量子ドットを利用したブランチスイッチ型と単一の量子ドットを有するノードスイッチ型の2つのタイプの素子を設計・試作・評価した。得られた結果に基づき、集積度、プロセス、消費電力等の観点からヘキサゴナルBDD回路に適したデバイス構造について議論する。
  • 葛西 誠也, 湯元 美樹, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 105 (550) 15 -20 2006年01月20日 
    量子ナノ集積論理回路であるナノプロセッサの低消費電力演算特性を明らかにするために, GaAs系ショットキーラップゲート(WPG)制御量子細線トランジスタおよび単電子トランジスタの論理スイッチング特性に理論的・実験的解析を行った.WPG制御量子細線トランジスタおよび単電子トランジスタについて, サブスレッショルド係数や論理振幅を実験的に評価したところ, これらのパラメータの温度依存性はほぼ線形であり, 理論と一致した.しかし, 量子細線トランジスタの中には温度に対し非線形変化するものが認められ, 電子波干渉効果や微細MOSFETにおけるトンネルによる温度依存性消失とは異なり, トンネルや統計分布以外に論理振幅を支配する物理機構が介在していることが示唆された.
  • 葛西 誠也, 小谷 淳二, 長谷川 英機, 橋詰 保 電子情報通信学会技術研究報告. ED, 電子デバイス 105 (435) 47 -52 2005年11月18日 
    ショットキーゲートGaN系ヘテロ構造FET(HFET)に関し, ナノメートルサイズまでゲート長を短縮した際に生じる特有のゲートリーク電流, および, ゲート制御性のスケーリング異常について, 理論的・実験的検討を行った.ナノメートルショットキーゲートでは, ゲート端と表面電位の差によって形成される強電界領域をキャリアがトンネルするため生じる, 横方向リーク電流が顕著に生じる.またそのゲート制御特性は, この横方向電流成分により引き起こされたゲート端近傍の表面電位の変化: 仮想ゲートにより支配され, スケーラビィリティが失われる.この機構がGaN系材料で固有のものである要因についても考察する.
  • 小谷 淳二, 葛西 誠也, 長谷川 英機, 橋詰 保 電子情報通信学会技術研究報告. LQE, レーザ・量子エレクトロニクス 105 (329) 67 -70 2005年10月13日 
    AlGaN/GaN HFETにおける表面準位の影響を明らかにするために、ゲートリーク電流を詳細に測定し、その結果をシミュレーションと比較し、考察した。その結果、大面積Ni/AlGaNショットキー接合において、ショットキー界面に垂直な縦方向トンネル電流がリーク電流に支配的寄与をすることが分かった。これに対し、ナノスケールショットキーゲートのリーク電流の解析結果は、横方向リークパスの存在を示唆した。これに基づき、縦方向リーク電流の計算結果に横方向リーク電流の計算を付加することで、ゲートリーク電流の振る舞いを計算で再現することができた。このようにナノスケールゲートでは、横方向へのトンネル過程による電子注入が、リーク電流や関連するトラッピングに大きな効果をもたらすことが分かった。
  • 葛西 誠也, 湯元 美樹, 田村 隆博, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 104 (622) 31 -38 2005年01月20日 
    ヘキサゴナルBDD論理量子回路をベースにした超低消費電力ナノプロセッサ(NPU)の実現を目指し, 各ユニットの設計試作およびシステムの構成について検討した.ヘキサゴナルナノ細線ネットワークをナノショットキーゲートで制御し二分決定グラフ(BDD)論理アーキテクチャを実装する手法により, 8 bit加算器等のサブシステムから, ALUやコントローラ等のプロセッサ要素回路を設計・試作した.そして, これらを統合し, ヘキサゴナルBDDをベースとした2bitナノプロセッサを設計するとともに, その動作をシミュレーションにより確認した.さらに, システムの消費電力や実装面積について検討を行った.
  • HASHIM Abdul Manaf, TAKEUCHI Mariko, KASAI Seiya, HASHIZUME Tamotsu, HASEGAWA Hideki Extended abstracts of the ... Conference on Solid State Devices and Materials 2004 664 -665 2004年09月15日
  • 葛西 誠也, 湯元 美樹, 田村 隆博, 長谷川 英機 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 103 (164) 45 -48 2003年07月02日 
    ヘキサゴナル量子二分決定グラフ(BDD)回路技術をベースにした論理サブシステムの設計と実装,および,次世代の超小型・低消費電カデジタル演算ユニットであるナノプロセッサヘの応用について検討した.加算器,減算器,比較器などのサブシステムを設計し. GaAsヘキサゴナルナノ細線ネットワーク構造をショットキーラップゲートで制御する手法で回路実装を試みた.1000万素子/cm^2以上のBDDデバイス集積化が可能なプロセスを開発するとともに,試作した2ビット加算器において正しい演算出力を得た.さらに,8命令2ビット算術論理演算ユニット(ALU)を, Si CMOSゲートと比較し少ない素子数で設計した.
  • 各務高明, 石川史太郎, 葛西誠也, 長谷川英機 応用物理学関係連合講演会講演予稿集 50th (1) 358 2003年03月27日 [査読無し][通常論文]
  • 葛西 誠也, 湯元 美樹, 長谷川 英機 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 102 (640) 17 -22 2003年02月03日 
    化合物半導体ナノ細線ネットワークを用いたヘキサゴナル量子二分決定グラフ(BDD)論理集積回路サブシステムの実装について検討を行った.まず,加算器や比較器などのBDDサブシステムを,ヘキサゴナルネットワーク構造上にグラフの交差なしにレイアウトした.回路試作プロセスの開発を進め,素子集積度4.5×<10>^8素子/^2対応プロセスを実現するとともに,量子細線形節点デバイスを40個集積した4ビット加算器の作製に成功した.量子細線形BDD2ビット加算器にて,正しい演算出力が得られることを古典的輸送モードで確認した.さらに,プロセッサを構成するために必要となるレジスタについて,WPGナノデバイスによる実装を検討した.
  • 各務高明, 石川史太郎, 葛西誠也, 長谷川英機 応用物理学会学術講演会講演予稿集 63rd (1) 290 2002年09月24日 [査読無し][通常論文]
  • 葛西 誠也, 湯元 美樹, 村中 司, 福士 哲夫, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 102 (177) 15 -18 2002年06月26日 
    AlGaAs/GaAsヘキサゴナルナノ細線ネットワーク構造をショットキーラップゲート(WPG)で制御して実装する新しいヘキサゴナル二分決定グラフ(BDD)量子回路方式による集積回路技術について述べる.量子BDD節点デバイスをWPG制御量子細線(QWR)および単電子(SE)スイッチを用いて実現した.これを集積化してANDなどの基本論理回路を試作し,低温での量子輸送モードおよび室温における多数電子動作モード両方において正しい論理動作を確認した.電力・遅延時間積は,QWR形で10^<-18> J,SE形で10^<-22> Jと見積もられた.また,ナノ細線の交差なく任意ビットのBDD加算器を設計するとともに,AlGaAs/GaAsエッチングヘキサゴナルナノ細線ネットワーク構造を用いて全加算器を試作し,集積密度2.5x10^7cm^<-2>を達成した.
  • 葛西 誠也, 湯元 美樹, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 101 (619) 9 -14 2002年01月23日 
    量子デバイスを集積化し論理回路を実現する, ヘキサゴナル量子BDD集積回路について述べる.二分決定グラフ(BDD)論理アーキテクチャをゲート制御量子細線や単電子デバイスを用いて実装する回路であり, 高密度ヘキサゴナルネットワークを利用して論理グラフを直接ハードウエア上に表現する, 新しい形態を有する.その実現には, GaAsヘキサゴナルナノ細線ネットワーク構造を, ショットキーラップゲート(WPG)で制御する方法を用いる.本手法に基づき, 量子細線形および単電子形の節点デバイスを試作評価し, 基本的な動作を確認した.次に, これらを集積化し, 基本論理回路および半加算器を実現し, 論理動作を実証した.さらに, 全加算器の設計, および2ビット全加算器の試作を通じ, 大規模集積化への可能性を示した.
  • 金 智, 遠藤 眞, 橋詰 保, 葛西 誠也, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 101 (618) 19 -26 2002年01月22日 
    GaNおよびAlGaN/GaNヘテロ構造に対してメタン系RIBEを行い、in-situ XPS, SEM, AFM, PLにより、エッチング表面の特性を詳細に評価した。CH_4/H_2/Ar混合ガスを用いた場合、エッチングされたGaN表面は荒れたモフォロジーとなり、同時に窒素空乏が生じた。N_2ガスを添加した場合、エッチングレートの低下と表面モフォロジーの大幅な改善がみられ、エッチング前の値と同程度の表面ラフネスrms値が得られた。また、化学量論的組成に非常に近いエッチング面が達成できた。エッチングガスへのN_2ガス添加の効果は、AlGaN/GaNヘテロ構造のエッチング面でも同様であり、また、光学特性の向上が見られた。エッチングプロセス条件の最適化により、線幅110nmのAlGaN/GaNナノ細線を形成した。
  • XIE Yong-Gui, KASAI Seiya, TAKAHASHI Hiroshi, JIANG Chao, HASEGAWA Hideki IEICE transactions on electronics 84 (10) 1335 -1343 2001年10月01日 
    A novel InGaAs/InAlAs insulated gate (IG) pseudomorphic high electron mobility transistor (PHEMT) having a silicon interface control layer (Si ICL) is successfully fabricated and characterized. Systematic efforts to characterize and optimize the insulated gate structure and the PHEMT fabrication process were made by using in-situ X-ray photoelectron spectroscopy (XPS) and capacitance-voltage (C-V) techniques. This led to successful fabrication of a novel IG-PHEMT showing excellent stable DC characteristics with a good pinch off and a high transconductance (177 mS/mm), very small gate leakage currents, very high gate breakdown voltages (about 40 V) and respectable RF characteristics fT = 9 GHz and fmax=38 GHz.
  • ENDO Makoto, JIN Zhi, KASAI Seiya, HASEGAWA Hideki Extended abstracts of the ... Conference on Solid State Devices and Materials 2001 320 -321 2001年09月25日
  • YUMOTO Miki, KASAI Seiya, HASEGAWA Hideki Extended abstracts of the ... Conference on Solid State Devices and Materials 2001 304 -305 2001年09月25日
  • 謝 永桂, 高橋 賢, 高橋 浩, 江 潮, 葛西 誠也, 長谷川 英機 電子情報通信学会論文誌. C, エレクトロニクス 84 (9) 872 -882 2001年09月01日 
    InP系高速デバイスの作製に用いられるInAlAs/InGaAs/InAlAs/InP多層エピタキシャル薄膜構造を超薄膜シリコン界面制御層(Si ICL)を用いて表面不活性化する手法について基礎的検討を行い, 次の3点について新しい知見を得た.(1)表面にInGaAsキャップ層がない場合とある場合について, ひずみ効果及び量子状態制御を考慮し, 不活性化構造の理論的設計と最適化を行った.(2)設計された不活性化構造を実現するプロセスの検討を行い, Si ICL形成及び窒化プロセスによるSiN_x/Si ICL構造形成条件を最適化するとともに, InGaAsキャップ層の重要性を実験的に明らかにした.(3)最適プロセスによる表面不活性化構造について, デバイスと同一の絶縁性基板上に作製可能なプレーナ形MIS容量素子により多層薄膜MIS構造の界面電子物性を評価し, Si ICLの有用性を実証した.
  • 葛西 誠也, 雨宮 好仁, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 100 (642) 1 -7 2001年02月22日 
    新たな情報処理理論アーキテクチャを実現するGaAs系ショットキーラップゲート(WPG)による単電子二分決定グラフ(BDD)デバイスについて述べる。単電子BDDのキーデバイスである単電子節点デバイスを、AlGaAs/GaAsヘテロ接合エッチング細線と微細ショットキーゲートを組み合わせたWPG構造を用い設計・作製し、その基本動作を確認した。さらに、WPG単電子BDD OR 回路を試作し、その動作実証を行った。また、WPG単電子BDDデバイスによる論理集積回路応用について触れる。
  • 湯元 美樹, 岩谷 将伸, 葛西 誠也, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 100 (642) 27 -33 2001年02月22日 
    ショットキーインプレーンゲート(IPG)およびラップゲート(WPG)型GaAs量子細線トランジスタの工学的応用のため、デバイス特性を詳細に調べると共に、デバイス構造最適化を図った。電流-電圧特性および磁気抵抗特性より、各々のゲート構造における、実効細線幅のゲートデバイス依存性など、ゲート制御特性を明らかにした。また、エッチング細線形状がコンダクタンス特性に与える影響を調べると共に、素子形状制御によるコンダクタンスステップやしきい値制御について検討した。
  • 赤澤 正道, 葛西 誠也, 橋詰 保, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 100 (641) 89 -96 2001年02月21日 
    極微細MOSFETの極薄ゲート酸化膜におけるトンネル電流を、高誘電体を導入せずに低減するための素子構造を提案し、その試作結果を報告する。金属ゲート電極と半導体表面との間に極薄SiO_2膜を介在させ、高濃度の極薄SOIをチャネルとし、擬似的なMESFETとして動作させる。本素子をQMESFETと呼ぶ。QMESFETにおいては、半導体表面の空乏層が擬似的なトンネルバリアとして働き、極薄ゲート酸化膜におけるトンネル電流を大幅に低減する。また、本素子を微細化することにより、ULSI素子として十分な特性を得ることができる。
  • 葛西 誠也, 岡田 浩, 岩谷 将伸, 湯元 美樹, 長谷川 英機 電子情報通信学会ソサイエティ大会講演論文集 2000 (2) 176 -177 2000年09月07日 [査読無し][通常論文]
  • 武山 真弓, 板井 順一, 野矢 厚, 橋詰 保, 葛西 誠也, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 100 (236) 29 -34 2000年07月21日 
    n-InP上の電極材料としてCu単体を用いた場合のCu/InPコンタクト界面に生起する拡散・反応の挙動と電気的特性との関連について詳細に検討した。AES分析及びXPS分析の結果から、熱処理前の状態において既に、Cu/InP界面ではCuの拡散が支配的であることに起因して部分的に不均一反応による異なる反応生成物が得られることが示された。そのような界面での不均一反応は、コンタクトの電気的特性にも影響を及ぼし、そのI-V特性から異なる二つの障壁高さの存在が確認された。これらのことから、電極とInPとのコンタクト界面で均一な反応層を得ることが良好な電気的特性を得るためには重要なプロセスであることが示唆された。
  • 長谷川 英機, 葛西 誠也 電子情報通信学会技術研究報告. ED, 電子デバイス 100 (147) 43 -48 2000年06月21日 
    III-V族化合物半導体量子デバイスの今後の展望と課題について、量子界面エレクトロニクス研究センターの最近の成果を交えながら議論する。制御性の高いエピタキシャル成長技術、優れたヘテロ界面、幅広い材料の選択肢、優れた電子輸送特性、量子効果が顕著に現れることなど、III-V族化合物半導体量子デバイスには多くの特徴があり、物理的な側面のみならず工学的にも注目される。ここでは、量子ナノ構造形成、量子デバイス、材料やプロセス技術、および量子デバイスを用いた回路やシステムアーキテクチャについて述べる。
  • 山田 崇史, 木下 純臣, 葛西 誠也, 雨宮 好仁, 長谷川 英機 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 99 (618) 1 -6 2000年02月10日 
    量子ドットを用いたグラフ論理システムの概念を提案する。ショットキーラップゲート構造による量子ドットアレイでグラフ論理表現を回路化することにより、新しい信号処理システムを創ることができる。ここでは共有二分決定グラフを量子ドットアレイで回路化する方法を示した。例として基本論理回路や加算回路を設計し、シュミレーション上で正しい動作を確認した。
  • 佐藤 威友, 葛西 誠也, 岡田 浩, 長谷川 英機 電子情報通信学会技術研究報告. SDM, シリコン材料・デバイス 99 (618) 79 -84 2000年02月10日 [査読無し][通常論文]
     
    ナノショットキー接触界面の電気的特性を、理論的および実験的立場から検討した。計算機シュミレーションの結果から、ナノショットキー界面直下のポテンシャル形状は電極周囲の影響を強く受け、電流輸送特性は、マクロなショットキー接触とは異なる熱電子放出電流特性を示すことが明らかとなった。このような周囲の影響は、半導体自由表面のフェルミ準位のピンニング現象に起因し、電極サイズが減少するほど顕著になる。一方、電気化学プロセスを用いて作製したナノショットキー接触の電気的特性を導電性AFMで評価した結果、電流・電圧特性はシュミレーション結果と良く一致し、周囲のフェルミ準位のピンニングがナノショットキー接触の電流輸送に大きな影響を与えることがわかった。
  • KASAI Seiya, SATOH Yoshihiro, OKADA Hiroshi, HASHIZUME Tamotsu, HASEGAWA Hideki Extended abstracts of the ... Conference on Solid State Devices and Materials 1997 480 -481 1997年09月16日
  • Hiroshi Okada, Seiya Kasai, Hajime Fujikura, Tamotsu Hashizume, Hideki Hasegawa Japanese Journal of Applied Physics 36 (6B) 4156 -4160 1997年 [査読無し][通常論文]
     
    To clarify the control properties of Schottky in-plane gates (IPGs) and Schottky wrap-gates (WPGs) recently employed in the high-temperature operation of compound semiconductor single electron devices, computer simulations and transport measurements were carried out for gated quantum wires (QWRs). Both types of QWRs showed clear Shubnikov-de Haas oscillations. Non-linear Landau plots confirmed gate-controlled 1D transport in the QWRs. In the GaAs IPG QWR, the effective wire width was found to change linearly with gate bias, whereas this was not observed in the InGaAs WPG QWR. These gate control behaviors are in excellent agreement with theory. Near pinch-off, clear conductance oscillation was seen in both QWRs.
  • KASAI Seiya, JINUSHI Kei-ichiroh, OKADA Hiroshi, TOMOZAWA Hidemasa, HASHIZUME Tamotsu, HASEGAWA Hideki Extended abstracts of the ... Conference on Solid State Devices and Materials 1996 443 -445 1996年08月26日
  • 宇野 正一, 橋詰 保, 呉 南健, 葛西 誠也, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 95 (314) 15 -20 1995年10月19日 
    In-situ電気化学プロセスによる新しいPt/InPショットキー障壁形成技術を開発した。この電気化学プロセスにより、遷移層のない良好なPt/InP界面を実現し、0.86evという高い障壁高さと、理想因子1.13を得た。新しいショットキー障壁形成技術をMESFETに応用し、Pt ゲートInP MESFETを作製した。その結果、ゲート電圧による良好なドレイン電流の制御とピンチオフ特性を得ることができ、チャネル実効移動度は184Ocm^2/vsであった。また、デバイスは正ゲート電圧条件下でも良好なFET動作を示した。
  • KASAI Seiya, HASEGAWA Hideki Extended abstracts of the ... Conference on Solid State Devices and Materials 1995 797 -799 1995年08月21日
  • UNO S., HASHIZUME T., KASAI S., WU N.-J., HASEGAWA H. Extended abstracts of the ... Conference on Solid State Devices and Materials 1995 959 -961 1995年08月21日
  • 葛西誠也, 宇野正一, 中村隆俊, 友沢秀征, 石川靖彦, 橋詰保, 長谷川英機 応用物理学関係連合講演会講演予稿集 42nd (Pt 3) 1995年
  • 葛西 誠也, 宇野 正一, 橋詰 保, 長谷川 英機 電子情報通信学会技術研究報告. ED, 電子デバイス 94 (268) 79 -86 1994年10月11日 
    Si界面制御層を用い、GaAsショットキー障壁高さを制御することを試みた。SiICLの膜厚やドーピングを適切に行うことにより300meV以上の幅で制御できることが示された。またこの技術を量子構造へ応用する目的で、障壁高さを空間的に制御する方法について検討した。SiICLと収束イオンビーム(FIB)を用い、局所的にSiICLとGaAs界面に界面準位を誘起する事により障壁高さを変化させることを試み、障壁高さがおよそ290meVの幅で変化する結果が得られた。これによりnmスケールでショットキー障壁高さを制御できる見通しが得られた。

書籍等出版物

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担当経験のある科目（授業）

  • 科学技術の世界「ロボットは感情をもつか」北海道大学 全学
  • 国際交流科目「Forefront of Semiconductor Electronics」北海道大学全学
  • 科学技術英語演習北海道大学工学部
  • 科学技術の世界「半導体エレクトロニクスの最前線」北海道大学全学
  • 電子情報工学実験IV北海道大学工学部
  • 量子デバイス学特論北海道大学大学院情報科学研究科
  • 量子デバイス工学北海道大学大学院工学研究科
  • 半導体物性工学北海道大学工学部
  • 情報学I北海道大学全学
  • 物理学III北海道大学全学
  • 電子デバイス工学北海道大学工学部

所属学協会

  • 日本化学会   IEEE   電子情報通信学会   応用物理学会   

共同研究・競争的資金等の研究課題

  • 日本学術振興会：科学研究費助成事業 基盤研究(B)
    研究期間 : 2021年04月 -2025年03月 
    代表者 : 葛西 誠也
     
    運動神経系を伝達する筋電信号を取得し随意運動（ユーザーが意図する運動）をリアルタイムかつ高精度に読み出す手段として機械学習の一種であるリザバー計算フレームワークの適用にあたり、適切な規模のシステムを見出すために必要となるリザバー計算系の構成・規模と計算能力の関係について検討を行った。系の数理構造から複雑ネットワーク理論と線形代数を組み合わせたモデル化に至り、リザバーを構成するネットワークおよびノード非線形性と系の関数表現力の関係性が見えつつある。 リザバー計算系に対する深い理解のため物理電子リザバー実装を同時並行して行い、半導体トンネルダイオードによる非線形ノードおよび非線形振動子によるダイナミックノード構成とその接続のシミュレーションおよび実測と評価解析を行った。いずれのノード形態も実現に成功し、さらに実デバイスを用いた実装における課題と対応策について多くの知見を得た。 アメーバ型最適化問題解探索と強化学習を組み合わせた独自の自律ロボットのためのその場行動発見・行動発達の仕組みを創出した。さらに、探索型行動で得た知識をベースに高効率行動へ移行する機構「２段階発達」を編み出し、小規模モデルに対して数値シミュレーションを行い、高効率なパターン反復型の行動を見つけて自発的に移行できることを実証した。本成果は、筋電義手が使用者の随意運動と環境や対象物の違いによるその場の動作調整に可能にし、反射能力の実装につながる。
  • 日本学術振興会：科学研究費助成事業 国際共同研究加速基金(国際共同研究強化(B))
    研究期間 : 2019年10月 -2023年03月 
    代表者 : 松本 卓也, 葛西 誠也, 赤井 恵, 谷 洋介, 玉木 孝
     
    本研究の採択が10月であったことから、外国渡航を伴う研究計画を年度内に実施することは困難であると判断した。そこで、2019年度は、次の２点に絞って研究を実施した。 １．本研究の申請の前提となった共同研究を、本研究の一部として進めた。2018年度に研究代表者の松本の学生が、本研究の相手先研究者であるオランダTwente大学のWiel教授の研究室に留学した。その間行われた研究を完成するために、学生が帰国後、大阪大学で行われていた追加実験を、本研究の一部として行った。具体的には、脳型デバイスを目指したポリアニリンネットワークのインピーダンス測定を行った。Twente大学で前年度に実施した研究結果と良い整合性のあるデータを得ることができた。また、本研究採択前からWiel研から大阪大学へ留学することが決まっていた学生の研究を、本研究の一部として行った。金微粒子ネットワークを用いた脳型デバイスを作る研究の一部で、電子線リソグラフィを用いて、ネットワーク型ギャップ電極の作製に成功した。 ２．本研究の研究協力者である九州工業大学の田中啓文教授により、本研究の研究協力者であるUCLAのGimzewski教授を招いて、九州工業大学にニューロモルフィックAIハードウェア研究センターを設立するための研究会が開催された。そこで、本研究の共同研究者が全員この研究会に参加し、本研究の打ち合わせ会を兼ねることにした。打ち合わせの結果、本研究者の若手である大阪大学の谷洋介助教、京都大学の玉木孝特任助教をオランダTwnete大学に長期で派遣し、共同研究を進めることが決まった。
  • 行動変容を支援する最適化・機械学習融合コンパクトAIの開発
    JST：A-STEP トライアウト
    研究期間 : 2021年05月 -2022年03月 
    代表者 : 青野真士
  • 日本学術振興会：科学研究費助成事業 基盤研究(B)
    研究期間 : 2018年04月 -2021年03月 
    代表者 : 葛西 誠也
     
    筋肉が発する筋電位からユーザの動きや意図を検知し機器に伝える筋電型マン・マシンインターフェース（MMI）は、電動義手やロボットなどの直感的操作を可能にする。しかし実際には信号の誤検出が多く、思い通りに操作することは非常に難しい。本研究は、誰もが日常生活で容易に使える筋電型MMIを目指し、独自の非線形筋電検出手法をベースにユーザや環境に適応する技術を開拓し、筋電検出精度の大幅向上を図ることを目的とする。さらに感覚フィードバック機構を省電力でコンパクトに実装する技術を開発し、筋電検出デバイスと一体化を図り操作性をより高める。2019年度の研究成果は以下の通りである。 （１）人工感覚フィードバックの表現力向上のため、複数の小型偏心モーター振動子の合成による振動多様化を試み、うねりを使い単一振動子では不可能な低周波振動の生成およびトロコイド空間パターンの生成を可能にした。また、振動特性が装置固定圧やまさつなどの装着条件に依存することがわかった。 （２）２振動子合成のうねり周波数の下限が位相同期によって数十Hzに制限されることがわかった。振動子支持基板の構造や振動子の身体固定法と同期の関係を調べ、位相同期を抑制する基板設計および装着要件を見出した。その結果10 Hzレベルの超低周波振動の生成が可能になった。 （３）表面筋電信号から最適動作を推定するために最適化計算の適用を検討し、その一環として独自の最適化計算システム「電子アメーバ」を４足歩行ロボットに搭載し運足推定とその精度向上を試みた。本ロボットは各足の接地情報と少数の動作制約から適切な運足を推定するが、身体姿勢をセンシングし情報追加することで運足推定精度向上が可能になった。 （４）レザバー計算を応用した表面筋電信号解析のため、システム要素となる入力、レザバー、出力の各層の実現に取り組み、基本要素を揃えてシステム構成の準備が完了した。
  • 日本学術振興会：科学研究費助成事業 挑戦的萌芽研究
    研究期間 : 2016年04月 -2019年03月 
    代表者 : 葛西 誠也
     
    半導体の中には電子トラップと呼ばれる電子の落とし穴が複数存在する。原子ほどの大きさしかない電子トラップを１つずつ捉えその電気的影響を調べる計測技術はまだない。本研究は、極細の金属短針によって原子レベルの空間分解能をもつ走査プローブ顕微鏡に、トラップに捕らわれ動きを制限された電子の電荷を増幅する独自のメカニズムを付与し、トラップを出入りする電子の動きを雑音として検知し分析する新しい単一トラップ計測技術を開発した。さらに、この計測技術を分子の電気的性質を調べることに応用した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2013年06月 -2018年03月 
    代表者 : 夛田 博一, 長谷川 修司, 浅井 哲也, 山田 豊和, 宇野 英満, 浅井 美博, 米田 忠弘, 葛西 誠也, 松本 卓也, 高木 紀明, 石田 浩, 小川 琢治, 松本 和彦, 家 裕隆
     
    分子設計・合成、表面物理、分子ナノ技術、半導体工学、情報工学、物性理論を専門とする研究者の共同研究により、(1)分子および分子集合体の精密設計、(2)さまざまな電極表面での分子構造および電子状態解明、(3)非線形・非対称な電流電圧特性を与える分子接合の設計指針と電場や磁場によるスイッチング特性の発現、(4)素子の内在ノイズを利用した確率共鳴素子の作製と電圧印加による自励発振的なパルス発生などに関し、５９１報の論文を発表した。これらの結果は、単分子エレクトロニクス分野の進展に大きく寄与するとともに、分子ネットワークを用いた新しい記憶・演算素子などの研究分野を拓いた。
  • 単一分子集積ネットワークによる情報処理機能実装と信頼性向上
    文部科学省：科研費新学術領域研究（研究領域提案型）
    研究期間 : 2013年10月 -2018年03月 
    代表者 : 葛西 誠也
  • マンーマシンインターフェースのための非侵襲型確率共鳴生体信号検出技術の開発
    半導体理工学研究センター：FSプログラム
    研究期間 : 2013年04月 -2016年03月 
    代表者 : 葛西 誠也
  • 化合物半導体１次元ブラウンラチェットによる超低エネルギー電子輸送の検討
    日本学術振興会：科研費挑戦的萌芽研究
    研究期間 : 2011年04月 -2014年03月 
    代表者 : 葛西 誠也
  • 半導体ナノワイヤ3分岐接合デバイスの非線形メカニズムの解明と制御
    日本学術振興会：科研費基盤研究(B)
    研究期間 : 2010年04月 -2013年03月 
    代表者 : 葛西 誠也
  • 極低電圧動作超並列III-V族半導体微細トランジスタ技術の開発
    JST：先端的低炭素化技術開発（探索ステージ）
    研究期間 : 2011年09月 -2012年09月 
    代表者 : 葛西 誠也
  • 半導体トランジスタ確率共鳴を利用した耐雑音生体信号検出技術の開拓
    半導体理工学研究センター：ISプログラム
    研究期間 : 2011年08月 -2012年07月 
    代表者 : 葛西 誠也
  • 量子コンピューティング実現に向けた化合物半導体基本量子論理ゲートの開発
    日本学術振興会：科研費奨励研究(A)
    研究期間 : 2000年04月 -2012年03月 
    代表者 : 葛西 誠也
  • 確率共鳴を利用した新しい情報処理のためのナノデバイスと集積化
    JST：戦略的創造研究推進事業さきがけ
    研究期間 : 2007年10月 -2011年03月 
    代表者 : 葛西 誠也
  • Stochastic resonance nanodevices and their integrated systems
    JST Basic Research Programs (Precursory Research for Embryonic Science and Technology :PRESTO)
    研究期間 : 2007年 -2011年
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2008年 -2010年 
    代表者 : 雨宮 好仁, 葛西 誠也, 浅井 哲也
     
    本研究では生命現象の一端を担う反応拡散メカニズムを模倣する単電子集積システムの構成法を提案した。反応拡散系を電子化するために、多数の単電子トンネル振動子をマトリクス配置して容量結合した二次元ネットワークを設計した。動作シミュレーションによれば、この系には時空間秩序をもった負のノード電位パターン(電子的な散逸構造)が発生して成長・分裂・増殖など生命的な挙動を示した。よって、この系は電子的な疑似生命体を生み出す反応拡散系である、という結論を得た。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2006年 -2010年 
    代表者 : 福井 孝志, 雨宮 好仁, 本久 順一, 葛西 誠也, 原 真二郎
     
    電子線描画法による微細パターン形成技術と有機金属気相成長法とを組み合わせて、化合物半導体ナノワイヤの選択成長技術を確立した。成長したガリウムヒ素、インジウムリン等の半導体ナノワイヤは、その結晶形態を電子顕微鏡で解析、光学特性をフォトルミネッセンスで解明すると共に、トランジスタ構造を作製して電気伝導特性の解析と評価、異種接合やp-n接合を作製してレーザ、発光ダイオード、太陽電池素子としての動作原理を確認する等、次世代ナノエレクトロニクスへの応用展開の可能性を見出した。
  • ヘキサゴナルBDD量子回路方式に基づく超小型・超低消費電力ナノプロセッサ
    日本学術振興会：科研費若手研究(A)
    研究期間 : 2005年04月 -2008年03月 
    代表者 : 葛西 誠也
  • ナノショットキーゲート制御量子ナノドット集積デバイスによる単電子確率共鳴の観測
    日本学術振興会：科研費萌芽研究
    研究期間 : 2006年04月 -2007年03月 
    代表者 : 葛西 誠也
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2006年 -2007年 
    代表者 : 雨宮 好仁, 葛西 誠也, 浅井 哲也, 廣瀬 哲也
     
    量子ドット非線形振動子からなる複数個の反応拡散系をニューラルネットワークで相互結合して自己組織化量子集積回路を構成するために、ニューラルネットワークを量子ドット非線形振動子で構成する方法を開発した。 生体の神経細胞は電気的なスパイク信号を媒体として他のニューロンとコミュニケーションを行う。これを簡単にモデル化するため、スパイク発生時の複雑な非線型現象を単純化して、ニューロンをスパイク点列の発生装置-スパイクニューロン-と見なし、このスパイクニューロンを量子ドットデバイスで構成するために、単電子トンネル事象をスパイク信号に対応させることを提案した。 生体ニューロンは三つの部分、すなわち樹状突起、細胞体、および軸索からなる。このうち軸索は単安定の量子ドット振動子を一次元結合することで電子化できる。細胞体を電子化するには、トンネル事象の時間平均個数に応じて出力のトンネル事象を発生するデバイスをつくればよい。これは、単安定の量子ドット振動子に複数の入力キャパシタ結合を付けることで実現可能である。細胞体と軸索を模倣するデバイス構造を設計し、その動作をシミュレーションで確認した。 生体ニューロンの軸索は末端で分岐し、その端部がシナプスと呼ばれる結合部を介して他のニューロンの樹状突起に接続している。これによってニューロン間で信号の授受を行っている。大まかにはシナプス結合強度が不変とみなしてもよい。一定強度のシナプス結含を構成する方法を提案し、基本的なパルスニューラルネットワークを構成するための方針を示した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2005年 -2006年 
    代表者 : 橋詰 保, 葛西 誠也, 佐藤 威人友, 金子 昌充
     
    GaNおよびAlGaN混晶の表面結晶欠陥および不純物の振舞いを詳細に評価し、金属界面特性・絶縁体界面特性との相関、および、デバイスの電流崩壊、漏れ電流および劣化・破壊現象との関連性を系統的に調べてこれらの機構を明らかにし、表面欠陥制御・界面制御に基づきデバイスの信頼性・安定性の向上に直結する知見を得ることを目的とした。 1)Al<0.26>Ga_<0.74>N混晶にショットキー接合を形成し、過渡容量応答解析を行ない、深い準位を評価した。秒オーダーの時間領域で解析することにより、伝導帯下端より0.9eVの位置に電子捕獲準位が1x10^<16>cm^<-3>程度の高密度で存在することを明らかにした。 2)CN_x/SiN_x複合膜構造を利用した拡散プロセスを開発し、GaNへの炭素ドーピングを行なった。N_2雰囲気中で1000℃程度の熱処理を行なうことにより、炭素がGaN中へ拡散することを確認し、拡散した炭素は主として深い準位として振る舞うことを明らかにした。 3)窒素ラジカル処理、超薄Al膜堆積、真空アニールにより、AlGaN表面近傍の窒素空孔欠陥と酸素不純物を低減する表面制御プロセスを開発し、Ni/AlGaNショットキー接合において、逆方向漏れ電流の大幅な低減と電流-電圧特性の明確な温度依存性を実現した。 4)GaNおよびAlGaNとの絶縁膜界面を種々のプロセスにより形成し、高温および光照射下での容量-電圧測定により、禁制帯中央から価電子帯上端に分布する界面準位のふるまいを初めて明らかにした。また、界面準位の抑制には、超薄Al酸化膜制御層が有効であることを示した。 5)AlGaN/GaNヘテロ構造トランジスターを製作し、高温におけるoff-stateバイアスストレスによりDC特性がどのように変化するかを調べた。SiN_x膜のみの表面保護を行なった場合、ストレス後にドレイン抵抗の増加による特性劣化が見られたが、Al超薄膜を利用した表面制御プロセスを施したデバイスでは劣化が全く見られなかった。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2005年 -2005年 
    代表者 : 長谷川 英機, 葛西 誠也, 佐藤 威友, 賈 鋭
     
    テラヘルツ(THz)帯の周波数領域では、効率よく電磁波を発生・増幅・検波する技術が確立されておらず「テラヘルツギャップ」とよばれている。本研究の目的は、ミリ波・テラヘルツ帯におい.て増幅・検波機能を果たす新しい進行波型半導体デバイスの可能性を、理論的および実験的に検討することにある。その原理は、半導体の2次元電子ガス中に発生するドリフトプラズマ波と、遅波構造による電磁波の空間高調波との相互作用を利用することにある。 (1)電子の慣性項を取り入れたより厳密なプラズマ方程式をもとに、TMモード解析とグリーン関数を含むFredholm積分方程式による空間高調波解析を行い、その結果ミリ波・THz帯で、大きな負性コンダクタンスが得られことを確認した。そして、その機構が高周波では1サイクルあたりの衝突頻度が飛躍的に減ることにあることを示した。 (2)さらに、解析を半導体の表面準位の効果を含むものに拡張し、表面状態による電界分布の変化やスクリーニングが、デバイスに悪影響を及ぼすことを見出した。 (3)AlGaAs/GaAsヘテロ接合上に、インターディジタル型遅波構造を形成したデバイスについて、マイクロ・ミリ波帯で予備実験を行い、おおきなコンダクタンス変調を観測するとともに、理論解析と実験がよく一致することを実証した。これらは、Jpn.J.Appl.Physの正規論文やISDRS(Dec.2005)の国際会議で報告された。 (4)大電力の観点からさらにすぐれた材料は、窒化物系であるが、ヘテロ接合形成技術や電極形成技術が遅れている。このため、この材料のヘテロ界面や表面制御の研究や調査を活発に同時進行させ、多くの成果を得て、これらを公表した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2001年 -2005年 
    代表者 : 福井 孝志, 長谷川 英機, 雨宮 好仁, 本久 順一, 橋詰 保, 葛西 誠也
     
    平成17年度は、有機金属気相成長(MOVPE)選択成長法による量子ナノ構造を利用した単電子素子・単電子回路の実現と、高密度量子ナノ構造の周期配列の形成技術の確立を目的として、以下の研究を行った。 1.前年度に続き、単電子トランジスタの論理回路応用を目的に集積化を進めた。2分決定グラフ論理による1ビット加算器に関して、論文公表することが出来た。また、選択成長により作製したリッジ型量子細線と、自己形成InAs量子ドットを組み合わせた、フローティングゲート型の単電子メモリーの試作とその動作特性解析を進めた。試作した素子を温度20Kで評価した結果、ドレイン電流に、ゲート電圧に対する明瞭な時計回りのヒステリシスが観測された。印加するゲート電圧の最大値を変化させる実験、あるいはヒステリシスの幅やしきい値のシフト量およびその温度依存性、さらにゲート電圧を変化させた後の時間応答などの実験結果により、このヒステリシスが、ゲート側から注入された電子が量子ドットに保持されることに起因することが示された。 2.単電子素子の高温動作化を目的として、選択成長を用い、新しい種類のナノ構造の作製を試みた。具体的には、円形あるいは6角形のマスク開口部を有するGaAs(111)B基板に対して選択成長を行うことにより、直径50nm、長さは9μmにもおよぶ、GaAsナノワイヤ構造の作製に成功した。そして、このナノワイヤを単電子素子へと応用するプロセス手法を考案した。同様な構造はInP(111)A基板上にも作製した。まずInPナノワイヤ、横方向成長を利用したInP/InAsコアシェル構造、さらにInP/InAs/InP横方向ヘテロ構造からなるInAs量子リングを作製し、その光学的特性から、量子閉じ込め構造を確認した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2002年 -2004年 
    代表者 : 橋詰 保, 本久 順一, 葛西 誠也, 赤澤 正道
     
    本研究では、GaN系材料の表面、金属界面、ヘテロ接合界面、保護絶縁膜界面の構造的・化学的特性およびそれらと電気的特性との相関を系統的に評価し、プロセス技術にフィードバックし、絶縁ゲート型およびショットキーゲート型ヘテロ構造電界効果トランジスタ(AlGaN/GaN HFET)の高安定化を実現することを目的とした。主な成果を以下にまとめる。 (1)水素プラズマを含むプロセス、高温熱処理プロセス、プラズマドライエッチングプロセスによって、AlGaN表面において顕著な窒素空乏が生じ、伝導帯下端近傍に深いドナー準位が形成されることを明らかにした。また、この深いドナー準位が、トランジスタの電流変動の主因になっていることを指摘した。 (2)MBE装置内でのAl薄膜の分子線蒸着とECR励起酸素プラズマ酸化により、3〜4nmの超薄Al_2O_3膜をAlGaN表面に形成するプロセスを開発し、Al_2O_3膜の禁制帯幅が7eV、Al_2O_3/Al_<0.3>Ga_<0.7>Nの伝導帯の不連続量が2.1eVであることを明らかにした。 (3)さらにこの超薄Al_2O_3膜をゲート絶縁膜と表面不活性化膜に応用し、新しい絶縁ゲート型AlGaN/GaNヘテロ構造電界効果トランジスター(HFET)を試作し、良好なゲート制御特性、大きな飽和ドレイン電流(0.8A/mm)、大きな相互コンダクタンス(130mS/mm)を達成した。また、ショットキーゲート型HFETで観測された電流コラプス現象がAl_2O_3絶縁ゲート型HFETでは観測されず、超薄Al_2O_3膜を利用した表面保護構造のデバイス安定化効果を確認することができた。 (4)ショットキー接合の電流-電圧特性における表面近傍の深いドナー準位の影響を、数値計算と実験の両面から検討した。厳密な数値計算プログラムを用いた計算により、実験で求められた電流-電圧特性の温度依存性のふるまいを、詳細に再現することに成功した。その結果より、深いドナー準位のイオン化により薄層化したショットキーバリアが、非常に大きな逆方向漏れ電流の主因であることを明らかにした。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2002年 -2003年 
    代表者 : 本久 順一, 須田 善行, 葛西 誠也
     
    平成15年度は、フラットバンド強磁性が実験的に確認できるという理論的予測がされている、周期0.7μmのInAsによるKagome格子を有機金属気相成長(MOVPE)選択成長法により作製するするため、以下のような実験を行った。 まず、SiO_2膜堆積を堆積したGaAs(111)A基板に対して、電子線リソグラフィ、およびウエットエッチングにより、MOVPE選択成長用のマスク基板を作製した。マスクのパターンは昨年度のものと同様、6角形あるいは3角形のマスクを周期的に配列させたものであるが、今回は、(111)B基板ではなく、(111)A基板を用いている。その後、窓明け部分へ、GaAsおよびInAsを、MOVPE選択成長を行った。 まず、(111)Aプレーナ面では平坦な表面が得られる、温度500Cにおいて格子周期が1〜3μmのマスクパターンに対して、選択成長を行った場合、細線の交点部分にのみ、3次元的にInAsが成長するが、成長温度を下げると、3次元成長モードから2次元成長へと転移することが明らかとなった。この成長モードの転移は、成長温度の低下に伴う表面拡散長の減少によって説明でき、またGaAsとInAsの格子定数の差による歪みは、その成長界面で発生したミスフィット転移により緩和されていると考えられる。この結果、ピットを含み、表面平坦性には問題があるが、垂直{110}ファセットを側壁として有する細線の交差構造である、InAsによるKagome格子が、そのマスクパターンを踏襲して形成可能であることが示された。さらに、表面平坦性を改善するため、アルシン(AsH_3)分圧に対する依存性について調べた。その結果、AsH_3分圧を下げた場合に、表面平坦性に優れ、また横方向成長が抑制され、マスクパターンを踏襲したKagome格子構造が形成されることがわかった。 以上に述べた成長条件の最適化の結果、温度400C・低AsH_3分圧という成長条件で、MOVPE選択成長により、周期0.7μmのInAs Kagome格子の形成に成功した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2001年 -2003年 
    代表者 : 長谷川 英機, 赤澤 正道, 橋詰 保, 雨宮 好仁, 葛西 誠也
     
    本研究は、独自の二分決定グラフ(BDD)論理アーキテクチャを実装する集積回路をナノショットキーゲートで量子ドットを形成制御する単電子節点デバイスを用いて実現することを目的とする。当該研究期間に得られた主な成果を以下に示す。 1.BDDアーキテクチャをヘキサゴナルナノ細線ネットワークを用いて高密度に実装する新しい量子論理回路方式「ヘキサゴナルBDD量子回路方式」を提案し、本方式に基づき各種論理サブシステムから算術論理演算ユニット(ALU)まで設計した。 2.GaAsエッチングナノ細線をショットキーラップゲート(WPG)で制御する方法でBDD節点デバイスを実現し、低温から室温まで明確なスイッチング動作を確認した。単電子形では電力遅延積(PDP)が10^<-22>Jと極めて小さいことを明らかにするとともに、WPGスイッチがGHz動作可能であることを実験的に示した。 3.エッチングヘキサゴナルナノ細線ネットワークをWPGで制御する手法でBDD基本論理回路を試作し、低温において量子輸送のもとで論理動作を実証した。また本回路はPDPとのトレードオフにより室温においても演算が可能であることを示した。さらに、4500万素子/cm^2を実現する高密度集積プロセスを確立するとともに、単電子および量子細線型2ビット加算器を試作評価し正しい論理動作を確認した。そして、8ビット加算器の試作に成功した。 4.MBE選択成長法によるヘキサゴナル量子ナノ細線ネットワーク形成技術を開発し高密度化を図り、GaAs系で2.4x10^8、InP系で10^9素子/cm^2に相当する集積構造形成技術を確立した。さらに、選択成長量子ナノ細線を用いた量子細線スイッチおよび節点デバイスの試作に成功した。 5.量子ナノ構造表面不活性化技術として、超薄膜Siおよびc-GaN界面制御層(ICL)による手法を検討し最適化を図った。ICL形成前の初期表面として(4x6)再構成面を用いることで極めて高い表面不活性化効果が得られることを初めて明らかにし、絶縁体/GaAs界面の最小界面準位密度を4x10^<10>cm^<-2>eV^<-1>まで低減した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2000年 -2001年 
    代表者 : 長谷川 英機, 葛西 誠也, 橋詰 保, 江 潮
     
    本研究の目的は、独自の構造をもつIII-V化合物半導体量子細線トランジスタによって、量子限界近傍で動作をする論理回路やメモリー回路のプロトタイプを実現し、量子集積回路に実用化の展望を切り開くことにある。本研究の成果を以下に示す。 1.ショットキーインプレーンゲート(IPG)量子細線トランジスタと金属ナノドットを組合せ、ドットクローン荷電でトランジスタのコンダクタンスしきい値を制御する新しい単電子メモリデバイスを提案、開発した。 2.単電子小規模集積回路をWPG単電子トランジスタ(SET)により構成することことを検討し、量子細線トランジスタを負荷とする単電子抵抗負荷インバータや、2つのSETを用いた単電子相補形インパークを試作し、動作を実証した。ことに前者では伝達利得1.3が達成された。 3.量子限界近傍の電力・遅延時間積で動作可能な新たな量子論理回路として、二分決定グラフ(BDD)アーキテクチャを量子細線トランジスタで実装するBDD量子論理回路方式を提案した。そして、基本デバイスをGaAsエッチングナノ細線とナノショットキーゲート技術を用いて試作し、低温および室温にて動作実証するとともに、これを集積化することにより基本論理回路を試作し回路が正しい論理演算を行うことを確認した。 4.量子細線トランジスタの基本構造として、均一性およびサイズ制御性に優れたInGaAsおよびGaAs埋め込みリッジ量子細線アレイを選択MBE成長法により実現した。ことにInGaAs量子細線においては基板前処理の最適化や原子状水素処理の適用により、サブミクロンピッチ高密度細線アレイの実現に成功した。 5.素子表面不活性化のために、III-V族半導体表面を走査トンネル分光(STS)法により詳細に評価した。異常STSスペクトルの機構を明らかにし、ピンニングがエネルギー的・空間的に連続分布する表面準位の集合体によることを示した。さらに、シリコン界面制御層(Si ICL)を用いた表面不活性化法を検討し、Si ICL形成前初期表面の最適化を図るとともに、本手法の有効性をSTSなどで確認した。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 1999年 -2001年 
    代表者 : 橋詰 保, 葛西 誠也, 兼城 千波, 本久 順一, 関 昇平, 武山 真弓
     
    本研究では、GaN表面の詳細な評価に基づく金属/半導体界面制御を試み、安定なショットキー接合と、低接合抵抗オーミック電極形成のための作製プロセスを確立することを目的とする。得られた主な成果を以下にまとめる。 (1)n-GaNに対して安定なショットキー接合法を確立することを目的として、プロセス直前のGaN表面の表面フェルミ準位の位置を光電子分光(XPS)法を用いて測定し、表面のバンド曲がりを詳細に評価した。(1)大気に曝した表面のバンド曲がりは1.4eVと大きく、フェルミ準位が強くピンニングされていることが分った。(2)アンモニア溶液処理と窒素プラズマ処理を行うことでバンド曲がりは0.5eV程度緩和し、分子線エピタキシー法で成長した表面と同等の電子状態が得られることが明らかになった。 (2)電子デバイスのショットキーゲート構造への応用を目的として、逆方向リーク電流特性を詳しく調べた。(1)n-GaNに対するショットキー接合の逆方向リーク電流は熱電子放出理論で計算される値よりも数ケタ高く、かつ、バイアス依存性が強く温度依存性が弱い。(2)逆方向リーク電流はショットキー電極とオーミック電極間の表面状態や表面構造に敏感であり、バイアス掃引に対してヒステリシスを持つ。これらの結果より、n-GaNに対するショットキー接合の電流輸送特性には、接合界面および電極間表面のトラップに起因するリーク機構が影響していることが強く示唆された。 (3)AlGaN表面に超真空中で金属Alを約1nm蒸着後、真空アニール(800℃、10min)することで、金属AlとAlGaN表面に残留している自然酸化膜が反応して形成された極薄Al酸化膜を表面不活性化膜として利用し、GaN/AlGaNヘテロ構造上のショットキーゲート特性の改善を実現した (4)MgドープP-GaN表面のXPS分析を行った。Mg原子の表面蓄積に伴うMg-O結合ピークが強く検出され、GaおよびNの内殼ピークの半値幅がn-GaNと比較して1.5倍程度に増加していることが分った。表面でのバンド曲がりは1.3eVと強く、Mg蓄積による表面乱れ層により、高密度の表面欠陥準位が存在していることが示唆された。ECR励起のN2プラズマによる表面処理で、表面乱れは回復し、ほぼフラツトな表面バンドを実現できることが明らかになった。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 1999年 -2000年 
    代表者 : 長谷川 英機, 江 潮, 葛西 誠也, 橋詰 保, 藤倉 序章
     
    本研究の目的は、化合物半導体上にナノスケールでサイズ制御された微細ショットキー接合を形成する手法により、フェルミ準位ピンニングを除去し、金属-半導体界面の物性を制御する技術を創り出すこと、および、そのデバイス応用にある。本研究の成果を以下に示す。 1.電気化学プロセスにより形成した化合物半導体ショットキー界面は、ナノ金属ドットの集合体により形成されること、および、印加パルス条件により、ドット粒径、ドット数を制御可能であることを示した。さらに、各々の金属ドットが小さく均一性が高くなるに従い、金属-半導体界面のフェルミ準位ピンニングが緩和し、障壁高さの金属仕事関数依存性が増大することを実験的に見出し、ショットキー極限の実現による障壁高制御が可能であることを示した。 2.電気化学プロセスと電子線露光法により、ゲート長数十nmのナノショットキーゲート、および、数十nmのドット径を有する高均一ナノ金属ドットアレイの形成に成功した。 3.単一金属ドットナノショットキー接合の電気的特性を、導電性プローブ原子間力顕微鏡を用いて評価すると共に、ナノショットキー特性解析シミュレーターを開発し、その電流輸送機構を明らかにした。同時に、単一金属ドット・半導体界面においても、ドットサイズの縮小に伴い障壁高さの金属仕事関数依存性が高まること、および、電極周囲の表面フェルミ準位ピンニングがナノショットキー接合の電流輸送やポテンシャル制御性に大きく影響することを見出した。 4.電気化学プロセスによるナノショットキーゲートとナノ金属ドット形成技術を用い、GaAsおよびInGaAs量子細線トランジスタ、単電子トランジスタ、単電子メモリ回路などの量子デバイスを試作・評価した。各素子は、制御されたショットキー界面を反映した動作を実現し、本技術の有効性が実証された。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 1998年 -1999年 
    代表者 : 長谷川 英機, 葛西 誠也, 藤倉 序章, 橋詰 保, 上田 大助
     
    本研究は、本グループが提唱している「超薄膜シリコン量子井戸を含む新しい絶縁ゲート構造」を用いることにより、InP系超高周波大電力デバイス実現に、突破口を開くことを目的として、平成10年度から平成11年度にわたって行なったものである。本研究により得られた成果を以下にまとめる。 (1)本研究グループが独自に開発した超高真空非接触C-V法、ホトルミネセンス表面準位分光法(PLS^3)に基づく絶縁ゲート構造形成プロセスのその場評価法を確立するとともに、これらとSTM/STS測定およびXPS法を組み合わせ、表面フェルミ準位ピンニングが表面のある程度の面積を持った領域で生じており、しかも各領域において表面準位がU字形の連続分布を有していることを明かにした。これは、「超薄膜シリコン量子井戸」の概念の基礎となった界面準位の起源に関する「統一DIGSモデル」を支持する結果である。 (2)InP系化合物半導体上へ擬似格子整合する超薄膜シリコン層のMBE成長と、ECRプラズマを用いたシリコン層の部分窒化による薄膜化により、シリコン量子井戸層の膜厚の精密制御を達成し、超薄膜シリコン量子井戸を含む絶縁ゲート構造の実現に成功した。 (3)上述のプロセスをInP表面に適用した場合、最適なECRプラズマによる部分窒化条件においては、フェルミ準位ピンニングを大幅に緩和し、界面準位密度の最小値として2x10^<10>cm^<-2>eV^<-1>を得た。この値は、非酸化物ゲートのInP MIS構造としては、これまでで最小の値である。 (4)さらに、超薄膜シリコン量子井戸を含む新しい絶縁ゲート構造を用いて試作したInP MISFETは、良好なゲート制御特性、高い実効移動度とともに、通電時間10^4秒間後のドレイン電流の変動が1.9%という高い動作安定性を示した。

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