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Last Updated :2024/07/25

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Master

Affiliation (Master)

  • Research Center for Integrated Quantum Electronics

Affiliation (Master)

  • Research Center for Integrated Quantum Electronics

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Profile and Settings

Degree

  • Ph.D（2000 Hokkaido University）

Profile and Settings

  • Name (Japanese)

    Ikebe

  • Name (Kana)

    Masayuki

  • Name

    200901051850424987

Achievement

Research Interests

  • イメージセンサ   画像処理   生体模擬   局所演算   RF CMOS   集積化センサ   発振回路   ネットワーク   センサネットワーク   量子集積ハードウェア   

Research Areas

  • Informatics / Intelligent informatics
  • Nanotechnology/Materials / Crystal engineering
  • Nanotechnology/Materials / Applied materials
  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electronic devices and equipment
  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electric/electronic material engineering
  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Communication and network engineering

Research Experience

  • 2018 - Today 北海道大学量子集積エレクトロニクス研究センター 教授
  • 2014 - Today 東京大学 大規模集積システム設計教育センター 協力研究員
  • 2021 - 2023/11 北海道大学病院 次世代遠隔医療システム開発センター
  • 2004 - 2018 Hokkaido University
  • 2000 - 2006 大日本印刷株式会社半導体製品研究所
  • 2002 - 2003 Toyohashi University of Technology
  • 1997/04 - 2000/03 北海道大学大学院 電子情報工学専攻 博士課程

Published Papers

  • Prasoon Ambalathankandy, Yafei Ou, Sae Kaneko, Masayuki Ikebe
    Color and Imaging Conference 31 (1) 55 - 60 2023/11/13
  • Haolin Wang, Yafei Ou, Wanxuan Fang, Prasoon Ambalathankandy, Naoto Goto, Gen Ota, Taichi Okino, Jun Fukae, Kenneth Sutherland, Masayuki Ikebe, Tamotsu Kamishima
    Computerized medical imaging and graphics : the official journal of the Computerized Medical Imaging Society 108 102273 - 102273 2023/09 
    Rheumatoid arthritis (RA) is a chronic autoimmune inflammatory disease that leads to progressive articular destruction and severe disability. Joint space narrowing (JSN) has been regarded as an important indicator for RA progression and has received significant attention. Radiology plays a crucial role in the diagnosis and monitoring of RA through the assessment of joint space. A new framework for monitoring joint space by quantifying joint space narrowing (JSN) progression through image registration in radiographic images has emerged as a promising research direction. This framework offers the advantage of high accuracy; however, challenges still exist in reducing mismatches and improving reliability. In this work, we utilize a deep intra-subject rigid registration network to automatically quantify JSN progression in the early stages of RA. In our experiments, the mean-square error of the Euclidean distance between the moving and fixed images was 0.0031, the standard deviation was 0.0661 mm and the mismatching rate was 0.48%. Our method achieves sub-pixel level accuracy, surpassing manual measurements significantly. The proposed method is robust to noise, rotation and scaling of joints. Moreover, it provides misalignment visualization, which can assist radiologists and rheumatologists in assessing the reliability of quantification, exhibiting potential for future clinical applications. As a result, we are optimistic that our proposed method will make a significant contribution to the automatic quantification of JSN progression in RA. Code is available at https://github.com/pokeblow/Deep-Registration-QJSN-Finger.git.
  • Haolin Wang, Yafei Ou, Wanxuan Fang, Prasoon Ambalathankandy, Naoto Goto, Gen Ota, Taichi Okino, Jun Fukae, Kenneth Sutherland, Masayuki Ikebe, Tamotsu Kamishima
    Computerized Medical Imaging and Graphics 108 102273 - 102273 0895-6111 2023/09
  • Taichi Okino, Yafei Ou, Masayuki Ikebe, Kenichi Tamura, Kenneth Sutherland, Jun Fukae, Kazuhide Tanimura, Tamotsu Kamishima
    JAPANESE JOURNAL OF RADIOLOGY 41 (5) 510 - 520 1867-1071 2023/05 
    Purpose We have developed an in-house software equipped with partial image phase-only correlation (PIPOC) which can automatically quantify radiographic joint space narrowing (JSN) progression. The purpose of this study was to evaluate the software in phantom and clinical assessments. Materials and methods In the phantom assessment, the software's performance on radiographic images was compared to the joint space width (JSW) difference using a micrometer as ground truth. A phantom simulating a finger joint was scanned underwater. In the clinical assessment, 15 RA patients were included. The software measured the radiological progression of the finger joints between baseline and the 52nd week. The cases were also evaluated with the Genant-modified Sharp score (GSS), a conventional visual scoring method. We also quantitatively assessed these joints' synovial vascularity (SV) on power Doppler ultrasonography (0, 8, 20 and 52 weeks). Results In the phantom assessment, the PIPOC software could detect changes in JSN with a smallest detectable difference of 0.044 mm at 0.1 mm intervals. In the clinical assessment, the JSW change of the joints with GSS progression detected by the software was significantly greater than those without GSS progression (p = 0.004). The JSW change of joints with positive SV at baseline was significantly higher than those with negative SV (p = 0.024). Conclusion Our in-house software equipped with PIPOC can automatically and quantitatively detect slight radiographic changes of JSW in clinically inactive RA patients.
  • Taichi Okino, Yafei Ou, Masayuki Ikebe, Kenichi Tamura, Kenneth Sutherland, Jun Fukae, Kazuhide Tanimura, Tamotsu Kamishima
    Japanese journal of radiology 41 (5) 510 - 520 2023/05 
    PURPOSE: We have developed an in-house software equipped with partial image phase-only correlation (PIPOC) which can automatically quantify radiographic joint space narrowing (JSN) progression. The purpose of this study was to evaluate the software in phantom and clinical assessments. MATERIALS AND METHODS: In the phantom assessment, the software's performance on radiographic images was compared to the joint space width (JSW) difference using a micrometer as ground truth. A phantom simulating a finger joint was scanned underwater. In the clinical assessment, 15 RA patients were included. The software measured the radiological progression of the finger joints between baseline and the 52nd week. The cases were also evaluated with the Genant-modified Sharp score (GSS), a conventional visual scoring method. We also quantitatively assessed these joints' synovial vascularity (SV) on power Doppler ultrasonography (0, 8, 20 and 52 weeks). RESULTS: In the phantom assessment, the PIPOC software could detect changes in JSN with a smallest detectable difference of 0.044 mm at 0.1 mm intervals. In the clinical assessment, the JSW change of the joints with GSS progression detected by the software was significantly greater than those without GSS progression (p = 0.004). The JSW change of joints with positive SV at baseline was significantly higher than those with negative SV (p = 0.024). CONCLUSION: Our in-house software equipped with PIPOC can automatically and quantitatively detect slight radiographic changes of JSW in clinically inactive RA patients.
  • Yafei Ou, Prasoon Ambalathankandy, Ryunosuke Furuya, Seiya Kawada, Tianyu Zeng, Yujie An, Tamotsu Kamishima, Kenichi Tamura, Masayuki Ikebe
    IEEE JOURNAL OF BIOMEDICAL AND HEALTH INFORMATICS 27 (1) 53 - 64 2168-2194 2023/01 
    Rheumatoid arthritis (RA) is a chronic autoimmune disease that primarily affects peripheral synovial joints, like fingers, wrists and feet. Radiology plays a critical role in the diagnosis and monitoring of RA. Limited by the current spatial resolution of radiographic imaging, joint space narrowing (JSN) progression of RA for the same reason above can be less than one pixel per year with universal spatial resolution. Insensitive monitoring of JSN can hinder the radiologist/rheumatologist from making a proper and timely clinical judgment. In this paper, we propose a novel and sensitive method that we call partial image phase-only correlation which aims to automatically quantify JSN progression in the early RA. The majority of the current literature utilizes the mean error, root-mean-square deviation and standard deviation to report the accuracy at pixel level. Our work measures JSN progression between a baseline and its follow-up finger joint images by using the phase spectrum in the frequency domain. Using this study, the mean error can be reduced to 0.0130 mm when applied to phantom radiographs with ground truth, and 0.0519 mm standard deviation for clinical radiography. With the sub-pixel accuracy far beyond usual manual measurements, we are optimistic that the proposed work is a promising scheme for automatically quantifying JSN progression.
  • Ou, Yafei, Ambalathankandy, Prasoon, Furuya, Ryunosuke, Kawada, Seiya, Zeng, Tianyu, An, Yujie, Kamishima, Tamotsu, Tamura, Kenichi, Ikebe, Masayuki
    IEEE Journal of Biomedical and Health Informatics 27 (1) 53 - 64 2168-2194 2023/01 
    Rheumatoid arthritis (RA) is a chronic autoimmune disease that primarily affects peripheral synovial joints, like fingers, wrists and feet. Radiology plays a critical role in the diagnosis and monitoring of RA. Limited by the current spatial resolution of radiographic imaging, joint space narrowing (JSN) progression of RA for the same reason above can be less than one pixel per year with universal spatial resolution. Insensitive monitoring of JSN can hinder the radiologist/rheumatologist from making a proper and timely clinical judgment. In this paper, we propose a novel and sensitive method that we call partial image phase-only correlation which aims to automatically quantify JSN progression in the early RA. The majority of the current literature utilizes the mean error, root-mean-square deviation and standard deviation to report the accuracy at pixel level. Our work measures JSN progression between a baseline and its follow-up finger joint images by using the phase spectrum in the frequency domain. Using this study, the mean error can be reduced to 0.0130 mm when applied to phantom radiographs with ground truth, and 0.0519 mm standard deviation for clinical radiography. With the sub-pixel accuracy far beyond usual manual measurements, we are optimistic that the proposed work is a promising scheme for automatically quantifying JSN progression.
  • Yafei Ou, Prasoon Ambalathankandy, Ryunosuke Furuya, Seiya Kawada, Tianyu Zeng, Yujie An, Tamotsu Kamishima, Kenichi Tamura, Masayuki Ikebe
    IEEE journal of biomedical and health informatics 27 (1) 53 - 64 2023/01 
    Rheumatoid arthritis (RA) is a chronic autoimmune disease that primarily affects peripheral synovial joints, like fingers, wrists and feet. Radiology plays a critical role in the diagnosis and monitoring of RA. Limited by the current spatial resolution of radiographic imaging, joint space narrowing (JSN) progression of RA for the same reason above can be less than one pixel per year with universal spatial resolution. Insensitive monitoring of JSN can hinder the radiologist/rheumatologist from making a proper and timely clinical judgment. In this paper, we propose a novel and sensitive method that we call partial image phase-only correlation which aims to automatically quantify JSN progression in the early RA. The majority of the current literature utilizes the mean error, root-mean-square deviation and standard deviation to report the accuracy at pixel level. Our work measures JSN progression between a baseline and its follow-up finger joint images by using the phase spectrum in the frequency domain. Using this study, the mean error can be reduced to 0.0130 mm when applied to phantom radiographs with ground truth, and 0.0519 mm standard deviation for clinical radiography. With the sub-pixel accuracy far beyond usual manual measurements, we are optimistic that the proposed work is a promising scheme for automatically quantifying JSN progression.
  • Eiichi Sano, Masayuki Ikebe
    IEEE Transactions on Electromagnetic Compatibility 64 (4) 1052 - 1057 0018-9375 2022/08
  • Ou Y., Ambalathankandy P., Ikebe M., Takamaeda-Yamazaki S., Motomura M., Asai T.
    IEEE Transactions on Circuits and Systems for Video Technology Institute of Electrical and Electronics Engineers (IEEE) 32 (5) 2666 - 2686 1051-8215 2022/05/05 [Refereed][Not invited]
  • Yafei Ou, Prasoon Ambalathankandy, Ryunosuke Furuya, Seiya Kawada, Tamotsu Kamishima, Masayuki Ikebe
    2022 14TH BIOMEDICAL ENGINEERING INTERNATIONAL CONFERENCE (BMEICON 2022) 2334-3052 2022 
    Rheumatoid arthritis is a form of autoimmune disease characterized by synovitis that can ultimately cause joint deformities and impaired functioning. The cartilage destruction is one of the most important indicators for diagnosis and treatment of Rheumatoid arthritis, and it is radiographically manifested as joint space narrowing. In this study, we propose a joint location detection method and a sub-pixel accurate method for quantifying joint space narrowing progression with a joint angle correction. The proposed joint location detection method can detect the location of 14 joints from a given hand radiographic image, the error of 89.13% joints is less than 3 pixels (spatial resolution: 0.175 mm/pixel). In our previous works, we measured joint space narrowing progression between a baseline and its follow-up finger joint images by using partial image phase only correlation. We found that the inconsistency of joint angles may lead to characteristic mismatch and thus affect the accuracy of joint space narrowing quantification. In this work, we introduce rotation invariant phase only correlation in joint space narrowing quantification for joint angle correction. In our experiment, the improved quantification method can effectively manage the mismatch due to the inconsistency of joint angles.
  • Masayuki Ikebe, Prasoon Ambalathankandy, Yafei Ou
    ITE Transactions on Media Technology and Applications 10 (2) 27 - 51 2022
  • Prasoon Ambalathankandy, Yafei Ou, Masayuki Ikebe
    Journal of Electronic Imaging 30 (4) 2021
  • Aimi Taguchi, Shun Shishido, Yafei Ou, Masayuki Ikebe, Tianyu Zeng, Wanxuan Fang, Koichi Murakami, Toshikazu Ueda, Nobutoshi Yasojima, Keitaro Sato, Kenichi Tamura, Kenneth Sutherland, Nozomi Oki, Ko Chiba, Kazuyuki Minowa, Masataka Uetani, Tamotsu Kamishima
    Journal of Digital Imaging 34 (1) 96 - 104 2021
  • Prasoon Ambalathankandy, Masayuki Ikebe, Takayuki Yoshida, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai
    IEEE Transactions on Circuits and Systems for Video Technology 30 (9) 3015 - 3028 2020
  • Yamamoto K., Ikebe M., Asai T., Motomura M., Takamaeda-Yamazaki S.
    IEICE Transactions on Information and Systems E102-D (12) 2295 - 2305 2019/12/01 [Refereed][Not invited]
  • Ando K., Ueyoshi K., Oba Y., Hirose K., Uematsu R., Kudo T., Ikebe M., Asai T., Takamaeda-Yamazaki S., Motomura M.
    IEICE Transactions on Information and Systems E102 (12) 2341 - 2353 2019/12/01 [Refereed][Not invited]
  • A study on a low power optimization algorithm for an edge-AI Device
    Kaneko T., Orimo K., Hida I., Takamaeda-Yamazaki S., Ikebe M., Motomura M., Asai T.
    Nonlinear Theory and Its Applications E10-N (4) 373 - 389 2019/10/01 [Refereed][Not invited]
  • Kaneko T., Ikebe M., Takamaeda-Yamazaki S., Motomura M., Asai T.
    Journal of Signal Processing 23 (4) 151 - 154 2019/07/20 [Refereed][Not invited]
  • Shota Hiramatsu, Masayuki Ikebe, Eiichi Sano
    Analog Integrated Circuits and Signal Processing 100 (1) 23 - 29 1573-1979 2019/07/15 
    The switching noise generated in digital circuits propagates through conductive silicon substrate to analog circuits in a mixed-signal CMOS LSI. Substrate noise coupling may degrade the performance of the analog circuits, and may result in a fault operation of the mixed-signal LSI in the worst-case. In this paper, the substrate noise coupling between the clock recovery circuit and the input port of the envelop detector in a low-power wake-up receiver (WuRx) was investigated experimentally. The propagation path of the substrate noise coupling was clarified by comparing the experimental results with the circuit simulations on the basis of an equivalent circuit model. The design of the WuRx was modified on the basis of the findings to suppress the substrate noise coupling. The fabricated WuRx successfully operated a 100-kbps PWM signal with a carrier frequency of 2.4 GHz, and the effectiveness of the noise coupling suppression recipe was confirmed.
  • Wideband terahertz imaging pixel with a small on-chip antenna in 180 nm CMOS
    Y. Kanazawa, S. Yokoyama, S. Hiramatsu, E. Sano, T. Ikegami, Y. Takida, P. Ambalathanakandy, H. Minamide, M. Ikebe
    JJAP 58 2019/04 [Refereed][Not invited]
  • Sayuri Yokoyama, Masayuki Ikebe, Yuri Kanazawa, Takahiro Ikegami, Prasoon Ambalathankandy, Shota Hiramatsu, Eiichi Sano, Yuma Takida, Hiroaki Minamide
    Digest of Technical Papers - IEEE International Solid-State Circuits Conference 2019- 108 - 110 0193-6530 2019/03/06 
    There are many compelling characteristics of signals in the terahertz band (100GHz to 10THz) located between the millimeter wave band and the infrared band. In particular, terahertz waves have higher spatial resolution than mm-waves. Moreover, they can transmit through various substances such as plastics, fibers and paper, and can detect hazardous substances. Because of these features, interest in terahertz applications such as security screening is rising. However, there is a paucity of low-cost terahertz detectors. The Si-CMOS process technology is low-cost and highly integratable with readout electronics and on-chip signal processors. A key consideration for many of the terahertz-detector technologies is the need for additional process steps to make them compatible with CMOS technologies [1]. Recent antenna-type pixel detectors have shown success in high-speed operation and do not require extra process steps [2] however, power consumption of each pixel and the sequential read-out architecture offsets the speed advantage.
  • Sayuri Yokoyama, Masayuki Ikebe, Yuri Kanazawa, Takahiro Ikegami, Prasoon Ambalathankandy, Shota Hiramatsu, Eiichi Sano, Yuma Takida, Hiroaki Minamide
    IEEE International Solid- State Circuits Conference(ISSCC) 43 (11(IST2019 12-22)) 108 - 110 1342-6893 2019
  • Yafei Ou, Prasoon Ambalathankandy, Takeshi Shimada, Tamotsu Kamishima, Masayuki Ikebe
    16th IEEE International Symposium on Biomedical Imaging(ISBI) 1183 - 1187 2019
  • Prasoon Ambalathankandy, Yafei Ou, Jyotsna Kochiyil, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
    2019 Digital Image Computing: Techniques and Applications(DICTA) 1 - 8 2019
  • Miho Yamada, Shun Ono, Yasuo Arai, Ikuo Kurachi, Toru Tsuboyama, Masayuki Ikebe, Makoto Motoyoshi
    2019 International 3D Systems Integration Conference (3DIC)(3DIC) 1 - 4 2019
  • Ambalathankandy P, Takamaeda-Yamazaki S, Motomura M, Asai T, Ikebe M, Kusano H
    Microprocessors and Microsystems 60 21 - 31 2018/12/01 [Refereed][Not invited]
  • Quantization error-based regularization for hardware-aware neural network training
    Hirose K, Uematsu R, Ando K, Ueyoshi K, Ikebe M, Asai T, Motomura M, Takamaeda-Yamazaki S
    Nonlinear Theory and Its Applications E9-N (4) 453 - 465 2018/10/01 [Refereed][Not invited]
  • CMOS terahertz imaging pixel with a VCO-based ADC
    S. Yokoyama, M. Ikebe, Y. Kanazawa, T. Ikegami, P. Ambalathankandy, S. Hiramatsu, E. Sano, Y. Takida, H. Minamide
    2018 Int'l Conf. Solid State Devices and Materials 2018/09 [Refereed][Not invited]
  • CMOS terahertz imaging pixel with a wideband on-chip antenna
    Y. Kanazawa, S. Hiramatsu, E. Sano, S. Yokoyama, P. Ambalathankandy, M. Ikebe
    2018 43rd International Conference on Infrared, Millimeter and Terahertz Waves (IRMMW-THz) 2018/09 [Refereed][Not invited]
  • Ando K, Ueyoshi K, Orimo K, Yonekawa H, Sato S, Nakahara H, Takamaeda-Yamazaki S, Ikebe M, Asai T, Kuroda T, Motomura M
    IEEE Journal of Solid-State Circuits 53 (4) 983 - 994 2018/04/01 [Refereed][Not invited]
  • 平松正太, 池辺 将之, 佐野 栄一
    電子情報通信学会論文誌 J101-C (3) 147 - 155 1881-0217 2018/03 [Refereed][Invited]
  • Tanibata A, Schmid A, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T
    Complexity 2018 3618621-1 - 11 2018/02/15 [Refereed][Not invited]
  • Prasoon Ambalathankandy, Takeshi Shimada, Shinya Takamaeda, Masato Motomura, Tetsuya Asai, Masayuki Ikebe
    IEEE Visual Communications and Image Processing(VCIP) 1 - 4 2018
  • Takumi Kudo, Kodai Ueyoshi, Kota Ando, Kazutoshi Hirose, Ryota Uematsu, Yuka Oba, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
    12th IEEE International Symposium on Embedded Multicore/Many-core Systems-on-Chip(MCSoC) 237 - 243 2018
  • Takeshi Shimada, Masayuki Ikebe, Prasoon Ambalathankandy, Shinya Takamaeda-Yamazaki, Masato Motomura, Tetsuya Asai
    2018 IEEE International Conference on Acoustics, Speech and Signal Processing(ICASSP) 1842 - 1846 2018
  • Kota Ando, Kodai Ueyoshi, Yuka Oba, Kazutoshi Hirose, Ryota Uematsu, Takumi Kudo, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
    International Conference on Field-Programmable Technology(FPT) 6 - 13 2018
  • Equivalent circuit analysis of artificial dielectric layers
    E. Sano, M. Ikebe
    Progress In Electromagnetics Research M 60 85 - 92 2017/09 [Refereed][Not invited]
  • Tsuji T, Ikebe M, Takamaeda-Yamazaki S, Motomura M, Asai T
    Journal of Signal Processing 信号処理学会 21 (4) 191 - 194 2017/07/20 [Refereed][Not invited]
     
    We propose real-time camera position and posture estimation with six degrees of freedom (6-DoF) based on local patches of an image sequence. Our method alternately performs camera motion calculation and depth map reconstruction. Using the reconstructed depth map on only edge regions of images, our estimation method was 30% faster than that based on all pixels and achieved robust motion tracking compared with the feature-points-based method.
  • Ando K, Takamaeda-Yamazaki S, Ikebe M, Asai T, Motomura M
    Circuits and Systems 8 (6) 149 - 170 2017/06/29 [Refereed][Not invited]
  • Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T
    Circuits and Systems 8 (5) 134 - 147 2017/05/19 [Refereed][Not invited]
  • Hida I, Takamaeda-Yamazaki S, Ikebe M, Motomura M, Asai T
    Nonlinear Theory and Its Applications E8-N (3) 235 - 245 2017/05/19 [Refereed][Not invited]
  • Kosuke Wakita, Eiichi Sano, Masayuki Ikebe, Stevanus Arnold, Taiichi Otsuji, Yuma Takida, Hiroaki Minamide
    FUNDAMENTAL AND APPLIED PROBLEMS OF TERAHERTZ DEVICES AND TECHNOLOGIES 58 (3&4) 33 - 41 1793-1274 2017 [Refereed][Not invited]
     
    A CMOS cascode amplifier, biased near the threshold voltage of a MOSFET, for terahertz direct detection is proposed. A CMOS terahertz imaging circuit ( size: 250 x 180 mu m) is designed and fabricated on the basis of low-cost 180-nm CMOS process technology. The imaging circuit consists of a microstrip patch antenna, an impedance-matching circuit, and a direct detector. It achieves a responsivity of 51.9 kV/W at 0.915 THz and a noise equivalent power (NEP) of 358 pW/Hz(1/2) at a modulation frequency of 31 Hz. NEP is estimated to be reduced to 42 pW/Hz(1/2) at 100 kHz. These results suggest that cost-efficient terahertz imaging is possible in the near future.
  • Kazutoshi Hirose, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Shinya Takamaeda-Yamazaki
    Artificial Intelligence XXXIV - 37th SGAI International Conference on Artificial Intelligence 137 - 142 2017
  • Haruyoshi Yonekawa, Shimpei Sato, Hiroki Nakahara, Kota Ando, Kodai Ueyoshi, Kazutoshi Hirose, Kentaro Orimo, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    IEEE 60th International Midwest Symposium on Circuits and Systems(MWSCAS) 116 - 119 2017
  • Yuhan Fu, Masayuki Ikebe, Takeshi Shimada, Tetsuya Asai, Masato Motomura
    18th International Symposium on Quality Electronic Design(ISQED) 397 - 402 2017
  • Kodai Ueyoshi, Kota Ando, Kentaro Orimo, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    2017 International Joint Conference on Neural Networks(IJCNN) 2510 - 2516 2017
  • Kazutoshi Hirose, Ryota Uematsu, Kota Ando, Kentaro Orimo, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Shinya Takamaeda-Yamazaki, Masato Motomura
    Fifth International Symposium on Computing and Networking(CANDAR) 291 - 297 2017
  • Kasho Yamamoto, Weiqiang Huang, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    Proceedings of the 8th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies(HEART) 3 - 6 2017
  • Aoi Tanibata, Alexandre Schmid, Shinya Takamaeda-Yamazaki, Masayuki Ikebe, Masato Motomura, Tetsuya Asai
    27th International Conference on Field Programmable Logic and Applications(FPL) 1 - 1 2017
  • Shinya Takamaeda-Yamazaki, Kodai Ueyoshi, Kota Ando, Ryota Uematsu, Kazutoshi Hirose, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    2017 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 1045 - 1051 2017
  • Eiichi Sano, Takehito Watanuki, Masayuki Ikebe, Bunshi Fugetsu
    Japanese Journal of Applied Physics 56 (9) 1347-4065 2017 [Refereed][Not invited]
     
    The addition of carbon nanotubes (CNTs) in polyacrylonitrile (PAN) precursor is an effective way to increase the electrical conductivity of derived carbon fibers. The electrical conductivity of 4.9 ' 104 S/m for a PAN-based carbon fiber at room temperature increases to 9.4 ' 104 S/m by adding 0.5 wt % CNTs. The measured conductivity for both PAN/CNT- and PAN-based carbon fibers monotonically increases as the temperature increases from 10 and 300 K. An attempt to explain the measured temperature dependences of electrical conductivities by various carrier transport models showed that a simple two-carrier model can give reasonable electron and hole mobility. A monopole antenna fabricated with PAN/CNT-based carbon fibers shows a gain of 2.3 dBi at 2.4 GHz, which is only 0.2 dB smaller than that of a reference (Cu-wire) monopole antenna. This result suggests the possibility of using PAN/CNT-based carbon fibers as antenna elements.
  • Eiichi Sano, Masayuki Ikebe
    Progress In Electromagnetics Research C 76 55 - 62 1530-9681 2017 [Refereed][Not invited]
     
    The electromagnetic characteristics of two-dimensional composite right/left-handed transmission lines (2D CRLH TLs) were investigated for the normal incidence of plane waves. The measured characteristic impedance and reflection phases exhibited resonant high impedance properties (equivalent to zero reflection phase) at a frequency within the left-handed mode for one-dimensional CRLH TL. An equivalent circuit was proposed to explain the measured characteristics. The relationship between the resonant frequency and the circuit parameters for 2D CRLH TLs was clarified by deriving an approximate equation for the resonant frequency.
  • Masayuki Ikebe, Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Daisuke Uchida, Yasuhiro Take, Tadahiro Kuroda, Masato Motomura
    2017 22ND ASIA AND SOUTH PACIFIC DESIGN AUTOMATION CONFERENCE (ASP-DAC) 7 - 8 2153-6961 2017 [Refereed][Not invited]
     
    1,000 fps motion vector (MV) estimation and classification engine for highspeed computational imaging in a 3D stacked imager/processor module is proposed, prototyped, assembled, and also tested. The module features 1) ThruChip interfaces for high fps image transfer, 2) orders of magnitude more area/power efficient MV estimation architecture compared to conventional ones, and 3) a cognitive classification scheme employed on MV patterns, enabling the classification of moving objects not possible in conventional proposals.
  • 脇田幸典, 池辺将之, ARNOLD Stevanus, 尾辻泰一, 瀧田佑馬, 南出泰亜, 佐野栄一
    電子情報通信学会技術研究報告 ED2016-83 (375(ED2016 80-95)) 17 - 22 0913-5685 2016/12 [Not refereed][Not invited]
  • Yamamoto K, Ikebe M, Asai T, Motomura M
    Circuits and Systems 7 (10) 3299 - 3309 2016/08/25 [Refereed][Not invited]
  • Ikebe M, Uchida D, Take Y, Someya M, Chikuda S, Matsuyama K, Asai T, Kuroda T, Motomura M
    ITE Transactions on Media Technology and Applications 一般社団法人 映像情報メディア学会 4 (2) 142 - 148 2186-7364 2016/04/01 [Refereed][Not invited]
     
    This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming Time to Digital Converter (TDC) used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.
  • Akira Mizuno, Masayuki Ikebe
    2016 IEEE International Conference on Acoustics, Speech and Signal Processing(ICASSP) 1671 - 1675 2016
  • Itaru Hida, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    2016 IEEE Asia Pacific Conference on Circuits and Systems(APCCAS) 297 - 300 2016
  • Tetsuya Asai, Masafumi Mori, Toshiyuki Itou, Yasuhiro Take, Masayuki Ikebe, Tadahiro Kuroda, Masato Motomura
    ESSCIRC CONFERENCE 2016 105 - 108 1930-8833 2016 [Refereed][Not invited]
     
    1,000 fps motion vector estimation and classification engine for highspeed computational imaging in a 3D stacked imager/processor module is proposed, prototyped, assembled, and also tested. The module features 1) ThruChip interfaces for high fps image transfer, 2) orders of magnitude more area/power efficient motion vector estimation architecture compared to conventional ones, and 3) a cognitive classification scheme employed on motion vector patterns, enabling the classification of moving objects not possible in conventional proposals.
  • Hotaka Kusano, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    2016 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG16) 1 - 6 2325-6532 2016 [Refereed][Not invited]
     
    The demand for light-weight and high-speed super resolution (SR) techniques is growing because super high-resolution displays, such as 4K/8K ultra high definition televisions (UHDTVs), have become common. We here propose an SR method using over up-sampling and anti-aliasing where no iteration process is required-unlike with conventional SR methods. Our method is able to attenuate jaggies in the edge of an enlarged image and does not need to preserve the entire enlarged image. Therefore, this method is suitable for hardware implementation, and the architecture requires five line buffers only (in the memory section). We implemented the proposed method on a field programmable gate array (FPGA) and demonstrated HDTV-to-4K and-8K SR processing in real time (60 frames per second).
  • Kosuke Wakita, Eiichi Sano, Masayuki Ikebe, Stevanus Arnold, Taiichi Otsuji, Yuma Takida, Hiroaki Minamide
    2016 21ST INTERNATIONAL CONFERENCE ON MICROWAVE, RADAR AND WIRELESS COMMUNICATIONS (MIKON) 2016 [Refereed][Not invited]
     
    Using terahertz waves for imaging is gaining increased interest. A CMOS cascode amplifier biased near the threshold voltage of a MOSFET for terahertz direct detection is proposed. A test chip composed of 4x4 pixel CMOS terahertz imaging array is designed and fabricated on the basis of a low-cost 180-nm CMOS process technology. Each pixel consists of a microstrip patch antenna, an impedance-matching circuit, and the direct detector. The imaging pixels achieve a responsivity of 51.9 kV/W at 0.915 THz and noise equivalent power (NEP) of 358 pW/Hz(1/2) at modulation frequency of 31 Hz. NEP is estimated to be reduced to 33.5 pW/Hz(1/2) at 10 kHz. The imaging pixel occupies 250x180 mu m. These results suggest that cost-efficient terahertz imaging is possible in the near future.
  • Kentaro Orimo, Kota Ando, Kodai Ueyoshi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura
    2016 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS (RECONFIG16) 1 - 6 2325-6532 2016 [Refereed][Not invited]
     
    Deep learning is being widely used in various applications, and diverse neural networks have been proposed. A form of neural network, such as the novel feed-forward sequential memory network (FSMN), aims to forecast prospective data by extracting the time-series feature. FSMN is a standard feed-forward neural network equipped with time-domain filters, and it can forecast with out recurrent feedback. In this paper, we propose a field-programmable gate-array (FPGA) architecture for this model, and exhibit that the resource does not increase exponentially as the network scale increases.
  • D. Uchida, M. Ikebe, J. Motohisa, E. Sano
    J. Signal Processing 19 (6) 219 - 226 2015/11 [Refereed][Not invited]
  • Kazuki Hiraishi, Toshiki Wada, Keishi Kubo, Yutaro Otsu, Masayuki Ikebe, Eiichi Sano
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 83 (1) 1 - 9 0925-1030 2015/04 [Refereed][Not invited]
     
    Development of a low-power, small-size transmitter is needed for wireless sensor networks. An effective way to reduce power consumption is to reduce the operating time in a voltage-controlled oscillator. In this study, a 2.4 GHz on-off keying transmitter circuit is designed and implemented with an electrically small antenna using a left-handed transmission line. The transmitter circuit was fabricated with a standard 0.18 mu m CMOS technology, while the antenna was fabricated with a 3.0 x 4.5 cm printed circuit board, chip capacitors, and chip inductors. Measured output power was -6.8 dBm with a power consumption of 3.59 mW when the baseband signal was always "high". The power consumption was reduced to 1.96 mW for the baseband signal with a mark ratio of 0.5.
  • Mizuno Akira, Ikebe Masayuki
    ITE Transactions on Media Technology and Applications 一般社団法人 映像情報メディア学会 3 (4) 251 - 257 2186-7364 2015 
    We propose a bit-depth expansion (BDE) method targeting natural images. In the analog part of an imaging system, signal intensity fluctuations occur due to noise (e.g. thermal noise in the image sensor). After that, in the digital part, the intensities are rounded off to limited levels. The latter process, which is quantization, increases the intensity of fluctuation errors caused by stochastic resonance. These errors are viewed as false contour artifacts in the gradation region. Our goal was to obtain the original signal from the quantized noisy signal. We formulated a probabilistic model based on this quantization process, and successfully reconstructed smooth gradations from noisy contours. Subjective evaluation by voting clarified that the output image has higher quality.
  • Yuta Kimura, Masayuki Ikebe
    2015 IEEE International Conference on Image Processing(ICIP) 3911 - 3915 2015
  • IKEBE Masayuki, UCHIDA Daisuke, TAKE Yasuhiro, SOMEYA Makito, CHIKUDA Satoshi, MATSUYAMA Kento, ASAI Tetsuya, KURODA Tadahiro, MOTOMURA Masato
    ITE Technical Report 一般社団法人 映像情報メディア学会 39 (35(IST2015 43-56)) 17 - 20 1342-6893 2015 
    This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming TDC used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.
  • Masayuki Ikebe, Daisuke Uchida, Yasuhiro Take, Makito Someya, Satoshi Chikuda, Kento Matsuyama, Tetsuya Asai, Tadahiro Kuroda, Masato Motomura
    2015 SYMPOSIUM ON VLSI CIRCUITS (VLSI CIRCUITS) 82  2015 [Refereed][Not invited]
     
    This paper proposes 3D stacked module consisting of image sensor and digital logic dies connected through inductive coupling channels. Evaluation of a prototype module revealed radiation noise from the inductive coils to the image sensor is less than 0.4-LSB range along with ADC code, i.e., negligible. Aiming at high frame rate image sensor/processing module exploiting this attractive off-die interface, we also worked on resolving another throughput-limiter, namely power consuming TDC used in column parallel ADCs. Novel intermittent TDC operation scheme presented in this paper can reduce its power dissipation 57% from conventional ones.
  • Mori M, Itou T, Ikebe M, Asai T, Kuroda T, Motomura M
    Journal of Signal Processing 18 (4) 165 - 168 2014/07/30 [Refereed][Not invited]
  • 自動しきい値補償型Dickson Charge Pumpによる整流特性の効率化
    謝侃, 池辺将之, 本久順一, 佐野栄一
    映情学技報 38 (26) 61 - 64 2014/07 [Not refereed][Not invited]
  • 2.4 GHz帯プリバイアス型整流回路の試作と評価
    吉川知秀, 平石一貴, 和田敏輝, 池辺将之, 佐野栄一
    映情学技報 38 (26) 55 - 59 2014/07 [Not refereed][Not invited]
  • 間欠動作TDCを用いたシングルスロープADC構成の検討”
    染谷槙人, 内田大輔, 池辺将之, 本久順一, 佐野栄一
    映情学技報 38 (26) 51 - 54 2014/07 [Not refereed][Not invited]
  • Yutaro Otsu, Keishi Kubo, Masayuki Ikebe, Eiichi Sano
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 79 (2) 301 - 307 0925-1030 2014/05 [Refereed][Not invited]
     
    A 2.4 GHz rectifier operating in a region of low RF input power was developed. The rectifier has a cross-coupled bridge configuration and is driven by a differential RF input signal. Since a rectifier needs an RF signal higher than the threshold voltage of transistors, we introduced a pre-biasing circuit to compensate for the threshold voltage. A low-voltage digital circuit, subthreshold voltage regulator, and low-power level shifter were introduced for reducing the power consumption of the pre-biasing circuit and increasing the driving voltage for the switches at the same time. The circuit simulations revealed that the pre-biasing circuit was effective in a low RF input power region. However, the output voltage was degraded in a high power region. Then, we combined the pre-biased rectifier in parallel with a non-biased rectifier. Three types of rectifiers consisting of LC matching circuits, three-stage rectifier cells, and biasing circuits were designed and fabricated using a 0.18-mu m mixed signal/RF CMOS process with one poly and six metal layers. The fabricated pre-biased rectifier operated in a region of RF input power of less than -15 dBm, while the non-biased rectifier could not operate in this region. The parallel combination of pre-biased and non-biased rectifiers effectively solved the drawback of the pre-biased rectifier in a high RF input power region.
  • Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano, Akira Kondou
    JAPANESE JOURNAL OF APPLIED PHYSICS 53 (4) 04EE20-1 - 04EE20-6 0021-4922 2014/04 [Refereed][Not invited]
     
    We propose an inductorless common-mode rejection filter with a gyrator-C network for common-mode-noise reduction. By adopting a gyrator-C network and ladder structure, high-order and small filter circuits with active transformer operation were fabricated. The filter was designed and fabricated in a Taiwan Semiconductor Manufacturing Company (TSMC) 0.18 mu m CMOS process. This filter exhibited a CMRR of 80 dB, output noise voltage of 103 nV/Hz(1/2), third-order input intercept point of 8.8 dBm at 1 MHz operation, and cutoff frequency of under 6 MHz. The total power consumption was 14.8 mW with a 2.5 V supply, and the chip area was 0.7 x 0.4 mm(2). (C) 2014 The Japan Society of Applied Physics
  • Daisuke Uchida, Masayuki Ikebe, Junichi Motohisa, Eiichi Sano
    2014 21ST IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS (ICECS) 770 - 773 2014 [Refereed][Not invited]
     
    We propose a single-slope ADC with an intermittent operational time-to-digital converter (TDC). Applying an n-bit TDC that uses a multi-phase-clock signal reduced the conversion time by a factor of 2(n), achieved timing consistency, and realized robust meta-stability. However, since a TDC needs to operate continuously, it required a large dissipation power. In this study, we focus on generating the PWM signal of a single-slope ADC and apply a scheme for limiting the TDC operation period in order to reduce TDC power dissipation. We designed and fabricated a 12-bit ADC, which consists of a 6-bit TDC and 6-bit-single-slope ADC, by using a 0.18-mu m CMOS process. The ADC, at 100 kS/s, consumes 5.5 mu W from a 1-V supply. Its INL and DNL were -1.9/ +1.9 LSB and -0.8/+0.5 LSB, respectively.
  • CMOS common-mode filter with gyrator-C network
    D. Uchida, M. Ikebe, J. Motohisa, E. Sano, A. Kondou
    Int'l Conf. Solid State Devices and Materials 886 - 887 2013/09 [Refereed][Not invited]
  • Sanada Y, Ohira T, Chikuda S, Igarashi M, Ikebe M, Asai T, Motomura M
    Journal of Signal Processing 17 (4) 111 - 114 2013/07/30 [Refereed][Not invited]
  • メタマテリアルアンテナを用いた低電力小型送信モジュール
    平石一貴, 和田敏輝, 久保圭史, 大津雄太郎, 池辺将之, 佐野栄一
    映情学技報 37 (29) 63 - 68 2013/07 [Not refereed][Not invited]
  • Kazuhiro Takahagi, Hiromichi Matsushita, Tomoki Iida, Masayuki Ikebe, Yoshihito Amemiya, Eiichi Sano
    ANALOG INTEGRATED CIRCUITS AND SIGNAL PROCESSING 75 (2) 199 - 205 0925-1030 2013/05 [Refereed][Not invited]
     
    We developed a wake-up receiver comprised of subthreshold CMOS circuits. The proposed receiver includes an envelope detector, a high-gain baseband amplifier, a clock and data recovery (CDR) circuit, and a wake-up signal recognition circuit. The drain nonlinearity in the subthreshold region effectively detects the baseband signal with a microwave carrier. The offset cancellation method with a biasing circuit operated by the subthreshold produces a high gain of more than 100 dB for the baseband amplifier. A pulse-width modulation (PWM) CDR drastically reduces the power consumption of the receiver. A 2.4-GHz detector, a high-gain amplifier and a PWM clock recovery circuit were designed and fabricated with 0.18-mu m CMOS process with one poly and six metal layers. The fabricated detector and high-gain amplifier achieved a sensitivity of -47.2 dBm while consuming only 6.8 mu W from a 1.5 V supply. The fabricated clock recovery circuit operated successfully up to 500 kbps.
  • Mizuno Akira, Igarashi Masaki, Ikebe Masayuki
    The Journal of the Institute of Television Engineers of Japan The Institute of Image Information and Television Engineers 67 (8) J326 - J333 1342-6907 2013 
    A novel approach for bit-depth expansion is proposed. When displaying a low bit-depth image on a monitor, false contour artifacts tend to appear in the gradation region. Such false contours seriously degrade the image quality. Reconstructing smooth gradations from false contours is crucial yet it remains difficult problem for 2D images. The proposed method enables the 2D interpolation problem to be separated into a 1D problem by using the Poisson equation. An output image with mathematically smooth gradations can be obtained.
  • Masaki Igarashi, Akira Mizuno, Masayuki Ikebe
    IEEE International Conference on Image Processing(ICIP) 1217 - 1221 2013
  • Toshiki Wada, Masayuki Ikebe, Eiichi Sano
    European Solid-State Circuits Conference 383 - 386 1930-8833 2013 [Refereed][Not invited]
     
    We present an ultra-low power 60-GHz band wake-up receiver (WuRx) designed and fabricated with a 0.18-μm RF CMOS low-cost technology. The WuRx consists of an envelope detector, high-gain baseband amplifier, and clock and data recovery (CDR) circuit. Subthreshold-operated offset-voltage cancellers are used in the detector and baseband amplifier. The envelope detector can operate for an on-off keying (OOK) signal with a low bit-rate baseband and 60-GHz carrier, which is higher than the cutoff frequency (fT) of 0.18-μm MOSFETs. This is because the fT defines the maximum operating bit-rate of the baseband signal. The CDR circuit is composed of a clock recovery circuit using an injection-locked oscillator, short pulse generator, and D-type flip/flop. The fabricated WuRx successfully operates with power consumption of only 9 μW from a 1.5-V supply and a high sensitivity of -68 dBm for a 350-kbit/s OOK signal with a 60-GHz carrier. The CMOS die area is 1.09 mm2. This is the first successful fabrication of a 60-GHz WuRx. © 2013 IEEE.
  • Katsuki Ohata, Yuki Sanada, Tetsuro Ogaki, Kento Matsuyama, Takanori Ohira, Satoshi Chikuda, Masaki Igarashi, Masayuki Ikebe, Tetsuya Asai, Masato Motomura, Tadahiro Kuroda
    2013 IEEE 20TH INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS, AND SYSTEMS (ICECS) 169 - 172 2013 [Refereed][Not invited]
     
    This paper presents a novel hardware-oriented stereo vision system based on 1-D cost aggregation. Many researchers have implemented hardware efficient stereo matching to realize real-time systems. However, such methods require a large amount of memory. We proposed a system that is based on a hardware-software hybrid architecture for memory reduction. It consisted of grayscale 1-D cost aggregation HW and 2-D disparity refinement SW. The 1-D processing reduced the size of RAM in our HW to 266 kb with an input image size of 1024 x 768. We achieved the average error rate for the Middlebury datasets as 6.24%. The processing time was 56.6 ms for the 1024 x 768 images and an average of 8.6 ms for the Middlebury datasets which have an average size of 400 x 380. Using the resolution of Middlebury datasets, our system can perform real-time depth-aided image processing.
  • K. Kim, M. Ikebe, J. Motohisa, E. Sano
    IEEE International Conference on Electronics, Circuits, and Systems 512 - 515 2012/12 [Refereed][Not invited]
  • インターリーブ動作による高速ランプ波形発生器
    内田大輔, 近藤 亮, 池辺将之, 本久順一, 佐野栄一
    LSIとシステムのワークショップ2012 228 - 229 2012/05 [Not refereed][Not invited]
  • 60GHz帯低電力直接検波回路
    和田敏輝, 高萩和宏, 池辺将之, 雨宮好仁, 佐野栄一
    LSIとシステムのワークショップ2012 255 - 257 2012/05 [Not refereed][Not invited]
  • Igarashi Masaki, Ikebe Masayuki, Shimoyama Sohsuke, Motohisa Junichi
    Nonlinear Theory and Its Applications, IEICE 一般社団法人 電子情報通信学会 3 (2) 222 - 232 2185-4106 2012 
    We propose a constant-time algorithm for a bilateral filter. Bilateral filter can be converted into the operation of three-dimensional (3D) convolution. By using recursive moving sum, we can reduce the number of calculations needed to construct a pseudo-Gaussian filter. Applying one-dimensional Gaussian filter to the 3D convolution, we achieved a constant-time bilateral filter. We used a 3-GHz CPU without SIMD instructions, or multi-thread operations. We confirmed our proposed bilateral filter to be processed in constant time. In practical conditions, high PSNR values over 40 dB are obtained.
  • A. Kondou, M. Ikebe, J. Motohisa, Y. Amemiya, E. Sano
    IEEE International Conference on Electronics, Circuits, and Systems 326 - 329 2011/12 [Refereed][Not invited]
  • センサネットワークのための極低消費電力ウェイクアップ受信器
    高萩和宏, 松下拓道, 飯田智貴, 池辺将之, 雨宮好仁, 佐野栄一
    第24回 回路とシステムワークショップ 300 - 304 2011/08 [Refereed][Not invited]
  • 容量分圧動作を用いたsingle-slope A/D変換器
    金基秀, 池辺将之, 本久順一, 佐野栄一
    LSIとシステムのワークショップ2011 201 - 203 2011/05 [Not refereed][Not invited]
  • Masayuki Ikebe, Junichi Motohisa
    INTERNATIONAL SYMPOSIUM ON PHOTOELECTRONIC DETECTION AND IMAGING 2011: ADVANCES IN IMAGING DETECTORS AND APPLICATIONS 8194 0277-786X 2011 [Refereed][Not invited]
     
    We investigated a negative feedback method for adding functionality to a CMOS image sensor. Our sensor effectively uses the method to set any intermediate voltage into a photodiode capacitance while a pixel circuit is in motion. The negative feedback reset functions as a noise cancellation technique and can obtain intermediate image data during charge accumulation. As an above application, dynamic range compression is achieved by individually selecting pixels and by setting an intermediate processing and were able to output frame-difference images without frame buffers. The experimental results obtained with a chip fabricated using a 0.25-mu m CMOS process demonstrate that dynamic range compression and intra-frame motion detection are effective applications of negative feedback resetting.
  • M. Shin, M. Ikebe, J. Motohisa, E. Sano
    17th IEEE International Conference on Electronics, Circuits, and Systems 865 - 868 2010/12 [Refereed][Not invited]
  • Masaki Igarashi, Masayuki Ikebe, Sousuke Shimoyama, Kenta Yamano, Junichi Motohisa
    2010 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING 3301 - 3304 1522-4880 2010 [Refereed][Not invited]
     
    We propose a O(1) algorithm for bilateral filter with low memory usage. Bilateral filter can be converted into weighted histogram operation. Applying line buffers of column histograms, we can reduce the number of calculation needed to construct recursive center-weighted local histogram. Also our method have advantage in terms of memory requirements. We used a 2-GHz CPU with our method and achieved one million pixels per 0.5 sec operation and high PSNR over 40 dB without the need for temporary frame buffers or additional instructions (downsampling, SIMD instructions, or multi-thread operations).
  • Sohsuke Shimoyama, Masaki Igarashi, Masayuki Ikebe, Junichi Motohisa
    Proceedings of the International Conference on Image Processing(ICIP) 3153 - 3156 2009
  • Masayuki Ikebe, Daisuke Ueo, Kazuhiro Takahagi, Masaki Ohuno, Yusuke Takada, Eiichi Sano
    2009 16th IEEE International Conference on Electronics, Circuits and Systems, ICECS 2009 17 - 20 2009 [Refereed][Not invited]
     
    Transmitter, receiver antennas, and other components monolithically integrated with CMOS LSIs are in high demand as a means of reducin. The cost of wireless equipment. Foy the first step, an RF frontend (low-noise-amplifier [LNA] and mixer) has been designed for use i. The 3.1 to 10.6-GHz band compatible with multi-band OFDM UWB all group spectrum allocation. We clarif. The design methodology of antennas on lossy Si substrates. The RF circuits wit. The antenna were fabricated using a 0.18-m CMOS process. Measured total gain with 50-cm air interface is about -40 dB i. The above band. © 2009 IEEE.
  • Kazuhiro Takahagi, Masaki Ohno, Masayuki Ikebe, Eiichi Sano
    2009 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS 2009) 81 - 84 2009 [Refereed][Not invited]
     
    On-chip antennas are demanded to further lower the cost of wireless CMOS ICs. We placed an artificial dielectric layer (ADL) between an antenna and Si substrate to improve the antenna gain. A 3.1-10.6-GHz ultra-wideband inverted-F antenna with ADL as well as a low-noise amplifier were designed and fabricated using a 0.18-mu m mixed signal/RF CMOS process with one poly and six metal layers. A fairly good agreement between measured and calculated gain characteristics was obtained. Using the ADL achieved a 2-dB gain enhancement. Increasing the surface dielectric constant for the ADL is expected to further enhance gain.
  • Frequency and phase lock operation using clock-period comparator
    Y. Makihara, M. Ikebe, J. Motohisa, E. Sano
    Proc. of Intl. Symposium on Multimedia and Communication Technology (ISMAC) 241 - 244 2009/01 [Refereed][Not invited]
  • A 0.18um 3GHz true single phase clocking divider-by-3 circuit
    M. Ikebe, J. Motohisa, E. Sano
    2008 WSEAS Intl. Conf. on Circuits, Systems, Electronics, Control & Signal Processing 110 - 113 2008/12 [Refereed][Not invited]
  • Phase lock operation by clock-period comparison for all digital PLL
    Y. Makihara, M. Ikebe, J. Motohisa, E. Sano
    Intl. Symposium on Topical Problems of Nonlinear Wave Physics (NWP) 49 - 50 2008/07 [Refereed][Not invited]
  • The design of high frequency true single phase clocking divider-by-3 circuit
    M. Ikebe, Y. Takada, M. Ohuchi, J. Motohisa, E. Sano
    Int. J. Circuits, Systems and Signal processing 2 (3) 219 - 228 2008 [Refereed][Not invited]
  • Yukinobu Makihara, Masayuki Ikebe, Eiichi Sano
    IEICE TRANSACTIONS ON ELECTRONICS E90C (6) 1307 - 1310 1745-1353 2007/06 [Refereed][Not invited]
     
    For a digitally controlled phase-locked loop (PLL), we evaluate the use of a clock-period comparator (CPC). In this PLL, only the frequency lock operation should be performed; however, the phase lock operation is also simultaneously achieved by performing the clock-period comparison when the phases of the reference signal and the output signal approach each other. Theoretically a lock-up operation was conducted. In addition, we succeeded in digitizing a voltage controlled oscillator (VCO) with a linear characteristic. We confirmed a phase lock operation with a slight loop characteristic through SPICE simulation.
  • M. Ikebe, D. Ueo, H. Osabe, K. Inafune, E. Sano, M. Koutai, M. Ikeda, K. Mashiko
    TRANSDUCERS '07 & EUROSENSORS XXI, DIGEST OF TECHNICAL PAPERS, VOLS 1 AND 2 2007 [Refereed][Not invited]
     
    Transmitter, receiver antennas and sensors monolithically integrated with CMOS LSIs are strongly demanded as a means of reducing the cost of wireless equipment. As the first step, an RF front-end (low-noise-amplifier [LNA] and mixer) is designed for use in the 7-GHz band corresponding to multi-band OFDM UWB group3 spectrum allocation. We clarify the design methodology of antennas on lossy Si substrates. The RF front-end with the antenna was fabricated using a 0.18-mu m CMOS process. Measured conversion gain with 60-cm air interface is about -50 dB in the above band.
  • Masayuki Ikebe, Keita Saito
    IEICE Transactions on Electronics 89-C (11) 1662 - 1669 2006
  • Daisuke Ueo, Hiroshi Osabe, Koji Inafune, Masayuki Ikebe, Eiichi Sano, Masato Koutani, Masayuki Ikeda, Koichiro Mashiko
    2006 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATIONS, VOLS 1 AND 2 235 - 238 2006 [Refereed][Not invited]
     
    Transmitter and receiver antennas monolithically integrated with CMOS LSIs are strongly demanded for reducing the cost of wireless equipment. As the first step toward realizing high-performance antennas on lossy Si substrates, we clarify the design methodology and basic characteristics of inverted-F antennas used for the 7-GHz band corresponding to multi-band OFDM UWB group3 spectrum allocation. An inverted-F antenna along with a low-noise amplifier (LNA) are designed and fabricated using a 0.18-mu m mixed signal/RF CMOS process with one poly and six metal layers. Comparisons between measured and calculated antenna gain characteristics are made. Measured antenna gain is about -25 dB in the multi-band OFDM UWB group3 frequency band. Fairly good agreement between measured and designed gains is obtained by taking account of the real geometry of the fabricated chip.
  • Ikebe M, Asai T
    Journal of Robotics and Mechatronics 17 (4) 372 - 377 2005/08 [Refereed][Not invited]
  • Asai T, Ikebe M, Hirose T, Amemiya Y
    International Journal of Parallel, Emergent and Distributed Systems 20 (1) 57 - 68 2005/03 [Refereed][Not invited]
  • On-chip fixed-pattern-noise canceling with non-destructive intermediate readout circuitry for CMOS active-pixel sensors
    Kagaya R, Ikebe M, Asai T, Amemiya Y
    WSEAS Transactions on Circuits and Systems 3 (3) 477 - 479 2004/05 [Refereed][Not invited]
  • Masayuki Ikebe, Tetsuya Asai, Tetsuya Hirose, Yoshihito Amemiya
    Proceedings of 2004 IEEE Asia-Pacific Conference on Advanced System Integrated Circuits 406 - 409 2004 [Refereed][Not invited]
     
    We will describe a cellular-automaton (CA) LSI that extracts quadrilateral objects, such as box areas filled with the same pixel values, from binary images. We propose an efficient CA algorithm, based on the reaction-diffusion chemical systems model. Each cell in the proposed CA is implemented by a digital circuit called an elemental processor. The CA LSI is constructed by a large number of elemental processors operating in parallel. This parallel operation ensures fast and efficient object extraction when the number of cells (processing pixels) increases. When we assumed a 0.25-μm CMOS process with the proposed circuits, the total area of the elemental processor was approximately 5 by 5 μm2.
  • Kanazawa Y, Asai T, Ikebe M, Amemiya Y
    International Journal of Robotics and Automation 19 (4) 206 - 212 2004 [Refereed][Not invited]
  • Oya T, Takahashi Y, Ikebe M, Asai T, Amemiya Y
    Superlattices and Microstructures 34 (3-6) 253 - 258 2003/09 [Refereed][Not invited]
  • Asai T, Sunayama T, Amemiya Y, Ikebe M
    Japanese Journal of Applied Physics 公益社団法人 応用物理学会 40 (4B) 2585 - 2592 0021-4922 2001/04 [Refereed][Not invited]
     
    A neuron MOS ($\nu$MOS) vision chip was designed and fabricated for developing high-speed parallel image-processing systems based on cellular-automaton processing. The chip consists of cellular $\nu$MOS circuits that implement two fundamental functions in digital image processing: i) cleaning up noise in binary images and ii) detecting edges in the images, in addition to photosensing and image quantizing. Experimental results reveal that the fabricated chip successfully extracted edges from noisy inputs, which demonstrates the great potential of the $\nu$MOS vision chip in future image-processing applications.
  • Sunayama T, Ikebe M, Asai T, Amemiya Y
    Japanese Journal of Applied Physics 公益社団法人 応用物理学会 39 (4B) 2278 - 2286 0021-4922 2000/04 [Refereed][Not invited]
     
    Aiming at the development of high-speed image processors, we propose a cellular νMOS circuit that performs the processing of edge detection. The proposed circuit uses neuron MOS (νMOS) transistors for analog convolution operations with Gaussian-shaped kernel functions, which makes the circuit organization extremely simple as compared with that of conventional convolution circuits. Performances of the proposed circuit are evaluated by simulation program with integrated circuit emphasis (SPICE). The results show the usefulness of the cellular νMOS circuit in image-processing applications.
  • Masayuki Ikebe, Masamichi Akazawa, Yoshihito Amemiya
    Knowledge-Based Intelligent Electronic Systems 447 - 453 1998

MISC

Association Memberships

  • THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS   IEEE   

Research Projects

  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research
    Date (from‐to) : 2022/04 -2026/03 
    Author : 冨岡 克広, 池辺 将之, 本久 順一
  • 日本学術振興会：科学研究費助成事業 基盤研究(C)
    Date (from‐to) : 2021/04 -2024/03 
    Author : 神島 保, 池田 啓, 渥美 達也, 池辺 将之, 田村 賢一
     
    Genant-modified Sharpスコア（GSS）などの、関節リウマチ（RA）における関節腔狭小化（JSN）のX線スコアリング法は広く受け入れられているが、評価が主観的で煩雑である。そのため、関節裂隙幅（JSW）の変化を自動的に定量化できる部分位相限定相関（PIPOC）を備えたソフトウェアを開発した。本研究の目的は、ソフトウェアを用いてトシリズマブ治療下の関節リウマチ患者のJSN進行を検討することである。 トシリズマブで治療された39名のRA患者（女性35名）を対象とした。中手指節関節および近位指節間関節のＸ線学的進行は、0ヶ月および12ヶ月のGSSに従って評価された。 被験者の均質性を確保するために、ソフトウェア分析のベースラインでGSS = 0の関節をターゲットにした。 JSN進行測定用の社内ソフトウェアの成功率は96.8％（449/464）であった。ソフトウェアで1年間に定量化された手指関節のJSW変化は、GSS進行陽性群の方が陰性群よりも有意に大きかった（p = 0.02）。 PIPOC依存ソフトウェアは、1年間のトシリズマブ治療下の追跡期間中にRA患者のJSN進行を検出できる可能性がある。
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research
    Date (from‐to) : 2018/06 -2023/03 
    Author : 本村 真人, 浅井 哲也, 池辺 将之, 高前田 伸也
     
    DNNアーキテクチャ：単一のネットワーク重みを用いてビットスケーラブルな推論を可能とする手法であるProgressiveNNを提案した．CIFAR-100/ResNet18における評価で1ビット幅の推論精度を65%まで回復させることを確認した．結合重みを乱数に固定したまま結合を枝刈りしていくことで学習する新たなCNN構造(乱数重み固定CNN)の推論アーキテクチャ及びその学習手法の研究を進めた．並行して，低ビット量子化ニューラルネットワークの研究に取り組んだ。既提案のDither NNを一般化し、1b等の低ビット表現ニューラルネットワークの空間方向の自由度を活用する新たな活性化関数を開発した。 DNNの画像処理応用：カスコード型U-netにおいて、特にセンサに特有なポアソンノイズ除去ではタイリングが有効に働くことを見出した。また局所適応画像処理において、低解像度化DCNNによる空間物体の識別によって空間制御パラメータを操作する研究を進めた。 リザーバコンピューティング：原子スイッチが持つ非線形性および短期記憶能力（忘却能力）を活かすアーキテクチャを特徴とする原子スイッチリザーバを構築した。シミュレーション評価により物理レザバーとしては現在最高水準の精度と線形メモリ性能を持つことを示した（国際会議NCSP 2021の学生論文賞を受賞。Journal of Signal Processing誌に掲載決定）。 確率的コンピューティング：多層パーセプトロンのフォワード演算およびバックプロパゲーション演算回路の確率的動作回路の構築および検証が完了した。（1）非線形活性化関数の確率回路表現、（2）負の重み・演算の生物的手法による模擬と確率回路表現、および（3）前述の（1）（2）を理論的に組み込んだ新規バックプロパゲーションアルゴリズムの構築と確率回路表現が完了している（特許出願手続き中）．
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    Date (from‐to) : 2019/04 -2022/03 
    Author : Tomioka Katsuhiro
     
    In this research, we developed and explored heterogeneous integration of III-V nanowires heterogeneous for high-speed, low-power, and high-efficiency three-dimensional (3D) circuits application. a nanowire 3D-architecture revolutionized the existing planar integration paradigm, and created a new trend in next-generation electronics. We have created an ultra-efficient tunnel transistors driven by nanowatts based on a new Si/III-V nanowire junction and tunneling transport mechanism. These results would provided new design guidelines for three-dimensional circuit structures based on nanowire TFETs.
  • ポスト 5G に向けたマルチモーダル情報の効率的活用と触診・遠隔医療技術への応用
    NEDO：ポスト 5G 情報通信システム基盤強化研究開発事業
    Date (from‐to) : 2020 -2022 
    Author : 池辺将之 北海道大学付属病院 北海道大学大学院保健科学研究院 日本ユニシス株式会社 株式会社テクノフェイス
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    Date (from‐to) : 2018/04 -2021/03 
    Author : Ikebe Masayuki
     
    In the local tone mapping we have been working on, the parameters of this process can be defined as the control points for spatial deformation, and we have found that it is appropriate to use DCNN for low-resolution images to identify spatial objects and manipulate the spatial and global control parameters for local functions in the tone-control function of this method. In DCNN (using U-net), image segmentation by tiling was found to be effective, especially for noise reduction (Poisson noise). In the case of tiling, it was found that the PSNR value was maintained at 32 dB even for 11x11 image blocks and overlap 3 pixels.
  • SOI技術を用いた極低ノイズ・高速イメージングデバイスの研究
    文部科学省：科学研究費補助金（新学術領域）
    Date (from‐to) : 2013/04 -2019/03 
    Author : 川人 祥二
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research on Innovative Areas (Research in a proposed research area)
    Date (from‐to) : 2013/06 -2018/03 
    Author : Kawahito Shoji
     
    In this study, a high-sensitvity SOI(Silicon-on-insulator) pixelated radiation detector using a pinned depeleted diode structure (SOPIX-PDD) is proposed and its exellent performance is demonstrated with the design and implementation of the SOI semiconductor chips. The SOIPIX-PDD has a pinned p-well layer underneath the buried oxide (BOX) and a depleted channel under the pinned p-well for gathering signal carriers generated at an arbitrary position in the pixel. This structure allows us to realize reduced dark current generated at the Si-SiO2 (BOX) interface, high charge correction efficiency and low-noise carrier detection with the small detector capacitance. An X-ray energy spectrum at 5.9keV is sucessfully measured with the high resolution of 171eV (FWHM). A SOI-based lock-in pixel detector and time-to-digital converter for mass-spectroscopy are also developed.
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research on Innovative Areas (Research in a proposed research area)
    Date (from‐to) : 2013/06 -2018/03 
    Author : AWAZU Kunio, TOYODA Michisato, KAWAI Yosuke, HONDO Toshinobu, MATSUOKA Hisanori, ARAI Yasuo, FUJITA Yowichi, IKEBE Masayuki, TSURUMOTO Yuma, Nomura SHUSEI, KAWAI Hayato, IMOTO Eishi, OKAZAKI Ayane, MORIGUCHI Naoki, KANNEN Hiroki
     
    A rapid and high resolution molecular imaging device with stigmatic imaging mass spectrometry has been developed. Since a position and time sensitive ion detector is required for practical use of stigmatic imaging mass spectrometry, novel ion detector has been developed with a semiconductor pixel detector. Prototype ion detectors have been developed two times in FY2013, and one time per year from FY2014 to FY2017. Finally, an ion detector with 192 x 192 pixels in 13.75 x 15.3 mm2, its driving circuit, and control software have been developed in FY2017, and its operation at the target time resolution of 1 ns was confirmed.
  • 高速マルチサンプリング超解像 CMOS テラヘルツイメージングデバイスの研究開発
    総務省：SCOPE フェーズII
    Date (from‐to) : 2016 -2018 
    Author : 池辺将之 佐野栄一
  • 高速マルチサンプリング超解像 CMOS テラヘルツイメージングデバイスの研究開発
    総務省：SCOPE フェーズI
    Date (from‐to) : 2015 -2016 
    Author : 池辺将之 佐野栄一
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    Date (from‐to) : 2012/04 -2015/03 
    Author : IGARASHI Hajime, WATANABE Kota, IKEBE Masayuki, MOTOHISA Junichi
     
    Batteryless wireless sensors are very effective for safety surveillance of infrastructures such as bridges, tunnels and steel towers of the power-transmission lines. In this study, vibration generators which power the wireless sensors have been developed. These vibration generators, which harvest energy from minute vibration of the structures, allow us to realize autonomous operation of the wireless sensors. Although the structures usually have wide vibration spectra, the conventional vibration generators, which have linear vibration modes, cannot harvest sufficient energy at nonresonant frequencies. In this study, it has been found that it is possible to generate chaotic vibration by introducing new design to the vibration generator and this leads to energy harvesting in wider vibration spectra.
  • 特に記載なし
    Semiconductor Technology Academic Research Center：特に記載なし
    Date (from‐to) : 2013/08 -2014/07 
    Author : IKEBE Masayuki
  • Japan Society for the Promotion of Science：Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (C)
    Date (from‐to) : 2010 -2012 
    Author : IKEBE Masayuki
     
    We developed an efficient CA algorithm for single-image super resolution based on low-memory box filtering. In FPGA implementation, we realize real-time QVGA to VGA movie processing and higher-quality jaggy suppression than bi-cubic interpolation. Moreover we implemented a fast 2-D local histogram equalization method, which with compensates halo effects, without kernel-size dependency. Using a2.9-GHz CPU with our method, the algorithm achieves 2 million pixels per 0.4 sec operation without the need for down sampling, Single Instruction/Multiple Data (SIMD) or multi-thread operation.
  • Ministry of Education, Culture, Sports, Science and Technology：Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 2008 -2010 
    Author : Eiichi SANO, Masayuki IKEBE
     
    On-chip antennas are demanded to further lower the cost of wireless CMOS ICs. The low resistivity of silicon substrates is a major obstacle to fabricate high-gain on-chip antennas. We placed an artificial dielectric layer (ADL) between an antenna and Si substrate to improve the antenna gain. A half-wave dipole-antenna that has ADL was designed and fabricated using a CMOS-compatible process with one poly-Si and two metal layers. Using the ADL enhanced gain by 3-dB. The measured gain was the highest ever achieved for the antennas operating at around 10 GHz on low-resistivity Si substrates. A method for further improvement is discussed. In addition to the improved antenna, we investigated wireless communication circuits monolithically integrated with antenna and nano-carbon materials for electromagnetic shielding applications.
  • Ministry of Education, Culture, Sports, Science and Technology：Grants-in-Aid for Scientific Research(若手研究(B))
    Date (from‐to) : 2008 -2009 
    Author : Masayuki IKEBE
     
    We developed an efficient CA algorithm for generating quasi linear curves based on finding shortest path between two points with topology reservation and CA algorithm in which a slime mold changes its body to obtain food effectively. Moreover we implemented a fast 2-D diffusion filtering method without kernel-size dependency. Using a dual core 2-GHz CPU with our method, the algorithm achieves 4 million pixels per sec operation without the need for downsampling, Single Instruction/Multiple Data (SIMD) or multi-thread operation.
  • Ministry of Education, Culture, Sports, Science and Technology：Grants-in-Aid for Scientific Research(基盤研究(A))
    Date (from‐to) : 2007 -2009 
    Author : Junichi MOTOHISA, Masayuki IKEBE, 橋詰 保
     
    We developed a formation method of high-density and highly uniform array of semiconductor nanowires to realize quantum integrated hardwares. In particular, fabrication and characterization of nanowire field-effect transistors (FETs) were charried out, and vertical nanowire FETs on Si substrates were demonstrated. We also proposed vertically-integrated logic circuits based on vertical FETs and investigated a method to laterally align nanowires for their high-density integration.
  • 文部科学省：科学研究費補助金(萌芽研究)
    Date (from‐to) : 2007 -2008 
    Author : 佐野 栄一, 池辺 将之
     
    本研究は、自然現象や社会現象で普遍的に見られるカオス同期に学ぶことにより、カオス同期による端末クラスタの形成、クラスタのグラフ論的性質を理解し、クラスタを活用した経路探索プロトコルを考案することにより、これまでのワイヤレス通信システムに革新をもたらす新たな通信方式を創出することを目的とする。昨年度の研究成果を発展させる研究を行った1。(1)カオス発生器を有するノードを円内あるいは直線に沿ってランダムに配置し、カオス発生器としてChua回路、ローレンツ写像、レスラー写像を用いて数値シミュレーションを行った。その結果、近接したノード問のみで同期クラスタを形成するのではなく、飛び地ができるという現象が見つかった。この現象はノード間の位相に深く関係しているものと推定している。(2)同期クラスタ内の端末間で経路探索のための情報をやり取りすることにより、放送型プロトコルと比較して周波数資源効率の向上と経路探索処理の高速化が可能であるとの考え方に基づき、カオス信号を搬送キャリアとしたクラスタ内でのデータ通信が可能か検討した。その結果、Chua回路によるカオス信号をキャリアとした場合にデータ通信成功の確率が高いことを明らかにした。ただし、この場合には確率100%とは限らず、改善策を探る必要がある。(3)新たに考案した発振周期同期型PLLについて、CMOSを用いて試作・評価を行った結果、正常動作を確認し、所期の目的を達成した。また、クロック生成に必要な3分周回路を考案した。(4)Kuramoto発振器としてリング発振器間の注入同期現象をCMOS試作により検討し、二つの発振器間同期を確認した.
  • 文部科学省：科学研究費補助金(若手研究(B))
    Date (from‐to) : 2006 -2007 
    Author : 池辺 将之
     
    1.セルオートマトンによる仮想粘菌アルゴリズムの研究(アルゴリズム設計)相互作用ルール設計手法を更に発展させ、回転テンプレートを用いた物体のトポロジー制御手法を考案した。粘菌のような生体動作をセルオートマトンで実現するためには、その特性のモデル化が必須となる。本研究では、粘菌が食物(ターゲット)を効率よく取得する体に変体していくモデルの研究を行った。研究にあたってC++言語によるセルオートマトンシミュレータを使用し、アルゴリズムの評価を行った。複雑な迷路を高速に解くセルオートマトン・アルゴリズムの実現に成功した。従来の迷路解析手法に比べ、14値から5値への大幅な状態遷移数の削減に成功し、かつ、ゴールまでに複数の経路があるような複雑な迷路形状においても、最短経路をセル幅1の線として抽出することが可能となった。2.CMOSイメージセンサ上でのフレーム内動き抽出処理の実現CMOSイメージセンサをアナログメモリとみなして、センサ上で演算する手法を実現し、センサチップを開発した。上記LSIでは、PS(プログラマブル・シーケンサ)を用いて演算部の制御を容易にする。相互作用ルールを実現する演算器のスイッチングを、PS用の命令として定義することで外部から容易な制御が可能であり、かつ、製作したLSIの評価・デバッグをシンプルにすることができた。センサの蓄積時間と演算機能により1フレームを取得するだけで動き抽出が可能となった。
  • Ministry of Education, Culture, Sports, Science and Technology：Grants-in-Aid for Scientific Research(基盤研究(B))
    Date (from‐to) : 2006 -2007 
    Author : Hideki HASEGAWA, Masamichi AKAZAWA, Masayuki IKEBE
     
    This project investigates key technologies for realization of GaN-based high-sensitivity chemical sensors and their on-chip integration using nanowires. The main conclusions are as follows: (1) Interface models on Schottky barrier formation are surveyed, and key issues related to AlGaN/GaN Schottky barriers including Fermi level pinning, Schottky barrier height (SBH) and reverse leakage currents are discussed. The current transport is explained by the thin surface barrier (TSB) model. Leakage currents can be reduced by the oxygen gettering process. (2) Pd Schottky barrier hydrogen sensors fabricated on AlGaN/GaN HEMT wafers exhibit unprecedented high sensitivities by applying the oxygen gettering process. (3) Its sensing mechanism is SBH reduction by interface dipole formed by atomic hydrogen which is produced at the Pd surface and diffuses to the Schottky interface. The rate limiting process for transient responses is surface reaction. Mathematical formulas for description of steady-state and transient response are given. (4) Sensitivity of AlGaN/GaN hydrogen sensors increases at higher temperatures, and they perform better than those by other major III-V semiconductors. (5) Slow transients are observed in hydrogen sensor diodes, and they can be explained by the dispersive transport due to time-continual hopping of electrons through surface states. This has led to a new model of current collapse in AlGaN/GaN HEMTs. (6)pH sensing HEMTs fabricated using an electrolyte/AlGaN gate structure, show nearly ideal Nernstian responses. Issues related to realization of bio-sensors using this structure are discussed. (7) For on-chip integration of sensors, implementation of a BDD (binary decision diagram) information processing architecture on hexagonal nanowire networks has been proposed. The proposal includes key elements such as basic integration unit, a sensor bridge, a sensor array structure, a selective MBE method for nanowire network formation and a wireless communication circuit integrated with an on-chip antenna. Their feasibilities have been proved.
  • 日本学術振興会：科学研究費助成事業 特別研究員奨励費
    Date (from‐to) : 1998 -1999 
    Author : 池辺 将之

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