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Kasai Seiya

Research Center for Integrated Quantum ElectronicsProfessor
Center for Human Nature Artificial Intelligence and NeuroscienceProfessor
Institute for Frontier Education and Research on SemiconductorsProfessor

Researcher basic information

■ Degree
  • Doctor (engineering), Hokkaido University
■ URL
researchmap URLホームページURL■ Various IDs
J-Global ID■ Research Keywords and Fields
Research Keyword
  • natural computing
  • 半導体表面界面物性
  • fluctuation, noise
  • stochastic resonance
  • Nonlinear device
  • III-V族化合物半導体
  • Semiconductor electron device
  • ultra-high speed device
  • III-V compound semiconductors
  • Semiconductor nanodevice
Research Field
  • Informatics, Soft computing, Amoeba-inspired computing, Electronic reservoir computing
  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering), Electron device and electronic equipment, Semiconductor electron devices, fluctuation, noise
  • Nanotechnology/Materials, Thin film/surface and interfacial physical properties
■ Educational Organization

Career

■ Career
Career
  • Apr. 2025 - Present
    Institute for Frontier Education and Research on Semiconductors, Hokkaido University, Deputy Director
  • Jan. 2024 - Present
    Advisor to the President, Hokkaido University
  • Jul. 2014 - Present
    Hokkaido University, Research Center for Integrated Quantum Electronics, Professor
  • 2004 - Jun. 2014
    Hokkaido University, Graduate School of Information Science and Technology
  • Oct. 2007 - Mar. 2011
    JST, PRESTO, Researcher
  • Apr. 2009 - Mar. 2010
    UTM, Visiting Professor
  • 2001 - 2004
    Hokkaido University, Graduate School of Engineering
  • 2004
    - Associate Professor, Graduate School of Information Science and Technology, and Research Center for Integrated Quantum Electronics
  • 2002 - 2003
    Associate Professor, Graduate School of Engineering, and University and Research Center for Integrated Quantum Electronics, Hokkaido University
  • 1999 - 2001
    Hokkaido University, Graduate School of Engineering
  • 1999 - 2001
    Research Assistant, Graduate School of Engineering, Hokkaido University,
  • 1997 - 1999
    NEC Corporation
  • 1997 - 1999
    NEC
Educational Background
  • Apr. 1994 - Mar. 1997, Hokkaido University, Graduate School of Engineering, DC, Electric Engineering, Japan
  • 1997, Hokkaido University, Graduate School, Division of Engineering
  • Apr. 1992 - Mar. 1994, Hokkaido University, Graduate School of Engineering, MC, Electric Engineering, Japan
  • Apr. 1988 - Mar. 1992, Hokkaido University, Department of Engineering, Faculty of Electric Engineering, Japan
  • 1991, Hokkaido University, Faculty of Engineering
Committee Memberships
  • Apr. 2025 - Present
    IEEE EDAPS2025, Local Committee Chair, Society
  • Jan. 2016 - Present
    International Microprocesses and Nanotechnology Conference (MNC), Organizing Committee Member, Society
  • Jan. 2023 - Dec. 2023
    36th International Microprocesses and Nanotechnology Conference (MNC), Organizing chair, Society
  • Jun. 2021 - May 2023
    Technical Committee of Electron Device, IEICE, Co-chair, Society
  • May 2021 - Apr. 2023
    IEICE Electron Device Committee, Co-chair, Society
  • Jan. 2022 - Dec. 2022
    35th International Microporcesses and Nanotechnology Conferencye, Organizing co-chair, Society
  • Apr. 2021
    日本学術振興会 R031ハイブリッド量子ナノ技術委員会, 物理・デバイス分野 副査, Government
  • Jan. 2018 - Dec. 2018
    International Microprocesses and Nanotechnology Conference (MNC), Organizing Committee Chair, Society
  • Feb. 2016 - Jan. 2018
    JSAP, member of a delegation, Society
  • Jan. 2016 - Dec. 2017
    International Microprocesses and Nanotechnology Conference (MNC), Organizing Committee Co-chair, Society
  • May 2013 - Apr. 2015
    電子情報通信学会, 電子デバイス研究会幹事, Society
  • 2015 - 2015
    International Conference on Solid State Devices and Materials, Secretary, Steering Committee, Society
  • 2014 - 2014
    International Conference on Solid State Devices and Materials, Steering Committee Member, Society
  • May 2011 - Apr. 2013
    電子情報通信学会, 電子デバイス研究会幹事補佐, Society
  • May 2009 - Apr. 2012
    電子情報通信学会, 和文誌C編集委員, Society
  • Jun. 2009 - May 2011
    応用物理学会, 講演会企画運営委員、大分科9応用物性世話人、9.3ナノエレクトロニクス世話人, Society
  • May 2001 - Apr. 2011
    電子情報通信学会, 電子デバイス研究会専門委員, Society
  • Jun. 2007 - May 2009
    応用物理学会, 9.3ナノエレクトロニクス世話人, Society
  • 2009 - 2009
    文部科学省, 特定領域研究専門委員会委員, Government
  • 2007 - 2007
    文部科学省, 特定領域研究専門委員会委員, Government
  • 国際学会（ISCS, AWAD, TWHM, etc）, 実行委員、プログラム委員など, Society
Position History
  • 総長補佐, 2024年1月1日 - 2024年3月31日
  • 総長補佐, 2024年4月1日 - 2026年3月31日

Research activity information

■ Awards
  • 2020, 応用物理学会, 応用物理学会優秀論文賞
    Divergence of relative difference in Gaussian distribution function and stochastic resonance in a bistable system with frictionless state transition
    葛西誠也;一木輝久;田所幸浩
  • 2017, 電気通信普及財団, テレコムシステム技術賞
    Design framework of image sensor system based on dynamic range extension by adding noise for saturated conditions
    田所 幸浩;葛西 誠也;一木 輝久;田中 宏哉
  • Mar. 2016, 電子情報通信学会, 電子情報通信学会エレクトロニクスソサイエティ活動功労表彰
    葛西 誠也
  • Mar. 2015, 情報処理学会高度交通システムとスマートコミュニティ研究会, 平成26年情報処理学会高度交通システム研究会優秀論文賞
    確率共鳴現象の応用によるハレーション環境での歩行者認識性能の改善
    田所幸浩;葛西誠也;一木輝久;田中宏哉
  • Nov. 2014, MNC2014, MNC2013 Award for Outstanding Paper
    "Detection of weak biological signal utilizing stochastic resonance in a GaAs-based nanowire FET and its parallel summing network
    Y. Imai;M. Sato;T. Tanaka;S. Kasai;Y. Hagiwara;H. Ishizaki;S. Kuwabara;T. Arakawa
  • Oct. 2011, MNC2011, MNC2010 Outstanding Paper Award
    Novel Nanowire-Based Flip-Flop Circuit Utilizing Gate-Controlled GaAs Three-Branch Nanowire Junctions
    H. Shibata;Y. Shiratori;S. Kasai
  • 2008, MNC2007 Outstanding Paper Award
    Japan
  • 2008, MNC2008 Outstanding paper award
  • 2007, NGC2007 Poster Prize
  • 2000, 第9回応用物理学会「講演奨励賞」
    Japan
  • 1996, SSDM Young Researcher Award
    Japan
■ Papers
■ Other Activities and Achievements
  • 揺らぎ
    葛西 誠也, 電子情報通信学会誌 = The journal of the Institute of Electronics, Information and Communication Engineers, 107, 6, 563, 565, Jun. 2024
    東京 : 電子情報通信学会, Japanese
  • 粘菌に触発された組合せ最適化計算機「電子アメーバ」とその記憶機能—Amoeba-inspired Combinatorial Optimization Machine "Electronic Amoeba" and Its Memory Functions—小特集 AIチップに向けた不揮発性メモリ技術とその展望
    葛西 誠也; 青野 真士, 電子情報通信学会誌 = The journal of the Institute of Electronics, Information and Communication Engineers, 107, 4, 340, 346, Apr. 2024
    東京 : 電子情報通信学会, Japanese
  • Purpose of symposium “AI Accelerator: Next stage of artificial intelligence devices”
    Baba Toshio; Kasai Seiya, JSAP Annual Meetings Extended Abstracts, 2021.2, 252, 252, 26 Aug. 2021
    The Japan Society of Applied Physics, Japanese
  • FPGA Implementation of the Satisfiability Problem Solver: AmoebaSATslim on a M-KUBOS Board
    YAN Yingjie; 青野真士; 天野英晴; 大古田香織; 福田真悟; 斉藤健太; 葛西誠也, 電子情報通信学会技術研究報告(Web), 121, 59(RECONF2021 1-16), 2021
  • 難問「巡回セールスマン問題」を新型コンピュータで解決~アメーバの探索能力から着想を得てアナログ回路で実現。超スマート社会での活躍に期待~
    葛西誠也; 青野真士, 北海道大学・アメーバエナジー社共同プレスリリース, Dec. 2020
    Introduction commerce magazine
  • Blind Sensing of Ground Condition Based on Somatic Sensation in Amoeba-inspired Autonomous Walking Robot
    大沼柊; 斉藤健太; 末藤直樹; 葛西誠也; 青野真士, 電子情報通信学会大会講演論文集(CD-ROM), 2020, 2020
  • Efficient Walking of an Amoeba-inspired Autonomous Walking Robot Using Stochastic Gradient Ascent
    大沼柊; 斉藤健太; 葛西誠也; 青野真士; 青野真士, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 81st, 2020
  • Influence of Delay in an Analog Electronic Amoeba on Solution-Searching Performance
    斉藤健太; 葛西誠也; 青野真士; 青野真士, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 81st, 2020
  • Solution Search Performance on an Amoeba Electronic Computing System for the Traveling Salesman Problem
    斉藤健太; 葛西誠也; 青野真士, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 67th, 2020
  • Mathematical Property of Gaussian Noise and Counterintuitive Stochastic Resonance
    Kasai Seiya, JSAP Annual Meetings Extended Abstracts, 2019.2, 250, 250, 04 Sep. 2019
    The Japan Society of Applied Physics, Japanese
  • Correlation between interface structure and contact resistance in Nickel-Graphene junction
    In Shou; Kasai Seiya, JSAP Annual Meetings Extended Abstracts, 2019.1, 3532, 3532, 25 Feb. 2019
    The Japan Society of Applied Physics, Japanese
  • 粘菌型自律歩行ロボット行動決定のための動態時系列センシング
    大沼柊; 斉藤健太; 末藤直樹; 葛西誠也; 青野真士, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 80th, 2019
  • アメーバ電子計算システムにおける最大カット問題のマッピングとその求解
    斉藤健太; 末藤直樹; 葛西誠也; 青野真士, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 80th, 2019
  • 粘菌に着想を得たTSP解探索アルゴリズムの電子回路実装
    斉藤健太; 末藤直樹; 葛西誠也; 青野真士, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 66th, 2019
  • 最適化問題を解く電子アメーバとその応用
    葛西誠也; 青野真士; 斉藤健太; 末藤直樹, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 66th, 2019
  • 非同期CMOS論理回路に問題をマッピングしたアメーバ型解探索電子システムの動的挙動
    末藤直樹; 斉藤健太; 青野真士; 葛西誠也, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 66th, 2019
  • 自然界のありふれた雑音は小さな信号を際立たせる -直感に反する確率共鳴現象の解明に新たな道筋：電子機器の小型・低消費電力化への貢献に期待
    葛西 誠也; 一木 輝久; 田所 幸浩, 北海道大学プレスリリース, Feb. 2018
    Japanese, Introduction commerce magazine
  • 電子アメーバSAT解探索システムにおけるエラーと解探索効率の相関
    斉藤健太; 葛西誠也; 青野真士, 電子情報通信学会大会講演論文集(CD-ROM), 2018, 2018
  • 粘菌アメーバ型最適化問題解探索にもとづく4脚ロボットの自律歩行
    末藤直樹; 斉藤健太; 葛西誠也; 青野真士, 電子情報通信学会大会講演論文集(CD-ROM), 2018, 2018
  • ジェスチャー型マン・マシンインターフェースに向けた確率共鳴現象を応用したロバスト表面筋電信号検出技術
    葛西 誠也, 電子情報通信学会和文誌C, J100-C, 369, 376, 2017, [Peer-reviewed]
  • 電子アメーバ最適化問題解探索における外乱の効果
    斉藤健太; 葛西誠也; 青野真士, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 64th, 2017
  • Application of Stochastic Resonance to Improve the Performance of Pedestrian-recognition Systems in Halation Environments
    Yukihiro Tadokoro; Seiya Kasai; Akihisa Ichiki; Hiroya Tanaka, R&D Review of Toyota CRDL, 47, 2, 61, 69, 14 Apr. 2016, [Peer-reviewed]
    English, Technical report
  • Nonlinear voltage transfer characteristics of a graphene three-branch nano-junction device and its control (電子デバイス)
    殷 翔; 劉 柏麟; 田中 啓文; 前元 利彦; 葛西 誠也, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 115, 469, 27, 32, 03 Mar. 2016
    電子情報通信学会, English
  • 単分子吸着によって発現するカーボンナノチューブ素子におけるランダムテレグラフシグナルノイズ
    藤井逸人; SETIADI Agung; 赤井恵; 葛西誠也; 金井康; 松本和彦; 桑原裕司, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 63rd, ROMBUNNO.21P-S421-11, 03 Mar. 2016
    Japanese
  • 電子アメーバSAT解探索におけるエラーと解探索効率の関係
    斉藤健太; 葛西誠也; 青野真士, 電子情報通信学会大会講演論文集(CD-ROM), 2016, 2016
  • C-10-6 Basic Study on Semiconductor Device for Detecting Spatial Distribution of Small Charges
    Sasaki Kentaro; Kuroda Ryouta; Yin Xiang; Sato Masaki; Kasai Seiya, Proceedings of the Society Conference of IEICE, 2015, 2, 39, 39, 25 Aug. 2015
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Amoeba-inspired Spatiotemporal Dynamics for Solving the Satisfiability Problem (Special Issue on New Challenges in Complex Systems Science)
    Aono Masashi; Kim Song-Ju; Kasai Seiya, 理工研報告特集号 : ASTE : advances in science, technology and environmentology : special issue, 11, 37, 40, Mar. 2015
    早稲田大学理工学術院総合研究所 (理工学研究所), English
  • C-10-10 Electronic circuit implementation of amoeba-inspired algorithm for satifiability problem and its operatin speed
    WAKAMIYA Ryo; KASAI Seiya; AONO Masashi; NARUSE Makoto; MIWA Hiroyoshi, Proceedings of the IEICE General Conference, 2015, 2, 57, 57, 24 Feb. 2015
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Electronic circuit implementation of amoeba-inspired solution search algorithm for optimization problems
    WAKAMIYA Ryo; KASAI Seiya; AONO Masashi; NARUSE Makoto; MIWA Hiroyoshi, Technical report of IEICE. SDM, 114, 443, 81, 85, 05 Feb. 2015
    It is known that amoeba has computational ability on the basis of its self-organized movements in spite of simple structure. Using its photoavoidance behavior and fluctuations of the movements, solution search algorithms for optimization problems such as constraint satisfaction problem (CSP) and satisfiability problem (SAT) have been developed. We recently successfully implemented the amoeba-inspired algorithms for solution search of CSP and SAT using simple electronic circuits. In this report, we present the circuit architecture, design, and experimental results of the circuit operations., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Electronic circuit implementation of amoeba-inspired solution search algorithm for optimization problems
    WAKAMIYA Ryo; KASAI Seiya; AONO Masashi; NARUSE Makoto; MIWA Hiroyoshi, IEICE technical report. Electron devices, 114, 442, 81, 85, 05 Feb. 2015
    It is known that amoeba has computational ability on the basis of its self-organized movements in spite of simple structure. Using its photoavoidance behavior and fluctuations of the movements, solution search algorithms for optimization problems such as constraint satisfaction problem (CSP) and satisfiability problem (SAT) have been developed. We recently successfully implemented the amoeba-inspired algorithms for solution search of CSP and SAT using simple electronic circuits. In this report, we present the circuit architecture, design, and experimental results of the circuit operations., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Current Noise Characteristics in GaAs-based Nanowire FETs and Carbon Nanotube Devices
    井上慎也; 葛西誠也; SETIADI Agung; 赤井恵, 電子情報通信学会技術研究報告, 114, 442(ED2014 138-152), 57, 61, 29 Jan. 2015
    Japanese
  • Characterization and analysis of hysteresis properties in insulated-gate GaAs-based nanowire FETs
    KURODA Ryota; YIN Xiang; SATO Masaki; KASAI Seiya, IEICE technical report. Electron devices, 114, 56, 91, 96, 28 May 2014
    We fabricate SiN and Al_2O_3-gate GaAs etched nanowire FETs, characterized dynamic hysteresis properties in their transfer characteristics, and analyzed. Both devices show clear hysteresis characteristics, however the Al_2O_3-gate device exhibits large dispersion of the average current when white Gaussian noise is superimposed to gate bias. In this dispersion, the drain current decreases as the noise intensity increases, without changing threshold voltages, which is not seen in the SiN-gate device. We explain the observed behavior by current expected value under transition between the discrete current states., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Hysteresis characteristics of GaAs-based etched nanowire MISFETs
    Kuroda ryota; Kasai Seiya, JSAP Annual Meetings Extended Abstracts, 2014.1, 1802, 1802, 03 Mar. 2014
    The Japan Society of Applied Physics, Japanese
  • Characterization of An Electron Brownian Ratchet Device Based on A GaAs-based Nanowire Having Asymmetric Gates
    ABE Yushi; TANAKA Takayuki; KASAI Seiya, IEICE technical report. Electron devices, 113, 449, 47, 50, 27 Feb. 2014
    We investigate the operation condition of an electron Brownian ratchet device utilizing a GaAs-based nanowire having asymmetric gates in terms of increasing the generated current. The Brownian ratchet is known as a driving mechanism of a molecular motor in biological systems, where dorected force is generated from thermally fluctuated molecules. Recently we fabricated a GaAs-based Brownian ratchet device and successfully observed the generation of coherent current by flashing ratchet operation. In this report, we characterize the input flashing signal dependence of the generated coherent current in this Brownian ratchet device and discuss the factors controlling the operation condition., The Institute of Electronics, Information and Communication Engineers, Japanese
  • 粘菌型解探索システムにおける自発的解探索の検討
    若宮遼; 葛西誠也; 青野真士; 成瀬誠; 巳波弘佳, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 75th, 2014
  • 最適化問題解探索電子アメーバ
    葛西誠也; 青野真士; 成瀬誠; 巳波佳弘; 若宮遼, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 61st, 2014
  • GaAsナノワイヤ電子ブラウンラチェットデバイスのフラッシング動作特性
    阿部 遊子; 田中 貴之; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2013.2, 2671, 2671, 31 Aug. 2013
    公益社団法人 応用物理学会, Japanese
  • ナノワイヤFETネットワーク確率共鳴を利用した生体信号検出に関する基礎的検討
    今井 裕理; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2013.2, 2672, 2672, 31 Aug. 2013
    公益社団法人 応用物理学会, Japanese
  • グラフェン３分岐ナノ接合デバイスのトップゲート制御
    殷 翔; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2013.2, 2669, 2669, 31 Aug. 2013
    公益社団法人 応用物理学会, Japanese
  • 電子的確率共鳴の非侵襲生体信号計測への応用に関する検討—Study on Application of Electronic Stochastic Resonance to Non-invasive Biological Signal Detection—シリコン材料・デバイス
    今井 裕理; 葛西 誠也, 電子情報通信学会技術研究報告 = IEICE technical report : 信学技報, 113, 41, 71, 75, May 2013
    東京 : 電子情報通信学会, Japanese
  • SiN/AlGaAs/GaAsナノワイヤFETのしきい値制御
    黒田 亮太; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2013.1, 1768, 1768, 11 Mar. 2013
    公益社団法人 応用物理学会, Japanese
  • GaAs ナノワイヤ3 分岐接合デバイスの表面状態と非線形特性の関連性についての検討
    佐藤 将来; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2013.1, 1767, 1767, 11 Mar. 2013
    公益社団法人 応用物理学会, Japanese
  • A-2-10 Experimental Demonstration of Low SNR Signal Detection by An Optimized Nonlinear Device
    Kasai Seiya; Tadokoro Yukihiro; Ichiki Akihisa, Proceedings of the IEICE General Conference, 2013, 37, 37, 05 Mar. 2013
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Fabrication of Graphene-based Three-branch Nano-junction (TBJ) and Its Application to Logic Gates
    Yin Xiang; Kasai Seiya, IEICE technical report. Electron devices, 112, 445, 35, 38, 27 Feb. 2013
    A graphene-based three-branch nano-junction (TBJ) devices is investigated for its application to Boolean logic gates. Owing to its unique nonlinear transfer characteristics of the TBJ as well as ambipolar transport in the graphene, the graphene-based TBJ operates as both AND and OR logic gates by itself and they can be switched by backgate bias. In this report, in order to realize universality of the TBJ-based logic gate architecture, the graphene-based TBJ logic inverter is proposed and demonstrated Fabricated graphene TBJ exhibits parabolic voltage transfer curve and the polarity of the curvature can be switched by backgate voltage. Giving voltage input to the backgate, inversion of voltage signal is observed in the TBJ output branch Voltage transfer gain of this device is 0.013., The Institute of Electronics, Information and Communication Engineers, Japanese
  • 確率共鳴を利用した生体信号検出ナノデバイスの検討
    今井 裕理; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2012.2, 1820, 1820, 27 Aug. 2012
    公益社団法人 応用物理学会, Japanese
  • 光照射局所コンダクタンス変調法を用いたGaAsナノワイヤ3分岐接合デバイスの非線形特性評価
    佐藤 将来; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2012.2, 1821, 1821, 27 Aug. 2012
    公益社団法人 応用物理学会, Japanese
  • Study on Synchronized Charge Transfer and Its Efficiency, in GaAs-based Etched Nanowire CCD
    NAKANO Yuki; TANAKA Takayuki; KASAI Seiya, IEICE technical report. Electron devices, 112, 154, 55, 59, 19 Jul. 2012
    For realization of the information processing system integrating nanowire-based circuits on a nanowire network, synchronized signal transfer in the network is necessary. In this report, we investigate a charge-coupled device (CCD) fabricated on a GaAs-based etched nanowire. The clocked signal transfer and the dynamic charge transfer efficiency for time-dependent bit signals were characterized. MHz-clocked charge transfer was realized in the fabricated device. The charge transfer efficiency was found to strongly depend on the nanowire surface, which significantly affected on a-few-electron transfer for low-power operation. Improvement of the transfer efficiency was investigated by SiN-based nanowire surface passivation., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Performance Evaluation of Stochastic-Resonance-based Delay Network under colored-noise environment
    TADOKORO Yukihiro; KASAI Seiya; ICHIKI Akihisa, IEICE technical report. Nonlinear problems, 112, 117, 97, 102, 28 Jun. 2012
    Stochastic-Resonance-based delay network has been proposed in order to obtain a weak signal which is buried in a strong noise. This network delays the input signal where the amount of delay is set to be larger than a correlation-time of the noise. Such operation produces many copies of the input signal whose noise components are uncorrelated each other. The copies are summed up, and then the noise is averaged out. The correlation-time of white noise equals to zero so that the delay can be set to be zero. However, colored noise is often seen in practical situations. In this report, performances of the network under colored-noise environment are evaluated. Discussions based on linear filtering theory makes clear that the delay-network has a noise-shaping like effect, and transversal filter, which is followed by the nonlinear device, eliminates the noise component located in a high-frequency region., The Institute of Electronics, Information and Communication Engineers, Japanese
  • C-10-11 Characterization of nonlinear voltage transfer in GaAs-based three-branch nanowire junctions by a light-induced local conductance modulation method
    Sato Masaki; Muramatsu Toru; Kasai Seiya, Proceedings of the IEICE General Conference, 2012, 2, 64, 64, 06 Mar. 2012
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • A-2-33 A performance improvement of stochastic resonance by delay network
    Tadokoro Yukihiro; Kasai Seiya; Ichiki Akihisa, Proceedings of the IEICE General Conference, 2012, 78, 78, 06 Mar. 2012
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • GaAsナノワイヤCCDの電荷転送効率の評価
    中野 雄紀; 田中 貴之; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2012.1, 1967, 1967, 29 Feb. 2012
    公益社団法人 応用物理学会, Japanese
  • Study on nonlinear transfer characteristics in a GaAs three-branch nanowire junction device using a light-induced local conductance modulation method
    SATO Masaki; MURAMATSU Toru; KASAI Seiya, IEICE technical report. Electron devices, 111, 425, 95, 99, 07 Feb. 2012
    Semiconductor three-branch nanowire junction devices show nonlinear electrical characteristics at room temperature and they are expected to be applied to analog and digital circuit,but it is necessary that understanding the mechanism in order to be applied to circuits. In this study nonlinear characteristics in three-branch nanowire junction device is characterized by using method of increasing conductance by localized light irradiation to the device and the mechanism is discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • GaAsナノワイヤFET経路長変調ネットワークにおける確率共鳴
    葛西誠也, 第回応用物理学関係速合講演会講演予稿集,2012, 6, 2012
  • Characterization and Analysis of Low-Frequency Noise in SiN Insulator-Gate GaAs Etched Nanowire FETs
    Toru Muramatsu; Seiya Kasai; Zenji Yatabe, EICE technical report. Electron devices, 111, 425, 89, 93, Jan. 2012, [Domestic magazines]
    Low-frequency noise in SiN-gate GaAs-based nanowire field-effect transistors (FETs) is characterized and analyzed focusing on its device size dependence. Noise in a nanometer-scale semiconductor is an important issue, since it increases as the feature size is decreased. We observe the increased low-frequency noise in the nanowire current, which is caused by charging and discharging electron traps in the SiN gate insulator. As the nanowire width is decreased, the noise intensity increased and the spectral shape changes from 1/f to 1/f^2. Noise spectrum is analyzed by computing the spectrum for specific trap distribution functions in terms of time constant. We find the relationship between the spectral shape and the distribution function. Change of the observed spectral slope is understood in terms of the broadening of the trap distribution., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Characterization of Low-Frequency Noise in SiN_x Insulator-Gate GaAs Etched Nanowire FETs
    MURAMATSU Toru; MIURA Kensuke; SHIRATORI Yuta; KASAI Seiya, IEICE technical report, 111, 167, 31, 34, 22 Jul. 2011
    Noise in a semiconductor field-effect transistor (FET) is going to increase, as the device size is reduced. The important issue is understanding and control of the noise characteristics. In this study, insulator-gate GaAs-based nanowire FETs are fabricated and their low frequency noise is characterized. We experimentally investigate the effect of electron traps in the SiN_x gate insulator and the size dependence of the intensity and the spectrum of the drain current noise. Observed noise typically shows 1/f^2 spectrum, indicating the random telegraph signal (RTS). The spectrum intensity depends on the nanowire width and it changes from 1/f to 1/f^2 as the width is decreased., The Institute of Electronics, Information and Communication Engineers, Japanese
  • 半導体ナノワイヤネットワークと情報処理機能
    葛西 誠也, 応用物理学会学術講演会講演予稿集, 2011.1, 477, 477, 09 Mar. 2011
    公益社団法人 応用物理学会, Japanese
  • 確率共鳴の電子的利用を可能にする半導体ナノデバイス技術
    葛西 誠也, 応用物理学会学術講演会講演予稿集, 2011.1, 374, 374, 09 Mar. 2011
    公益社団法人 応用物理学会, Japanese
  • C-10-11 Low Frequency Noise in GaAs Nanowire FETs Controlled by Schottky Wrap Gate
    Miura Kensuke; Shiratori Yuta; Muramatsu Toru; Kasai Seiya, Proceedings of the IEICE General Conference, 2011, 2, 58, 58, 28 Feb. 2011
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • C-10-12 Fabrication and Characterization of High Density Flip-flop Circuit Utilizing Gate-controlled GaAs Three-branch Nanowire Junctions
    Shibata Hiromu; Shiratori Yuta; Kasai Seiya, Proceedings of the IEICE General Conference, 2011, 2, 59, 59, 28 Feb. 2011
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • CT-2-3 Stochastic Resonance Transistor Coexisting with Noise
    Kasai Seiya, Proceedings of the IEICE General Conference, 2011, 2, "SS, 23"-"SS-26", 28 Feb. 2011
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Characterization of Single-Electron Stochastic Resonance in A Quantum Dot and Its Parallel Network
    KASAI Seiya; SHIRATORI Yuta; MIURA Kensuke; NAKANO Yuki, IEICE technical report, 110, 423, 79, 82, 16 Feb. 2011
    We investigate the effect of physical variation on single-electron stochastic resonance (SE-SR) in the quantum-dot parallel summing network. Analysis is carried out using a commercial single electron circuit simulator. The SR response in each dot is changed when the dot capacitance is changed, corresponding with the dot size variation. However, the total response of the network system integrating varied dots is found to converge to that of the system consisting uniform dots. This result is quite different from the behavior of the varied threshold-voltage FET network, where the response obeys the envelope of response curve from each device., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Fabrication of GaAs-based Nanowire CCD Controlled by Schottky Wrap Gates and Characterization of Its Charge Transfer Operation
    NAKANO Yuki; MIURA Kensuke; SHIRATORI Yuta; KASAI Seiya, IEICE technical report, 110, 423, 49, 52, 16 Feb. 2011
    For synchronization of nanowire-based integrated circuits, a GaAs nanowire charge-coupled device (CCD) controlled by Schottky wrap gates is fabricated and its charge transfer operation is characterized. The charge packet is transferred successively by clocked signals on two wrap gates. Measured DC current in the fabricated device depends linearly on the clock frequency. The current is found to independent on temperature. The obtained results confirm synchronized charge transfer in the present device., The Institute of Electronics, Information and Communication Engineers, Japanese
  • THz Sensing by GaAs-based Nanowire FET and Its Enhancement Utilizing Stochastic Resonance
    KASAI Seiya; MIURA Kensuke; SHIRATORI Yuta, IEICE technical report. Electron devices, 110, 203, 13, 17, 06 Sep. 2010
    THz signal sensing using GaAs nanowire FETs formed by lithography and chemical etching is described. THz photocurrent is experimentally observed when the device is operated at low temperature and conductance quantization appears. This result indicates that the strong nonlinear transfer characteristic plays an important role in conversion of the THz signal to the DC photocurrent. On the basis of this mechanism, sensing of very weak THz signal utilizing stochastic resonance in a FET parallel summing network is discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • C-10-9 Fabrication and Characterization of GaAs-based Nanowire Charge Coupled Devices
    Nakano Yuki; Miura Kensuke; Siratori Yuta; Kasai Seiya, Proceedings of the Society Conference of IEICE, 2010, 2, 53, 53, 31 Aug. 2010
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • GaAsナノワイヤFETにおける低周波雑音の構造サイズ依存性
    三浦 健輔; 白鳥 悠太; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2010.2, 1745, 1745, 30 Aug. 2010
    公益社団法人 応用物理学会, Japanese
  • SiNx絶縁ゲートGaAsナノワイヤFETの雑音特性
    村松 徹; 三浦 健輔; 葛西 誠也, 応用物理学会学術講演会講演予稿集, 2010.2, 1744, 1744, 30 Aug. 2010
    公益社団法人 応用物理学会, Japanese
  • 確率共鳴を利用した新しい情報処理のためのナノデバイスと集積化
    葛西 誠也, 応用物理学会学術講演会講演予稿集, 2010.2, 144, 144, 30 Aug. 2010
    公益社団法人 応用物理学会, Japanese
  • GaAsナノワイヤFETにおける確率共鳴と適応性
    葛西 誠也; 白鳥 悠太; 三浦 健輔, 応用物理学会学術講演会講演予稿集, 2010.1, 1900, 1900, 03 Mar. 2010
    公益社団法人 応用物理学会, Japanese
  • Compact Reconfigurable BDD Logic Circuits utilizing GaAs Nanowire Network
    SHIRATORI Yuta; MIURA Kensuke; KASAI Seiya, IEICE technical report, 109, 423, 71, 76, 15 Feb. 2010
    We describe a reconfigurable binary-decision-diagram logic circuit based on Shannon's expansion of Boolean logic function and its graphical representation utilizing a semiconductor nanowire network. The circuit is reconfigured by using programmable switches that electrically connect and disconnect branches. This circuit has a compact structure with a small number of devices and a small circuit area compared with the conventional Si CMOS look-up table architecture. A two-input reconfigurable BDD circuit was fabricated on an etched GaAs nanowire network having hexagonal topology with Schottky wrap gates and SiN-based programmable switches. Its correct logic operation together with dynamic reconfiguration was successfully demonstrated., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Analysis on Stochastic Resonance Behavior of Single Electrons in Quantum Dots
    KASAI Seiya; SHIRATORI Yuta; MIURA Kensuke, IEICE technical report, 109, 423, 17, 21, 15 Feb. 2010
    Stochastic resonance (SR) in single-electron charging and discharging process on quantum dots (QDs) is demonstrated theoretically and its behaviors are analyzed. The SR, in which response of a system is enhanced by fluctuation, has a possibility to solve thermal fluctuation problem in single electron systems. The single electron dynamics is described by a master equation with Poisson-type single electron tunneling rate and it is solved analytically. This analysis demonstrates the single electron SR in a quantum dot system. Deduced formula quantitatively reproduces the response obtained by a single electron device simulator, verifying the validity of the analysis. Correlation between the single electron SR response and device parameters of the QD system is clarified. Experiment observation of the single electron SR is also mentioned., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Fabrication of nanowire-based sequential circuits using gate-controlled GaAs three-branch nanowire junctions
    SHIBATA Hiromu; NAKATA Daisuke; SHIRATORI Yuta; KASAI Seiya, IEICE technical report, 109, 423, 65, 70, 15 Feb. 2010
    A novel sequential circuit integrating gate-controlled three-branch nanowire junctions (TBJs) is described. A TBJ shows a unique nonlinear voltage transfer characteristics even with a very simple structure connecting three nanowires. It can operate as a two-input AND gate by itself and NAND gate can be realized by integrating the TBJ and an inverter. The TBJ voltage transfer efficiency is improved by gate control of the input nano wires. This structure also has a DCFL inverter configuration. A set-reset flip flop (SR-FF) circuit is designed and fabricated by a GaAs-based etched nanowire network and its Schottky wrap gate control. A correct SR-FF operation of the fabricated circuit is successfully demonstrated., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Stochastic Resonance Devices Based on Carbon Nanotube Field-Effect Transistors
    HAKAMATA Yasufumi; OHNO Yasuhide; MAEHASHI Kenzo; KASAI Seiya; INOUE Koichi; MATSUMOTO Kazuhiko, IEICE technical report, 109, 423, 11, 15, 15 Feb. 2010
    Stochastic resonance in carbon nanotube field-effect transistors (CNT-FETs) was investigated to enhance weak-signal response. When weak pulse trains were given to the gate of the CNT-FET operating in sub-threshold region, the correlation between the input-pulse and source-drain current increased by adding noise with optimized intensity. Moreover, enhancement of the correlation was observed in a summing network of the CNT-FETs. It was also found that the peak width of correlation coefficient also became wider, indicating that the summing CNT-FET networks were robust against noise. Therefore, the summing CNT-FET networks based on stochastic resonance will be a promising candidate for highly sensitive label-free sensors., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Stochastic Resonance in GaAs-based Nanowire Field-Effect Transistors and Their Summing Network
    KASAI Seiya; ASAI Tetsuya; SHIRATORI Yuta; NAKATA Daisuke, IEICE technical report, 109, 98, 125, 128, 17 Jun. 2009
    Stochastic resonance phenomenon in GaAs-based nanowire field effect transistors (FETs) and their summing network is studied experimentally. Response to a weak signal of a nanowire FET operating in subthreshold region is enhanced by adding noise to gate. The response is further improved by forming a FET summing network and strong input-output correlation is obtained in wide noise voltage range. The effect of device variation in the network is also investigated and it is found to make the system respond the weak signal without tuning noise intensity., The Institute of Electronics, Information and Communication Engineers, English
  • Observation of Stochastic Resonance in Nanodevice-integrated Systems Utilizing GaAs-based Nanowire Network and Its Analysis
    KASAI Seiya; ASAI Tetsuya; SHIRATORI Yuta; ZHAO Hong-Quan, IEICE technical report, 108, 437, 75, 79, 19 Feb. 2009
    Stochastic resonance, in which response of a system is improved by adding noise, is successfully observed using field effect transistors on GaAs-based nanowire networks. The transistor is operated in a subthreshold region. A weak input signal with non-correlated noise is given to the gate and drain current is monitored as output. Then, input-output correlation coefficient as a function of noise intensity shows a peak. The correlation at the peak exceeds that of the conventional linear averaging system. Summing network of the transistors is found to further increase the correlation. The observed results are analyzed using a stochastic differential equation., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Characterization and Analysis on Operation of GaAs Three-Branch Nanowire Junction Device
    NAKATA Daisuke; ABD RAHMAN Shaharin Fadzli; SHIRATORI Yuta; KASAI Seiya, IEICE technical report, 108, 437, 63, 68, 19 Feb. 2009
    Three-branch nanowire junction devices show nonlinear electrical characteristics from the low temperature to the room temperature, and they are expected to be applied to logic and high frequency circuits. In such application, understanding the mechanism and control of characteristic are necessary. In this study GaAs-based three-branch nanowire junction devises having Schottky wrap gates are fabricated and characterized in detail, including the effect of Schottky wrap gate and nanowire length on nonlinear characteristics and operation speed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • C-10-21 Stochastic Resonance in GaAs-based Nanowire FETs and Enhanced Signal Detection by Noise
    Kasai Seiya; Asai Tetsuya, Proceedings of the Society Conference of IEICE, 2008, 2, 66, 66, 02 Sep. 2008
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • 2-bit Arithmetic Logic Unit Utilizing Hexagonal BDD Architecture for Implementation of Nanoprocessor on GaAs Nanowire Network
    ZHAO Hong-Quan; KASAI Seiya; HASHIZUME Tamotsu, IEICE technical report, 108, 122, 139, 144, 02 Jul. 2008
    2-bit arithmetic logic unit (ALU) utilizing the binary-decision diagram (BDD) logic architecture for nanoprocessor is fabricated on GaAs hexagonal nanowire networks with Schottky wrap gates (WPGs) and their operation is characterized. The ALU integrates 32 node devices and implements 4 instructions. They are fabricated by 3M or 16M nodes/cm^2 fabrication processes. Fabricated ALU shows correct operations experimentally obtained in classical transport domain at room temperature. Supply voltage and input voltage swing dependences of the circuit operation are characterized. Discrete node devices are also investigated from viewpoint of integration, including path switching, threshold voltage variation and gate leakage current., The Institute of Electronics, Information and Communication Engineers, English
  • Control of Nonlinear Characteristics in GaAs-based Three-terminal Nanowire Junction Devices and Its Application to Logic Gates
    ABD RAHMAN Shaharin Fadzli; SHIRATORI Yuta; KASAI Seiya, IEICE technical report, 107, 474, 33, 38, 23 Jan. 2008
    Three-terminal nanowire junctions show nonlinear electrical characteristics even at room temperature and they are expected to be useful building blocks for state-of-the-art nanowire-based logic circuits. In this study, GaAs-based three-terminal nanowire junction devices are fabricated and characterized, and the mechanism of the nonlinear characteristics is discussed. In order to control the electrical property, Schottky-wrap-gate (WPG)-control of nanowires in the junction is investigated. A NAND circuit integrating three-terminal junctions is also demonstrated for their application to logic circuits., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Implementation of Active and Sequential Circuits on GaAs-based Nanowire Network Structures Controlled by Schottky Wrap Gates
    KASAI Seiya; ZHAO Hong-Quan; HASHIZUME Tamotsu, IEICE technical report, 107, 474, 63, 68, 23 Jan. 2008
    Implementation of active and sequential circuits on semiconductor-based nanowire networks with a specific topology and periodicity is investigated. Concept of the circuits and design scheme are explained. Then fabrication on AlGaAs/GaAs-based etched nanowire network and their characterization are described. Issues and prospects of this circuit implementation technique are also discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • GaAs系ショットキーラップゲート量子細線トランジススタの微細化とスイッチング特性の相関(2)
    葛西 誠也, 電子情報通信学会技術研究報告 v.107(473), 63, 68, 2008
  • AlGaN/GaN HEMTs with Multi-Mesa-Channel Structures
    TAMURA Takahiro; HASHIZUME Tamotsu; KOTANI Junji; KASAI Seiya, 電気学会研究会資料. EFM, 電子材料研究会, 2007, 15, 11, 14, 30 Nov. 2007
    Japanese
  • Schottky-Wrap-Gate Controlled AlGaN/GaN Nanowire FETs
    TAMURA Takahiro; KOTANI Junji; KASAI Seiya; HASHIZUME Tamotsu, 電子情報通信学会技術研究報告. MW, マイクロ波, 106, 460, 179, 182, 10 Feb. 2007
    Japanese
  • Study on A Novel Logic-Circuit Implementation Scheme Utilizing Topological Affinity between Decision-Diagram Representation of Logic Functions and Nanowire Network Structures
    KASAI Seiya; NAKAMURA Tatsuya; SHIRATORI Yuta, IEICE technical report, 106, 520, 29, 34, 25 Jan. 2007
    This report presents study on a novel scheme to implement logic information processing function on nanowire network structures that can be produced with various materials. Decision diagram (DD) technique make it possible to visualize logic functions by directed graphs. By combination of the logic graph and nanowire-network structures thorough their topologies, the logic function can be implemented on the nanowire network directly. Its logic operation is realized by gate control of transport of information messengers in the nanowire. We demonstrate this approach by the hardware implementation of circuits, where GaAs-based etched nanowire networks are controlled by nanometer-scale Schottky wrap gates., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Fabrication and Characterization of Three-GaAs Nanowire-Junction Devices Controlled by Schottky Wrap Gates
    NAKAMURA Tatsuya; KASAI Seiya; SHIRATORI Yuta; HASHIZUME Tamotsu, IEICE technical report, 106, 520, 73, 77, 25 Jan. 2007
    A three-terminal nanowire junction device controlled by double nanometer-sized Schottky wrap gates (WPGs), which control left and right branches independently, is fabricated utilizing AlGaAs/GaAs etched nanowires and characterized experimentally. Fabricated device exhibits clear nonlinear characteristics of output voltage at the center terminal by applying voltages to left and right terminals in push-pull fashion. Applying asymmetric gate voltages to left and right WPGs provide clear asymmetry in the output voltage. The nonlinearity in the ballistic transport domain is greatly enhanced by squeezing both left and right branches using WPGs., The Institute of Electronics, Information and Communication Engineers, Japanese
  • 確率共鳴を利用した新しい情報処理のためのナノデバイスと集積化
    葛西誠也, http://www.mat-bcmos.jst.go.jp/kenkyu/01-01kasai.html, 2007
  • Study on Degradation of Gate-Length Dependence of Transconductance in AlGaN/GaN HFETs with Nanometer-Size Gates
    KASAI Seiya; BASILE Alberto F.; HASHIZUME Tamotsu, IEICE technical report, 106, 377, 33, 38, 17 Nov. 2006
    Degradation of gate length (L_G) dependence of transconductance (g_m) in AlGaN/GaN heterojunction field effect transistors (HFETs) with nanometer-size-Schottky gates was studied experimentally, focusing on the correlation between g_m and gate leakage current. Utilizing the surface control processes on AlGaN and formation of SiN passivation layer around the Schottky gates, gate leakage currents in fabricated HFETs decreased by two orders of magnitude as compared with devices without passivation. L_G dependence of g_m was recovered in the passivated devices and 30% increase of g_m was obtained by reducing L_G from 1,000nm to 300nm. The obtained results could be explained by the virtual gate model in which lateral gate leakage current charges AlGaN surfaces in the gate periphery., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Characterization of Conductance Switching in Schottky-Wrap-Gate-Controlled Quantum Wire Transistors in A-Few-Electron Regime
    KASAI Seiya; SHIRATORI Yuta; NAKAMURA Tatsuya; TAMURA Takahiro, IEICE technical report, 106, 137, 205, 209, 26 Jun. 2006
    Binary conductance switching at the first quantized conductance step in Schottky-wrap-gate (WPG)-controlled quantum wire transistors was characterized for the low power operation of the hexagonal binary-decision diagram (BDD) logic quantum circuits. The fabricated devices showed clear conductance quantization and their trace survived up to 80 K. They also exhibited non-linear dependence of logic swing and conductance step height on temperature, which were not explained by the standard one-dimensional transport theory. Analysis on the observed behaviors indicated the appearance of charge-spin separation under a low-electron-density condition in the quantum wire. This also suggests the possibility of 0.5G_0 switching, corresponding to single electron switching, even in quantum wire transistors., The Institute of Electronics, Information and Communication Engineers, English
  • Investigation of GaAs-based Single Electron Devices for Hexagonal BDD Single Electron Logic Circuits
    ABE Yuji; NAKAMURA Tatsuya; TAMURA Takahiro; KASAI Seiya; HASHIZUME Tamotsu; HASEGAWA Hideki, IEICE technical report, 105, 550, 21, 26, 20 Jan. 2006
    Towards future ultra-low power single electron logic circuits, single electron node devices implementing hexagonal binary decision diagram (BDD) quantum logic circuits were investigated. Two type of single electron BDD node devices called a branch switch type device and a node switch type device were designed utilizing GaAs-based nanowire branches controlled by nano-sized Schottky wrap gates (WPGs). The branch switch type device has single electron switches in each branch and the node switch type device has one quantum dot at node of Y-junction. Both devices were fabricated and their basic properties were characterized. Suitable device design and structure for the hexagonal BDD circuits were discussed from viewpoints of high-density integration, fabrication process, power consumption., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Study on Switching Characteristics of Quantum Wire Transistors and Single Electron Transistors Controlled by Schottky Wrap Gate for Ultra-low Power Quantum Nano-Integrated Logic Circuits
    KASAI Seiya; YUMOTO Miki; HASEGAWA Hideki, IEICE technical report, 105, 550, 15, 20, 20 Jan. 2006
    To confirm the ultra-low power consumption capability of quantum nano integrated logic circuits, such as nanoprocessors, switching characteristics of GaAs-based quantum wire transistors and single electron transistors controlled by nanometer-scale Schottky wrap gates (WPGs) were investigated theoretically and experimentally. Experimental data of subthreshold factor and logic swing values were found to be proportional to the temperature that could be explained by the theory. However, the some quantum wire transistors showed non-ideal temperature dependence of the logic swing, which were different from the theoretical prediction as well as the electron wave interaction and the tunneling. This indicated that there were another physical mechanisms controlling the logic swing value in the quantum wire transistors., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Investigation of Anomalous Gate Leakage Currents and Gate Control in AlGaN/GaN HFETs having Nanometer-Scale Schottky Gates
    KASAI Seiya; KOTANI Junji; HASEGAWA Hideki; HASHIZUME Tamotsu, IEICE technical report, 105, 435, 47, 52, 18 Nov. 2005
    Anomalous gate leakage current and gate control anomaly in AlGaN/GaN HFETs having nanometer-scale Schottky gates were investigated both experimentally and theoretically. It was found that the gate leakage current in the nanometer-scale Schottky gates consisted a lateral tunneling current at the gate edge through the high electric field domain at gate periphery due to large potential difference between the gate metal and the AlGaN surface. The gate control characteristics of nanometer-scale Schottky gate was indicated to be controlled by a so called virtual gate, where the surface potential at the gate periphery was modulated by the lateral gate leakage current, and it should degrade the scalability of the gate control., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Lateral Tunneling Transport in Sub micron Gates on AlGaN/GaN HFETs
    KOTANI Junji; KASAI Seiya; HASEGAWA Hideki; HASHIZUME Tamotsu, IEICE technical report, 105, 329, 67, 70, 13 Oct. 2005
    The gate leakage characteristics of AlGaN/GaN heterostrcuture field effect transistors (HFETs) were systematically investigated in an attempt to clarify possible effects of surface states. The experiments were compared with rigorous computer simulations. It was found that leakage currents in large area Schottky diodes are governed by tunneling leakage currents vertical to Schottky interface. On the other hand, in the nanometer-scale Schottky contacts on AlGaN/GaN HFETs, our analysis indicated additional lateral leakage components. By combining vertical and lateral tunneling components, the experimental behavior could be reproduced on computer. Thus lateral components can affect to leakage current behavior and related trapping in nanometer-scale gates., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Implementation of Ultra-Low Power Nanoprocessors based on Hexagonal BDD Quantum Circuits
    KASAI Seiya; YUMOTO Miki; TAMURA Takahiro; HASEGAWA Hideki, IEICE technical report. Electron devices, 104, 622, 31, 38, 20 Jan. 2005
    Implementation of ultra-low power nanoprocessors (NPUs) based on hexagonal BDD quantum circuits are investigated. The circuits and systems are implemented utilizing hexagonal nanowire networks controlled by nano-Schottky gates, and they operate with a few electrons utilizing quantum transport for ultra-low power consumption. Based on this architecture, subsystems and elemental parts of digital signal processors including ALUs were designed and fabricated. The hexagonal BDD-based 2-bit NPUs were successfully designed and their correct operations were confirmed by circuit simulation. Power consumption and size of the NPUs were also discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Large Conductance Modulation in Interdigital Gate HEMT Device due to Surface Plasma Wave Interactions and Its Device Application
    HASHIM Abdul Manaf; TAKEUCHI Mariko; KASAI Seiya; HASHIZUME Tamotsu; HASEGAWA Hideki, Extended abstracts of the ... Conference on Solid State Devices and Materials, 2004, 664, 665, 15 Sep. 2004
    English
  • Design and Implementation of Hexagonal Quantum BDD Logic Subsystems for Nanoprocessor Arithmetic Logic Processing
    KASAI Seiya; YUMOTO Miki; TAMURA Takahiro; HASEGAWA Hideki, Technical report of IEICE. SDM, 103, 164, 45, 48, 02 Jul. 2003
    Utilizing a hexagonal binary-decision diagram (BDD) quantum circuit technology, design, implementation and application of logic subsystems are studied for next-generation ultra-small and ultra-low power digital processing units, nanoprocessors. Subsystems including adders, substractors and comparators are successfully designed on hexagonal networks without branch crossover. 2 and 4 bit adders are fabricated on GaAs-based hexagonal nanowire networks controlled by Schottky wrap gate (WPG) with an effective device density over 10 million/cm^2. Correct operation of the 2-bit adder is obtained. A BDD 2-bit arithmetic logic unit (AUL) is designed with small device count compared with that in Si CMOS ALUs., The Institute of Electronics, Information and Communication Engineers, English
  • TBPを用いたGSMBE法により成長したIn0.5Ga0.5P/GaAsヘテロ界面特性の制御
    各務高明; 石川史太郎; 葛西誠也; 長谷川英機, 応用物理学関係連合講演会講演予稿集, 50th, 1, 358, 27 Mar. 2003
    Japanese
  • Binary Decision Diagram Logic Integrated Circuit Subsystems Based on Control of Compound Semiconductor Nanowire Networks
    KASAI Seiya; YUMOTO Miki; HASEGAWA Hideki, Technical report of IEICE. SDM, 102, 640, 17, 22, 03 Feb. 2003
    To realize ultra-high density and ultra-low power consumption quantum nanodevice logic integrated circuits, implementation of logic subsystems by a hexagonal quantum BDD logic circuit approach using compound semiconductor-based nanowire networks is investigated. BDD subsystems including adders and comparators are designed based on planar hexagonal layout without nanowire crossovers. Circuit fabrication process realizing 4.5×<10>^7 devices/^2 is developed. QWR-based BDD 2-bit and 4-bit adders are successfully fabricated and correct operation of the 2-bit adder is confirmed in a classical transport regime at room temperature. Design of register circuits utilizing WPG nanodevices is also discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • TBPを用いたGSMBE法により作製したIn0.5Ga0.5P/GaAsヘテロ構造における秩序構造の制御
    各務高明; 石川史太郎; 葛西誠也; 長谷川英機, 応用物理学会学術講演会講演予稿集, 63rd, 1, 290, 24 Sep. 2002
    Japanese
  • Realization of High-Density III-V Quantum Integrated Circuits by A Hexagonal Binary Decision Diagram Quantum Circuit Approach
    KASAI Seiya; YUMOTO Miki; MURANAKA Tsutomu; FUKUSHI Tetsuo; HASEGAWA Hideki, IEICE technical report. Electron devices, 102, 177, 15, 18, 26 Jun. 2002
    Feasibility of a novel hexagonal binary decision diagram (BDD) quantum circuit approach based on Schottky wrap gate (WPG) control of AlGaAs/GaAs hexagonal nanowire network has been demonstrated through design and fabrication of fundamental logic functions and full adders. Quantum BDD node devices were designed and realized utilizing WPG-controlled quantum wire (QWR) and single electron (SE) switches. BDD basic logic elements including AND were fabricated by integratin g the WPG BDD node devices and they operated correctly through either quantum transport at low temperature or many electron classical transport at room temperature. Power-delay products for QWR and SE-type devices were estimated 10^<-17> J and 10^<^22> J, respectively. A hexagonal BDD full adder for arbitrary bits on a hexagonal network without nanowire crossover was successfully designed. QWR-based BDD full adders were fabricated on the AlGaAs/GaAs etched hexagonal nanowire network with node density of 2.5 × 10^7 cm^2. The obtained results indicated the capability of the present approach for large scale quantum device integration., The Institute of Electronics, Information and Communication Engineers, English
  • Hexagonal Quantum BDD Integrated Circuit Utilizing GaAs Schottky Wrap Gate Structures
    KASAI Seiya; YUMOTO Miki; HASEGAWA Hideki, IEICE technical report. Electron devices, 101, 619, 9, 14, 23 Jan. 2002
    A novel hexagonal quantum BDD integrated circuit technology is described. This circuit is based on a binary decision diagram (BDD) logic architecture and it is implemented by gate-controlled quantum wire and single electron devices arranged on a hexagonal network, which is realized by Schottky wrap gate (WPG) control of GaAs-based hexagonal nanowire networks.Quantum wire and single electron node devices were successfully fabricated and characterized.Then, basic logic circuits including a half adder were realized and their logic operations were confirmed.Feasibility for large scale integration in this new circuit technology was demonstrated by design and fabrication of full adder circuits., The Institute of Electronics, Information and Communication Engineers, Japanese
  • GaN dry etching process for quantum nanostructure formation
    JIN Zhi; ENDO Makoto; HASHIZUME Tamotsu; KASAI Seiya; HASEGAWA Hideki, IEICE technical report. Electron devices, 101, 618, 19, 26, 22 Jan. 2002
    The reactive ion beam etching (RIBE) of GaN and AlGaN/GaN using methane-based plasmas was investigated. Methane/hydrogen/argon gas mixture resulted in a rough etched GaN surface and severe N-depletion layer. The addition of nitrogen gas resulted in a smooth etched GaN surface with comparable rms roughness to the original one and in a lower etch rate. In addition, the near stoichiometric etched GaN surface was obtained. Photoluminescence study showed that the addition of nitrogen gas drastically improved the optical properties of the etched AlGaN/GaN heterostructures. Using the optimized etching condition, we successfully fabricated the AlGaN/GaN nanowire with the width or 110nm, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Fabrication and Characterization of InGaAs/InAlAs Insulated Gate Pseudomorphic HEMTs Having a Silicon Interface Control Layer
    XIE Yong-Gui; KASAI Seiya; TAKAHASHI Hiroshi; JIANG Chao; HASEGAWA Hideki, IEICE Transactions on Electronics, 84, 10, 1335, 1343, 01 Oct. 2001
    A novel InGaAs/InAlAs insulated gate (IG) pseudomorphic high electron mobility transistor (PHEMT) having a silicon interface control layer (Si ICL) is successfully fabricated and characterized. Systematic efforts to characterize and optimize the insulated gate structure and the PHEMT fabrication process were made by using in-situ X-ray photoelectron spectroscopy (CPS) and capacitance-voltage (C-V) techniques. This led to successful fabrication of a novel IG-PHEMT showing excellent stable DC characteristics with a good pinch off and a high transconductance (177mS/mm), very small gate leakage currents, very high gate breakdown voltages (about 40 V) and respectable RF characteristics f_T = 9GHz and f_max = 38 GHz., IEICE, English
  • Reactive Ion Beam Etching of GaN and AlGaN for Nano-structure Fabrication Using Methane-Based Gas Mixtures
    ENDO Makoto; JIN Zhi; KASAI Seiya; HASEGAWA Hideki, Extended abstracts of the ... Conference on Solid State Devices and Materials, 2001, 320, 321, 25 Sep. 2001
    English
  • A Novel GaAs Binary Decision Diagram Device Having Quantum Wire Branch-Switches Controlled by Wrap Gates
    YUMOTO Miki; KASAI Seiya; HASEGAWA Hideki, Extended abstracts of the ... Conference on Solid State Devices and Materials, 2001, 304, 305, 25 Sep. 2001
    English
  • Surface Passivation of Epitaxial Multi-Layer Structures for InP-Based High Speed Devices by an Ultrathin Silicon Layer
    XIE Yong-Gui; TAKAHASHI Ken; TAKAHASHI Hiroshi; CHAO Jiang; KASAI Seiya; HASEGAWA Hideki, The Transactions of the Institute of Electronics,Information and Communication Engineers. C, 84, 9, 872, 882, 01 Sep. 2001
    InP系高速デバイスの作製に用いられるInAlAs/InGaAs/InAlAs/InP多層エピタキシャル薄膜構造を超薄膜シリコン界面制御層(Si ICL)を用いて表面不活性化する手法について基礎的検討を行い, 次の3点について新しい知見を得た.(1)表面にInGaAsキャップ層がない場合とある場合について, ひずみ効果及び量子状態制御を考慮し, 不活性化構造の理論的設計と最適化を行った.(2)設計された不活性化構造を実現するプロセスの検討を行い, Si ICL形成及び窒化プロセスによるSiN_x/Si ICL構造形成条件を最適化するとともに, InGaAsキャップ層の重要性を実験的に明らかにした.(3)最適プロセスによる表面不活性化構造について, デバイスと同一の絶縁性基板上に作製可能なプレーナ形MIS容量素子により多層薄膜MIS構造の界面電子物性を評価し, Si ICLの有用性を実証した., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Single Electron BDD Devices Based on A GaAs Schottky Wrap Gate Structure
    KASAI Seiya; AMEMIYA Yoshihito; HASEGAWA Hideki, IEICE technical report. Electron devices, 100, 642, 1, 7, 22 Feb. 2001
    Towards the next generation information processing logic architecture, single electron binary decision diagram (BDD) devices based on a GaAs Schottky wrap gate (WPG) technology are discussed. The key devices of the single electron BDD architecture, BDD node devices, were designed by using the WPG structure having AlGaAs/GaAs etched nanowire and nanometer-length Schottky gates. The WPG BDD node device were fabricated and their basic properties were characterized. A single electron BDD OR logic circuit utilizing the WPG BDD node devices was also successfully fabricated and its proper operation was confirmed. BDD logic circuit design and its WPG implementation are also mentioned., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Optimization and Application of GaAs-based Quantum Wire Transistors Utilizing Schottky In-Plane Gates and Wrap Gates
    YUMOTO Miki; IWAYA Masanobu; KASAI Seiya; HASEGAWA Hideki, IEICE technical report. Electron devices, 100, 642, 27, 33, 22 Feb. 2001
    Basic device characteristics GaAs Shottky in-plane gate (IPG)-and wrap gate (WPG)-based quantum wire transistors were investigated, and the device structures were optimized for their integrated circuit applications. The gate controllability in each gate structure including the gate-voltage dependence of effective wire width was characterized by current-voltage and magnetoresistance measur ements. The control of conductance step characteristics and the threshold voltage in the IPG/WPG quantum wire transistors were also discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Proposal and Fabrication of a QMESFET
    AKAZAWA M.; KASAI S.; HASHIZUME T.; HASEGAWA H., IEICE technical report. Electron devices, 100, 641, 89, 96, 21 Feb. 2001
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the proposed device as a ULSI device by reducing its size., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Compound Semiconductor-Based Quantum Devices Utilizing Schottky In-Plane-Gate and Wrap-Gate Structures and Their Application to Functional Integrated Circuits
    Kasai S; Okada H; Iwaya M; Yumoto M; Hasegawa H, Proceedings of the Society Conference of IEICE, 2000, 2, 176, 177, 07 Sep. 2000
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Electrical properties and interfacial reaction in Cu/n-InP contact
    TAKEYAMA Mayumi B.; ITAI Junichi; NOYA Atsushi; HASHIZUME Tamotsu; KASAI Seiya; HASEGAWA Hideki, IEICE technical report. Electron devices, 100, 236, 29, 34, 21 Jul. 2000
    The relationship between the electrical property and the interfacial reaction in the Cu/n-InP contact has been studied. Auger electron spectroscopy(AES) and X-ray photoelectron spectroscopy(XPS) analyses showed the existence of distinct phases at the Cu/InP interface in the as-deposited specimen, due to the nonuniform interfacial reaction. The nonuniform reaction at the interface results in the existence of multi barrier heights in the I-V characteristic of the Cu/InP contact. It is revealed that the formation of the uniform interlayer at the electrode/InP interface is crucial to obtain the excellent electrical property of the contact., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Prospects and Key Issues for Compound Semiconductor Quantum Devices
    HASEGAWA Hideki; KASAI Seiya, IEICE technical report. Electron devices, 100, 147, 43, 48, 21 Jun. 2000
    Prospects and key issues for the III-V compound semiconductor quantum devices are discussed, introducing the results recently obtained at RCIQE. A vailability of highly controllable epitaxial growth techniques, superb heterointerfaces, varieties of material selections, superb electron transport and large quantum effects, makes such devices extremely attractive. In this paper, issues related to quantum nanostructure formation, quantum devices, materials and processing technologies and circuit and system architecture are discussed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Quantum-Dot Logic Systems Based on Graphic Representation of Digital Functions
    YAMADA Takashi; KINOSHITA Yoshitaka; KASAI Seiya; AMEMIYA Yoshihito; HASEGAWA Hideki, Technical report of IEICE. SDM, 99, 618, 1, 6, 10 Feb. 2000
    We proposed creating novel logic systems by combining the quantum-dot arrays based on the Schottky-wrap-gate structure with the concept of graphic representation of digital functions. As an example, we proposed the method of constructing quantum-dot logic circuits based on the binary decision diagram. Sample structures were designed for elemental logic circuits and adder circuits. Computer simulation showed that the designed structures can perform correct logic operation., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Electrical Characterization on Nano-Schottky Contacts Fabricated Using the Electrochemical Process
    SATO Taketomo; KASAI Seiya; OKADA Hiroshi; HASEGAWA Hideki, Technical report of IEICE. SDM, 99, 618, 79, 84, 10 Feb. 2000
    The current transport characteristics of nanometer-sized Schottky contacts were investigated from theoretical and experimental viewpoints. A theoretical calculation of the 3D potential distributions has shown that the potential shape underneath the nano-Schottky contacts is greatly modified by the surface Fermi level pinning on the air exposed free surfaces. This leads to non-linear log I-V characteristics which are different from a standard thermionic emission characteristics obtained on the macro-Schottky contacts. On the other hand, the Pt nano-particles were selectively formed using the in situ electrochemical process, their I-V measurements were made using an conductive AFM system. The log I-V curves of the nano-Schottky contacts showed non-linear characteristics and could be very well explained by the theoretical I-V curves considering the "environmental" Fermi level pinning., The Institute of Electronics, Information and Communication Engineers, Japanese
  • 共有二分決定グラフにもとづく量子ドット回路の設計
    木下純臣; 山田崇史; 葛西誠也; 雨宮好仁; 長谷川英機, 応用物理学関係連合講演会講演予稿集, 47th, 1, 2000
  • 量子ドットアレイによるグラフ論理システム
    山田崇史; 葛西誠也; 雨宮好仁; 長谷川英機, 応用物理学関係連合講演会講演予稿集, 47th, 1, 2000
  • 量子ドット論理システムのための単電子レジスタ回路
    木下純臣; 山田崇史; 葛西誠也; 雨宮好仁; 長谷川英機, 応用物理学会学術講演会講演予稿集, 61st, 1, 2000
  • Formation of Quantum Dots by Schottky Wrap Gate Control of 2DEG and Its Application to Single Electron Transistors
    KASAI Seiya; SATOH Yoshihiro; OKADA Hiroshi; HASHIZUME Tamotsu; HASEGAWA Hideki, Extended abstracts of the ... Conference on Solid State Devices and Materials, 1997, 480, 481, 16 Sep. 1997
    English
  • Basic Control Characteristics of Novel Schottky In-Plane and Wrap Gate Structures Studied by Simulation and Transport Measurements in GaAs and InGaAs Quantum Wires
    Okada Hiroshi; Kasai Seiya; Fujikura Hajime; Hashizume Tamotsu; Hasegawa Hideki, Jpn J Appl Phys, 36, 6B, 4156, 4160, 1997
    To clarify the control properties of Schottky in-plane gates (IPGs) and Schottky wrap-gates (WPGs) recently employed in the high-temperature operation of compound semiconductor single electron devices, computer simulations and transport measurements were carried out for gated quantum wires (QWRs). Both types of QWRs showed clear Shubnikov-de Haas oscillations. Non-linear Landau plots confirmed gate-controlled 1D transport in the QWRs. In the GaAs IPG QWR, the effective wire width was found to change linearly with gate bias, whereas this was not observed in the InGaAs WPG QWR. These gate control behaviors are in excellent agreement with theory. Near pinch-off, clear conductance oscillation was seen in both QWRs., The Japan Society of Applied Physics, English
  • Realization of GaAs-Based Single Electron Devices Having Single and Multiple Dots by Schottky In-Plane-Gate Control of Two Dimensional Electron Gas
    KASAI Seiya; JINUSHI Kei-ichiroh; OKADA Hiroshi; TOMOZAWA Hidemasa; HASHIZUME Tamotsu; HASEGAWA Hideki, Extended abstracts of the ... Conference on Solid State Devices and Materials, 1996, 443, 445, 26 Aug. 1996
    English
  • Fabrication of Pt-Gate InP MESFET by In-Situ Electrochemical Process
    UNO Shouichi; HASHIZUME Tamotsu; WU Nan-Jian; KASAI Seiya; HASEGAWA Hideki, IEICE technical report. Electron devices, 95, 314, 15, 20, 19 Oct. 1995
    Novel fabrication technique of Pt/InP Shottky barriers has been developed. Pt/n-InP interfaces with no transient interlayer was realized by the in-situ electrochemical process, reuslting in the high Schottky barrier height of 0.86eV and the ideality factor of 1.13. Applying this novel fabrication process to InP MESFETs, Pt-gate InP MESFETs were successfully fabricated. Good gate control of drain currents with pinch-off and the effective channel mobility of 1840cm^2/v・s were obtained. The devices operate even under the positive gate bias., The Institute of Electronics, Information and Communication Engineers, Japanese
  • A Novel Lateral Surface Superlattice Structure Utilizing Schottky Barrier Height Control by Doped Silicon Interface Control Layers
    KASAI Seiya; HASEGAWA Hideki, Extended abstracts of the ... Conference on Solid State Devices and Materials, 1995, 797, 799, 21 Aug. 1995
    English
  • 0.86eV Platinum Schottky Barrier on Indium Phosphide by In-Situ Electrochemical Process and Its Application to MESFETs
    UNO S.; HASHIZUME T.; KASAI S.; WU N.-J.; HASEGAWA H., Extended abstracts of the ... Conference on Solid State Devices and Materials, 1995, 959, 961, 21 Aug. 1995
    English
  • The formation of quantum structures by surface potential and the effects of surface states.
    葛西誠也; 宇野正一; 中村隆俊; 友沢秀征; 石川靖彦; 橋詰保; 長谷川英機, 応用物理学関係連合講演会講演予稿集, 42nd, Pt 3, 1995
  • Control of GaAs Schottky Barrier Height by Si Interface Control Layer and its Application for Quntum Structures
    Kasai Seiya; Uno Syo-ichi; Hashizume Tamotsu; Hasegawa Hideki, IEICE technical report. Electron devices, 94, 268, 79, 86, 11 Oct. 1994
    Control of GaAs Schottky barrier heights by Si Interface Control Layer(Si ICL)was attempted.It was shown that Si ICL makes it possible to control the barrier height over the range of 300meV with suitable ICL thickness and doping into the ICL. To control the Schottky barrier height spatially at quantum structures,FIB technique was investigated.FIB-induced interface state gave the Schottky barrier height change in the range of 290meV.This indicates the possibility of control Schottky barrier heights in nano-meter scale., The Institute of Electronics, Information and Communication Engineers, Japanese
■ Books and other publications
■ Lectures, oral presentations, etc.
■ Syllabus
  • 応用デバイス回路学特論, 2024年, 修士課程, 情報科学院
  • 先端デバイス学特論, 2024年, 博士後期課程, 情報科学研究科
  • 応用デバイス回路学特論, 2024年, 博士後期課程, 情報科学院
  • 科学・技術の世界（1単位）, 2024年, 学士課程, 全学教育
  • 科学・技術の世界（1単位）, 2024年, 学士課程, 全学教育
  • 電子デバイス工学, 2024年, 学士課程, 工学部
■ Affiliated academic society
  • IEEE
  • 電子情報通信学会
  • 応用物理学会
■ Research Themes
  • Development of Controllable Myoelectric Arm Prosthesis Based on Electronic Motion Coordination and Reflex Action
    Grants-in-Aid for Scientific Research
    01 Apr. 2021 - 31 Mar. 2025
    葛西 誠也
    １．モーター消費電力に基づく力覚センシングメカニズム：ロボットアームを動作させるサーボモーターの消費電力を同時計測できる機構を設け、負荷重量が異なるあるいは動きを変えた時に消費電力の時系列が変化し区別されることを確認した。
    ２．表面筋電筋電位積分機構のパラメータ最適化：身体運動制御系をリザバーとみなした独自の運動推論機構においては、双極誘導波形の線型結合では学習ができないことがわかりその原因について解析した。またこの知見に基づき、動作推論可能にする筋電波形積分機構を最適化した。
    ３．表面筋電センサの性能向上：配線雑音抑制により安定化を行なった。動作安定化に伴いセンサの検出利得を高めることが可能になり、前腕に取り付けた表面電極で指の動きに伴う極微弱筋電を捕捉できるようになった。
    ４．バウンスバック回路の再構成化：アメーバ型アナログ最適化計算システム（アナログ電子アメーバ）において最適化の制約式を実装するバウンスバック回路を再構成化するためにクロスバーを用いた構成を設計し、小規模回路を試作評価し再構成可能であることおよびこれをもちいた解探索が可能であることを実験実証した。
    ５．アメーバ型最適化システムを応用した自律歩行ロボットの行動発達メカニズムの改善。視覚に頼らない身体感覚で行動を評価する目的で、加速度センサによる歩行距離の推論機能の実装を行なった。推論移動距離が実測値と大きく異なっていた。加速度時系列解析より原因の理解と解決の見通しを得た。
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 23K20956
  • Development of Controllable Myoelectric Arm Prosthesis Based On Electronic Motion Coordination and Reflex Action
    Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    01 Apr. 2021 - 31 Mar. 2025
    葛西 誠也
    運動神経系を伝達する筋電信号を取得し随意運動（ユーザーが意図する運動）をリアルタイムかつ高精度に読み出す手段として機械学習の一種であるリザバー計算フレームワークの適用にあたり、適切な規模のシステムを見出すために必要となるリザバー計算系の構成・規模と計算能力の関係について検討を行った。系の数理構造から複雑ネットワーク理論と線形代数を組み合わせたモデル化に至り、リザバーを構成するネットワークおよびノード非線形性と系の関数表現力の関係性が見えつつある。
    リザバー計算系に対する深い理解のため物理電子リザバー実装を同時並行して行い、半導体トンネルダイオードによる非線形ノードおよび非線形振動子によるダイナミックノード構成とその接続のシミュレーションおよび実測と評価解析を行った。いずれのノード形態も実現に成功し、さらに実デバイスを用いた実装における課題と対応策について多くの知見を得た。
    アメーバ型最適化問題解探索と強化学習を組み合わせた独自の自律ロボットのためのその場行動発見・行動発達の仕組みを創出した。さらに、探索型行動で得た知識をベースに高効率行動へ移行する機構「２段階発達」を編み出し、小規模モデルに対して数値シミュレーションを行い、高効率なパターン反復型の行動を見つけて自発的に移行できることを実証した。本成果は、筋電義手が使用者の随意運動と環境や対象物の違いによるその場の動作調整に可能にし、反射能力の実装につながる。
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 21H01379
  • Intelligence of nano-material networks
    Grants-in-Aid for Scientific Research Fund for the Promotion of Joint International Research (Fostering Joint International Research (B))
    07 Oct. 2019 - 31 Mar. 2023
    松本 卓也; 葛西 誠也; 赤井 恵; 谷 洋介; 玉木 孝
    本研究の採択が10月であったことから、外国渡航を伴う研究計画を年度内に実施することは困難であると判断した。そこで、2019年度は、次の２点に絞って研究を実施した。
    １．本研究の申請の前提となった共同研究を、本研究の一部として進めた。2018年度に研究代表者の松本の学生が、本研究の相手先研究者であるオランダTwente大学のWiel教授の研究室に留学した。その間行われた研究を完成するために、学生が帰国後、大阪大学で行われていた追加実験を、本研究の一部として行った。具体的には、脳型デバイスを目指したポリアニリンネットワークのインピーダンス測定を行った。Twente大学で前年度に実施した研究結果と良い整合性のあるデータを得ることができた。また、本研究採択前からWiel研から大阪大学へ留学することが決まっていた学生の研究を、本研究の一部として行った。金微粒子ネットワークを用いた脳型デバイスを作る研究の一部で、電子線リソグラフィを用いて、ネットワーク型ギャップ電極の作製に成功した。
    ２．本研究の研究協力者である九州工業大学の田中啓文教授により、本研究の研究協力者であるUCLAのGimzewski教授を招いて、九州工業大学にニューロモルフィックAIハードウェア研究センターを設立するための研究会が開催された。そこで、本研究の共同研究者が全員この研究会に参加し、本研究の打ち合わせ会を兼ねることにした。打ち合わせの結果、本研究者の若手である大阪大学の谷洋介助教、京都大学の玉木孝特任助教をオランダTwnete大学に長期で派遣し、共同研究を進めることが決まった。
    Japan Society for the Promotion of Science, Fund for the Promotion of Joint International Research (Fostering Joint International Research (B)), Osaka University, 19KK0131
  • 行動変容を支援する最適化・機械学習融合コンパクトAIの開発
    A-STEP トライアウト
    May 2021 - Mar. 2022
    青野真士
    JST, 北海道大学, Principal investigator
  • Development of adoptive nonlinear myoelectric signal detection technique for user-friendly man-machine interface
    Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    01 Apr. 2018 - 31 Mar. 2021
    Kasai Seiya
    In this study, we developed a user-friendly man-machine interface (MMI) that can detect the user's motion and intention using surface electric myosignal (EMS). The newly developed MMI includes the reduction of the error in the EMS detection and a MMI-integrable vibration haptic feedback device with rich expression. The EMS detection error was reduced by a self-parameter optimization mechanism in our unique nonlinear EMS detection technique, which could make the system adaptive to the user and the environment. We also showed an artificial haptic device integrating two small vibration motors that could generate a super-low frequency vibration down to 2.5 Hz by beating, which was two orders of magnitude smaller than that from single motor.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 18H01487
  • Detection and characterization of single-electron-trap in a semiconductor based on a metal-tip-induced current noise mechanism
    Grants-in-Aid for Scientific Research Grant-in-Aid for Challenging Exploratory Research
    01 Apr. 2016 - 31 Mar. 2019
    Kasai Seiya
    A novel characterization technique for detecting single electron trap in a semiconductor surface has been developed in this research project. The characterization system is composed by integrating a scanning probe microscope, achieving atomic-scale spatial resolution owing to a very narrow metal tip, and a charge amplification mechanism using a semiconductor nanowire through the local capacitive coupling between the metal tip and the electron trap. The dynamic behavior of the electron in a single trap is detected as current noise in the semiconductor nanowire and the electric properties of the trap are characterized by the noise analysis. This characterization technique has been successfully applied to the characterization of the single molecular nano-particles.
    Japan Society for the Promotion of Science, Grant-in-Aid for Challenging Exploratory Research, Hokkaido University, 16K14240
  • Molecular Architectonics: Orchestration of Single Molecules for Novel Functions
    Grants-in-Aid for Scientific Research
    28 Jun. 2013 - 31 Mar. 2018
    TADA Hirokazu
    We promoted joint studies by researchers in molecular design / synthesis, surface physics, molecular nanotechnology, semiconductor physics, information technology and theoretical physics, and published 591 papers on the following topics: (1) Precise design of molecules and molecular aggregates, (2) Structure and electronic state molecules on various electrodes, (3) Guiding principles for single molecular junctions showing nonlinear / asymmetrical current-voltage characteristics and switching characteristics by electric and magnetic field, and (4)Preparation of stochastic resonance devices utilizing the inherent noise of the element and the self-pulsating induced by voltage application.
    These results greatly contribute to progress in the field of single molecular electronics and open up research strategies on novel memory and computing systems based on molecular networks.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research on Innovative Areas (Research in a proposed research area), Osaka University, 25110001
  • Implementation of information processing function on single-molecule-integrated networks and improvement of its reliability
    Grants-in-aid for scientific research on innovative area
    Oct. 2013 - Mar. 2018
    KASAI Seiya
    MEXT, Principal investigator, Competitive research funding
  • マンーマシンインターフェースのための非侵襲型確率共鳴生体信号検出技術の開発
    FS program
    Apr. 2013 - Mar. 2016
    KASAI Seiya
    STARC, Principal investigator, Competitive research funding
  • Investigation on ultra-low-power electron transport in compound semiconductor-based 1D Brownian ratchet
    Grants-in-aid for challenging exploratory research
    Apr. 2011 - Mar. 2014
    KASAI Seiya
    JSPS, Principal investigator, Competitive research funding
  • Study on nonlinear mechanism in semiconductor nanowire three branch junction device and its control
    Grants-in-aid for scientific research (B)
    Apr. 2010 - Mar. 2013
    KASAI Seiya
    JSPS, Principal investigator, Competitive research funding
  • R&D of Ultra-low-voltage operation of super-parallel III-V semiconductor-based fine transistor
    ALCA
    Sep. 2011 - Sep. 2012
    KASAI Seiya
    JST, Principal investigator, Competitive research funding
  • 半導体トランジスタ確率共鳴を利用した耐雑音生体信号検出技術の開拓
    IS program
    Aug. 2011 - Jul. 2012
    KASAI Seiya
    STARC, Principal investigator, Competitive research funding
  • R&D of compound semiconductor-based fundamental quantum logic gates for quantum computation
    科研費奨励研究(A)
    Apr. 2000 - Mar. 2012
    KASAI Seiya
    JSPS, Principal investigator, Competitive research funding
  • Research on stochastic resonance nanodevices and their integration for novel noise-robust information processing systems
    PRESTO
    Oct. 2007 - Mar. 2011
    KASAI Seiya
    JST, Principal investigator, Competitive research funding
  • Stochastic resonance nanodevices and their integrated systems
    JST Basic Research Programs (Precursory Research for Embryonic Science and Technology :PRESTO)
    2007 - 2011
    Competitive research funding
  • Information-processing system using reaction-diffusion dynamics in multi-medium quantum integrated circuits
    Grants-in-Aid for Scientific Research
    2008 - 2010
    AMEMIYA Yoshihito; KASAI Seiya; ASAI Tetsuya
    We proposed a single-electron device that is analogous to the reaction-diffusion system, a chemical complex system producing various dynamic phenomena in the natural world. Our electrical reaction-diffusion device consists of a two-dimensional array of single-electron nonlinear oscillators that are combined with one another through capacitive coupling. Computer simulation revealed that the device produces animated spatiotemporal patterns of node voltages, e.g., a rotating spiral pattern similar to that of a colony of cellular slime molds and a dividing-and-multiplying pattern that reminds us of cell division.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 20360149
  • Semiconductor Nanowire Electronics by Selective-Area Metal-Organic Vapor Phase Epitaxy
    Grants-in-Aid for Scientific Research
    2006 - 2010
    FUKUI Takashi; AMEMIYA Yoshihito; MOTOHISA Junichi; KASAI Seiya; HARA Shinjiro
    A selective growth method for semiconductor nanowires by using electron beam lithography and metal organic vapor phase epitaxy has been established. The crystal structure and optical properties of GaAs and InP nanowires grown were characterized by electron microscopy and photoluminescence. Transistors, light emitting diodes and solar cells using heterostructure/p-n junction nanowires were fabricated to investigate the device characteristics, which showed promise for application to future nano-electronics.
    Japan Society for the Promotion of Science, Grant-in-Aid for Specially Promoted Research, Hokkaido University, 18002003
  • Ultra-small and ultra-low-power nanoprocessor based on hexagonal BDD quantum logic architecture
    Grants-in-aid for young scientists (A)
    Apr. 2005 - Mar. 2008
    KASAI Seiya
    JSPS, Principal investigator, Competitive research funding
  • Single-electron stochastic resonance in a quantum-dot-integrated device controlled by nanoscale Schottky gates
    Grants-in-aid for exploratory research
    Apr. 2006 - Mar. 2007
    KASAI Seiya
    JSPS, Principal investigator, Competitive research funding
  • Bio-inspired signal processor consisting of coupled quantum-dot devices
    Grants-in-Aid for Scientific Research
    2006 - 2007
    AMEMIYA Yoshihito; KASAI Seiya; ASAI Tetsuya; HIROSE Tetsuya
    In this work, we proposed a bio-inspired signal processing device that imitated the dynamics of reaction-diffusion systems combined with neural networks. A reaction-diffusion system (RD system) is a chemical complex system in which chemical reactions and material diffusion coexist in a nonequilibrium state. It is producing various dynamic phenomena in the natural world. Constructing an electrical analog of reaction-diffusion systems combined with neural networks will enable us to generate artificial biodynamics on a LSI chip and develop bio-inspired information-processing systems.
    We proposed constructing an electrical analog of RD systems, i.e., an electrical RD system consisting of quantum-dot circuits. An RD system can be considered an aggregate of chemical nonlinear oscillators interacting with one another, so we can construct electrical RD systems by using electrical oscillators instead of chemical ones. We used, as the electrical oscillator, a quantum-dot circuit that produced nonlinear oscillation caused by the Coulomb blockade phenomenon. The action of diffusion in RD systems can be imitated by capacitive coupling between the oscillators. By arranging coupled oscillators into a network, we designed a quantum-dot RD system. We also proposed constructing an electrical neural network consisting of quantum-dot circuits. The electrical neural network is composed of threshold devices and weighted coupling synapses consisting of monostable single-electron oscillators and coupling capacitors. We showed through computer simulation that the RD system combined with neural networks produced electrical dissipative structures, or animated spatiotemporal patterns of node potential in the circuit, which was a characteristic similar to that in chemical RD systems.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 18360156
  • Reliability improvement of GaN-based devices by controlling defects and interfaces
    Grants-in-Aid for Scientific Research
    2005 - 2006
    HASHIZUME Tamotsu; KASAI Seiya; SATO Taketomo; KANEKO Masamitsu
    The purpose of the research is to improve the stability of the GaN-based devices by controlling defects and interfaces. We have characterized electronic states of defects and impurities in GaN and A1GaN, as well as their correlation with degradation phenomena in various kinds of devices, such as the current collapse, the gate leakage current, electric breakdown, etc.
    1)We performed deep level transient spectroscopy (DLTS) measurements on the Schottky contacts fabricated on the Al_0.26Ga_0.74N surfaces, and detected a deep electron trap with an activation energy of 0.9 eV and a density higher than 1 x 10^16 cm^<-3>.
    2)We developed a diffusion process for carbon doping into GaN, using a CN_x/SiN_x bilayer. The C-rich CN_x layer was deposited on n-GaN while we used stoichiometric Si3N4 as a capping layer. The secondary ion mass spectroscopy (SIMS) result indicated the C diffusion into n-GaN in concentration higher than 1x 1018 cm-3 after an annealing at 1000 ℃ for 2hrs.
    3)We have developed a novel surface process for controlling electronic states at the AlGaN surfaces, The process consists of the deposition of ultrathin Al layer on the A1GaN surfaces and the in-situ UHV anneal at 700 ℃, resulting in the gettering of oxygen donors from the A1GaN surface into the Al layer. After the process, we observed pronounced reduction of the leakage current and the temperature-dependent current-voltage characteristics in the Ni/AlGaN interfaces.
    4)By applying the high-temperature or UV-assisted capacitance-voltage measurements on the insulator-GaN interfaces, we could firstly observed the response from the interface states near midgap of GaN. We also found that the ultrathin Al-oxide layer on the GaN surface was very effective in controlling interface states.
    5)We investigated the operation stability of the A1GaN/GaN high-mobility transistors (HEMTs) after applying the off-state stress at high temperatures. The devices without the unltrathin-Al based surface control process showed significant degradation in DC characteristics after the stress, mainly due to the increase in the drain conductance. On the other hand, no change in the the DC characteristics were observed in HEMTs with the surface process after the stress.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 17360133
  • 半導体2次元電子ガスのプラズマ波によるミリ波・テラヘルツ進行波デバイスの研究
    科学研究費助成事業
    2005 - 2005
    長谷川 英機; 葛西 誠也; 佐藤 威友; 賈 鋭
    テラヘルツ(THz)帯の周波数領域では、効率よく電磁波を発生・増幅・検波する技術が確立されておらず「テラヘルツギャップ」とよばれている。本研究の目的は、ミリ波・テラヘルツ帯におい.て増幅・検波機能を果たす新しい進行波型半導体デバイスの可能性を、理論的および実験的に検討することにある。その原理は、半導体の2次元電子ガス中に発生するドリフトプラズマ波と、遅波構造による電磁波の空間高調波との相互作用を利用することにある。
    (1)電子の慣性項を取り入れたより厳密なプラズマ方程式をもとに、TMモード解析とグリーン関数を含むFredholm積分方程式による空間高調波解析を行い、その結果ミリ波・THz帯で、大きな負性コンダクタンスが得られことを確認した。そして、その機構が高周波では1サイクルあたりの衝突頻度が飛躍的に減ることにあることを示した。
    (2)さらに、解析を半導体の表面準位の効果を含むものに拡張し、表面状態による電界分布の変化やスクリーニングが、デバイスに悪影響を及ぼすことを見出した。
    (3)AlGaAs/GaAsヘテロ接合上に、インターディジタル型遅波構造を形成したデバイスについて、マイクロ・ミリ波帯で予備実験を行い、おおきなコンダクタンス変調を観測するとともに、理論解析と実験がよく一致することを実証した。これらは、Jpn.J.Appl.Physの正規論文やISDRS(Dec.2005)の国際会議で報告された。
    (4)大電力の観点からさらにすぐれた材料は、窒化物系であるが、ヘテロ接合形成技術や電極形成技術が遅れている。このため、この材料のヘテロ界面や表面制御の研究や調査を活発に同時進行させ、多くの成果を得て、これらを公表した。
    日本学術振興会, 萌芽研究, 北海道大学, 17656099
  • 有機金属気相成長高密度量子ナノ構造による単電子集積エレクトロニクス
    科学研究費助成事業
    2001 - 2005
    福井 孝志; 長谷川 英機; 雨宮 好仁; 本久 順一; 橋詰 保; 葛西 誠也
    平成17年度は、有機金属気相成長(MOVPE)選択成長法による量子ナノ構造を利用した単電子素子・単電子回路の実現と、高密度量子ナノ構造の周期配列の形成技術の確立を目的として、以下の研究を行った。
    1.前年度に続き、単電子トランジスタの論理回路応用を目的に集積化を進めた。2分決定グラフ論理による1ビット加算器に関して、論文公表することが出来た。また、選択成長により作製したリッジ型量子細線と、自己形成InAs量子ドットを組み合わせた、フローティングゲート型の単電子メモリーの試作とその動作特性解析を進めた。試作した素子を温度20Kで評価した結果、ドレイン電流に、ゲート電圧に対する明瞭な時計回りのヒステリシスが観測された。印加するゲート電圧の最大値を変化させる実験、あるいはヒステリシスの幅やしきい値のシフト量およびその温度依存性、さらにゲート電圧を変化させた後の時間応答などの実験結果により、このヒステリシスが、ゲート側から注入された電子が量子ドットに保持されることに起因することが示された。
    2.単電子素子の高温動作化を目的として、選択成長を用い、新しい種類のナノ構造の作製を試みた。具体的には、円形あるいは6角形のマスク開口部を有するGaAs(111)B基板に対して選択成長を行うことにより、直径50nm、長さは9μmにもおよぶ、GaAsナノワイヤ構造の作製に成功した。そして、このナノワイヤを単電子素子へと応用するプロセス手法を考案した。同様な構造はInP(111)A基板上にも作製した。まずInPナノワイヤ、横方向成長を利用したInP/InAsコアシェル構造、さらにInP/InAs/InP横方向ヘテロ構造からなるInAs量子リングを作製し、その光学的特性から、量子閉じ込め構造を確認した。
    日本学術振興会, 学術創成研究費, 北海道大学, 13GS0001
  • Surface/interface control of high-frequency and high-power transistors based on GaN materials
    Grants-in-Aid for Scientific Research
    2002 - 2004
    HASHIZUME Tamotsu; MOTOHISA Junichi; KASAI Seiya; AKAZAWA Masamichi
    The purpose of this research was to characterize and control surface/interface properties of GaN-based material systems such as AlGaN/GaN hetrostrcutures for the stability improvement of high-frequency and high-power transistors. The main results obtained are listed below :
    (1)Serious deterioration such as stoichiometry disorder and nitrogen deficiency (N deficiency) was found at the processed AlGaN surfaces. This resulted in formation of a localized deep donor level related to N vacancy (V_N), causing excess leakage currents at the AlGaN Schottky interface and serious drain current collapse in AlGaN/GaN heterostructure field effect transistors.
    (2)An Al_2O_3-based surface passivation scheme including the N_2-plasma surface treatment was proposed and applied to an insulated-gate type HFET. A large conduction-band offset of 2.1 eV was achieved at the Al_2O_3/Al_<0.3>Ga_<0.7>N interface. No current collapse was observed in the fabricated Al_2O_3 insulated-gate HFETs under both drain stress and gate stress.
    (3)From the detailed temperature-dependent current-voltage (I-V-T) measurements, we discussed the mechanism of leakage currents through GaN and AlGaN Schottky interfaces. The experiments were compared to the calculations based on thin surface barrier model in which the effects of surface defects were taken into account. Our simulation results indicates that the barrier thinning caused by unintentional surface-defect donors enhances the funneling transport processes, leading to large leakage currents through GaN and AlGaN Schottky interfaces.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), HOKKAIDO UNIVERSITY, 14350155
  • 半導体人工格子による磁性制御
    科学研究費助成事業
    2002 - 2003
    本久 順一; 須田 善行; 葛西 誠也
    平成15年度は、フラットバンド強磁性が実験的に確認できるという理論的予測がされている、周期0.7μmのInAsによるKagome格子を有機金属気相成長(MOVPE)選択成長法により作製するするため、以下のような実験を行った。
    まず、SiO_2膜堆積を堆積したGaAs(111)A基板に対して、電子線リソグラフィ、およびウエットエッチングにより、MOVPE選択成長用のマスク基板を作製した。マスクのパターンは昨年度のものと同様、6角形あるいは3角形のマスクを周期的に配列させたものであるが、今回は、(111)B基板ではなく、(111)A基板を用いている。その後、窓明け部分へ、GaAsおよびInAsを、MOVPE選択成長を行った。
    まず、(111)Aプレーナ面では平坦な表面が得られる、温度500Cにおいて格子周期が1〜3μmのマスクパターンに対して、選択成長を行った場合、細線の交点部分にのみ、3次元的にInAsが成長するが、成長温度を下げると、3次元成長モードから2次元成長へと転移することが明らかとなった。この成長モードの転移は、成長温度の低下に伴う表面拡散長の減少によって説明でき、またGaAsとInAsの格子定数の差による歪みは、その成長界面で発生したミスフィット転移により緩和されていると考えられる。この結果、ピットを含み、表面平坦性には問題があるが、垂直{110}ファセットを側壁として有する細線の交差構造である、InAsによるKagome格子が、そのマスクパターンを踏襲して形成可能であることが示された。さらに、表面平坦性を改善するため、アルシン(AsH_3)分圧に対する依存性について調べた。その結果、AsH_3分圧を下げた場合に、表面平坦性に優れ、また横方向成長が抑制され、マスクパターンを踏襲したKagome格子構造が形成されることがわかった。
    以上に述べた成長条件の最適化の結果、温度400C・低AsH_3分圧という成長条件で、MOVPE選択成長により、周期0.7μmのInAs Kagome格子の形成に成功した。
    日本学術振興会, 萌芽研究, 北海道大学, 14655112
  • Single Electron Integrated Circuits Based on A BDD Architecture Utilizing Quantum Dots Controlled by Nano-Schottky Gates
    Grants-in-Aid for Scientific Research
    2001 - 2003
    HASEGAWA Hideki; AKAZAWA Masamichi; HASHIZUME Tamotsu; AMEMIYA Yoshihito; KASAI Seiya
    The purpose of this research was to investigate a novel single electron integrated circuit based on a binary-decision diagram (BDD) architecture utilizing quantum dots controlled by nano-Schottky gates. Main results are listed below :
    (1)A novel "hexagonal BDD quantum circuit approach" for realization of quantum LSIs, in which the BDD architecture is implemented on hexagonal nanowire network in high dense, was proposed. Various logic subsystems and arithmetic logic units (ALUs) were successfully designed utilizing the novel circuit approach.
    (2)Elemental BDD devices (node devices) were realized using GaAs-based etched nanowires controlled by Schottky wrap gates (WPGs). They showed clear path switching characteristics from low temperature to room temperature. Power-delay product (PDP) of WPG-controlled single electron node devices was found to be as small as 10^<-22> J. Capability of GHz operation of WPG switches was confirmed experimentally by direct measurement of cut-off frequency.
    (3)Basic BDD logic circuits were fabricated on etched hexagonal nanowire networks controlled by WPGs and they operated correctly in a quantum regime at low temperature. They were found to be possible to operate correctly even at room temperature by trading off of PDP values. Then, high-density integrated circuit fabrication process realizing 45 million devices/cm^2 has been established. Utilizing this process, 2-bit BDD adder circuits were fabricated and their correct operations were confirmed, and 8-bit adder was also successfully fabricated.
    (4)Formation of hexagonal quantum nanowire network structures by MBE selective growth on patterned substrates was investigated and ultra-high density network fabrication technology of 240 million nodes/cm^2 for GaAs-based systems and 1 giga nodes/cm^2 for InP-based systems have been established. Branch switches and node devices were successfully fabricated utilizing the selectively MBE grown nanowires and their correct operations were confirmed.
    (5)For surface passivation of III-V semiconductor quantum nanostructures, a technique using ultra-thin Si and c-GaN interface control layers (ICLs) was investigated for III-V materials and optimized. It was found that GaAs surfaces was successfully passivated by preparation of Ga-rich (4×6) reconstructed surface as an initial surface for the ICL formation. Ultra-small minimum interface state density of 4×10^<10> cm^<-2>eV^<-1> was obtained in the SiO_2/GaAs interface.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (A), HOKKAIDO UNIVERSITY, 13305020
  • Research and development of III-V quantum wire transistor-based logic and memory circuits operating near the quantum limit
    Grants-in-Aid for Scientific Research
    2000 - 2001
    HASEGAWA Hideki; KASAI Seiya; HASHIZUME Tamotsu
    The purpose of this research was to study and develop novel logic and memory circuits that operate ultra-small delay-power product near the quantum limit by utilizing III-V compound semiconductor quantum wire transistors. The main results obtained are listed below :
    (1) A novel single electron memory device having a metal nano-dot for charging and a Schottky in-plane gate (IPG) quantum wire transistor (QWRTr) for dot-charge detection was proposed, fabricated and its basic operation was confirmed.
    (2) As single electron integrated circuits, single electron inverter circuits utilizing Schottky wrap gate (WPG) GaAs single electron transistor (SETs), including QWRTr road type inverters and complementary inverters, were designed, fabricated and characterized. Transfer gain larger than unity was obtained in the QWRTr road type inverter.
    (3) A novel approach for quantum logic circuits operating with ultra-low delay-power product near the quantum limit. It is based on implementation of a binary decision diagram (BDD) logic architecture by quantum wire transistors, was proposed. BDD node devices were fabricated using GaAs etched nanowire and nano-Schottkys and their basic operations were confirmed. Fundamental logic circuits constructed by integrating the BDD devices operated correctly.
    (4) Highly uniform and size-controllable InGaAs and GaAs embedded ridge quantum wire arrays were grown by selective MBE growth as basic starting structures for quantum wire transistors. Submicron-pitch high-density InGaAs quantum wire arrays were realized by an atomic hydrogen treatment and optimization of pre-growth process.
    (5) For successful surface passivation of III-V QWRTrs, their surfaces were characterized by scanning tunneling spectroscopy (STS). The mechanism of anomalous STS spectra was clarified. From this analysis, it was found that surface states with continuously distribution in space and energy cause surface Fermi level pinning. Surface passivation method using ultrathin Si interface control layer was optimized and verified by contactless C-V, PL and STS.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), HOKKAIDO UNIVERSITY, 12555083
  • Metal contact formation to GaN based on the interface control technologies
    Grants-in-Aid for Scientific Research
    1999 - 2001
    HASHIZUME Tamotsu; KASAI Seiya; KANESHIRO Chinami; MOTOHISA Junichi; SEKI Shouhei; TAKEYAMA Mayumi
    The purpose of this research was to develop the formation processes of a stable Schottky contact and a ohmic contact with a low resistivity to GaN, based on the systematic characterization of the GaN surfaces and metal-GaN interfaces. The main results obtained are listed below:
    (1) Chemistry and electronic properties of GaN surfaces after various kinds of surface treatments were characterized by x-ray photoelectron spectroscopy (XPS). Strong upward band bending of 1.4 eV was found at the air-exposed GaN surface. This is due to the high density of surface state. The surface treatment in the NH_4OH solution and the ECR-excited N_2 plasma significantly decreased the surface band bending to 0.5 eV, indicating the reduction of the Fermi level pinning.
    (2) We investigated the leakage mechanism through metal/n-GaN interfaces by detailed current-voltage-temperature (I-V-T) measurements. A large deviation from the thermionic emission (TE) transport was observed in the reverse I-V curves with a large excess leakage. A novel barrier- modified thermionic-field emission (TFE) model based on presence of near-surface fixed changes or surface states was proposed to explain the observed large reverse leakage currents.
    (3) A novel surface passivation process for AlGaN/GaN heterostructures utilizing an ultrathin Al_2O_3 layer (〜 1 nm) was proposed. The reverse leakage current for the Schottky gate contact on the Al_2O_3-passivated heterostructure surface was reduced by three orders of magnitude than that for the conventional Schottky gate structure. C-V results showed good gate controllability two-dimensional electron gas (2DEG) by the novel gate structure.
    (4) Mg-doped GaN surfaces were characterized by XPS. The surface accumulation of Mg at the Mg-doped GaN seems to cause the formation of the disordered surface layer including a tenacionus oxide layer, leading to the large downward band-bending of 1.3-1.4 eV at the surface. The surface treatment in ECR-N_2 plasma was very effective in removing such a disordered layer.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), HOKKAIDO UNIVERSITY, 11555081
  • Control of Metal-Compound Semiconductor Interfaces by Formation of Nano-Scale Schottky Contacts and Its Application
    Grants-in-Aid for Scientific Research
    1999 - 2000
    HASEGAWA Hideki; JIANG Chao; KASAI Seiya; HASHIZUMA Tamotsu
    The purpose of this research was attempt to control metal-compound semiconductor interfaces by forming size-controlled nano-Schottky contacts and thereby removing the Fermi level pinning. The main results obtained are listed below :
    (1)Metal-semiconductor(M-S)interfaces formed by an electrochemical process was found to consist of metal nano-dots. By changing applied pulse conditions, dot size and the number of the dots could be controlled. Formation of small and uniform-size-metal dot relaxes Fermi level pinning at M-S interfaces and enhanced the metal-workfunction dependence of Schottky barrier heights. This opened up a possibility to control Schottky barrier heights toward the Schottky limit.
    (2)By the combination of the electrochemical process and electron-beam lithography techniques, a few ten nanometer-size nano-Schottky line gates and a few ten nanometer-sized highly uniform nano-dot arrays were successfully formed.
    (3)Current transport through M-S interfaces in single metal nano-dot-compound semiconductor systems was investigated by a conductive tip atomic force microscopy(AFM). The transport mechanism was theoretically studied by a newly developed device simulator for nano-Schottky interfaces. In the single metal-dot nano-Schottky contacts, reduction of the metal nano-dot size enhanced the metal-workfunction dependence. However, environmental surface Fermi level pinning around the nano-Schottky gates was found to affect strongly the potential control.
    (4)Nano-Schottky interface formation technology utilizing the electrochemical process were applied to realization of various quantum devices including GaAs-and InGaAs-based quantum wire transistors, single electron devices and memory devices. The fabricated devices showed proper and designed operations, and the effectiveness of the present technology was confirmed.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B)., HOKKAIDO UNIVERSITY, 11450115
  • Novel Insulated Gate Structure having Ultrathin Si Quantum Well for Realization of InP-Based Ultra High-Frequency and High-Power Devices
    Grants-in-Aid for Scientific Research
    1998 - 1999
    HASEGAWA Hideki; KASAI Seiya; FUJIKURA Hajime; HASEZUME Tamotsu; UEDA Daisuke
    The purpose of this study is to provide a breakthrough for realization of InP-based ultra high-frequency and high-speed devices using a novel insulated gate structure having a "ultrathin Si quantum well". The main results obtained are listed below:
    l ) Novel in-situ characterization methods for semiconductor free surfaces as well as MIS interfaces during the interface formation process were established based on a UHV-based contactless C-V method and a photoluminescence surface state spectroscopy (PLSィイD13ィエD1).
    2) By combining these methods with a UHV-STM/STS and a XPS analyses, the pinning center was found not to be a point with discrete deep level, but to be an area with gap state continuum. This seems to support the unified disorder induced gap state (DIGS) model for Fermi level pinning proposed by our group, which is the basis of the concept of present "insulated-gate structure having ultrathin Si quantum well".
    3) The insulated-gate structure having ultrathin Si quantum well with precisely controlled quantum well thickness was successfully realized by MBE growth of ultrathin psedomorphic Si layer on the InP-based materials and subsequent thinning of the Si layer by ECR plasma-induced partial nitridation.
    4) Under the optimum ECR nitridation condition, this process realized the InP MIS structure with extremely low interface state density of 2x10ィイD110ィエD1cmィイD1-2ィエD1eVィイD1-1ィエD1. This value is the best of all the oxide-free InP MIS structures reported so far.
    5) An InP MISFETs fabricated using the present insulated gate structure having the ultrathin Si quantum well exhibited excellent gate control capability, high effective electron mobility and stable operation. The drift of the drain current was found to be as small as 1.9% after 10ィイD14ィエD1 s operation.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, 10555098
■ Industrial Property Rights
  • 解探索システム、解探索方法及び解探索プログラム
    Patent right, 青野 真士; 葛西 誠也; 大古田 香織; 福田 真悟, Amoeba Energy株式会社, 国立大学法人北海道大学
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    特許第7627453号
    202503015805751980
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    Patent right, 葛西 誠也; 斉藤 健太; 末藤 直樹; 青野 真士, 国立大学法人北海道大学, Amoeba Energy株式会社
    特願2018-093127, 14 May 2018
    特開2019-198902, 21 Nov. 2019
    特許第7141614号
    202203004179880818
  • ロボット、ロボット制御方法、およびプログラム
    Patent right, 葛西 誠也; 斉藤 健太; 青野 真士, 国立大学法人北海道大学, Amoeba Energy株式会社
    特願2018-093128, 14 May 2018
    特開2019-198903, 21 Nov. 2019
    特許第7141615号
    202203010785622115
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    Patent right, 葛西 誠也; 末藤 直樹, 国立大学法人北海道大学
    特願2021-012464, 28 Jan. 2021
    特開2022-115728, 09 Aug. 2022
    202203009045396725
  • 解探索システム、解探索方法及び解探索プログラム
    Patent right, 青野 真士; 葛西 誠也; 大古田 香織; 福田 真悟, Amoeba Energy株式会社, 国立大学法人北海道大学
    特願2021-073972, 26 Apr. 2021
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    202203017063960401
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    Patent right, 葛西 誠也; 斉藤 健太; 青野 真士, 国立大学法人北海道大学, Amoeba Energy株式会社
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    特開2019-198903, 21 Nov. 2019
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    Patent right, 葛西 誠也; 斉藤 健太; 末藤 直樹; 青野 真士, 国立大学法人北海道大学, Amoeba Energy株式会社
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    特開2019-198902, 21 Nov. 2019
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    Patent right, 法元 盛久; 有塚 祐樹; 大八木 康之; 葛西 誠也; 松本 勉; 成瀬 誠; 竪 直也, 大日本印刷株式会社, 国立大学法人北海道大学, 国立大学法人横浜国立大学, 国立大学法人九州大学, 国立研究開発法人情報通信研究機構
    特願2016-234745, 02 Dec. 2016
    特開2018-089845, 14 Jun. 2018
    201803003412772665
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    Patent right, 田所 幸浩; 葛西 誠也; 一木 輝久, 株式会社豊田中央研究所, 国立大学法人北海道大学, 国立大学法人名古屋大学
    特願2015-097061, 12 May 2015
    特開2016-213725, 15 Dec. 2016
    201703007857995336
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    Patent right, 田所 幸浩; 一木 輝久; 葛西 誠也, 株式会社豊田中央研究所, 国立大学法人北海道大学
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    特開2013-135244, 08 Jul. 2013
    特許第5900848号
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    Patent right, 葛西 誠也, 国立大学法人北海道大学
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    Patent right, 田所 幸浩; 葛西 誠也; 一木 輝久, 株式会社豊田中央研究所, 国立大学法人北海道大学, 国立大学法人名古屋大学
    特願2015-097061, 12 May 2015
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    201703007857995336
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    Patent right, 葛西 誠也, 国立大学法人北海道大学
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    Patent right, 葛西 誠也, 国立大学法人北海道大学
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    Patent right, 葛西 誠也, 国立大学法人北海道大学
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    Patent right, 葛西 誠也, 独立行政法人科学技術振興機構
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