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NAKAJIMA Hiroomi

Faculty of EngineeringSpecially Appointed Professor

Researcher basic information

■ Degree
  • B.S., Hokkaido University, Mar. 1984
  • M.S., Hokkaido University, Mar. 1986
  • Ph.D. in Engineering, Hokkaido University, Mar. 2025
■ URL
researchmap URLホームページURL■ Various IDs
J-Global ID

Research activity information

■ Papers
■ Other Activities and Achievements
  • Floating Body RAM Technology and its Scalability to 32nm Node and Beyond
    中島博臣; 楠直樹; 篠智彰; 東知輝; 大澤隆; 藤田勝之; 幾見宣之; 松岡史宜; 福田良; 渡辺陽二; 南良博; 坂本篤史; 西村潤; 浜本毅司; 仁田山晃寛, 電子情報通信学会技術研究報告, 107, 1, 53, 58, Apr. 2007
    東京 : 電子情報通信学会, Japanese
  • Floating Body RAM Technology and its Scalability to 32nm Node and Beyond
    中島博臣; 楠直樹; 篠智彰; 東知輝; 大澤隆; 藤田勝之; 幾見宣之; 松岡史宜; 福田良; 渡辺陽二; 南良博; 坂本篤史; 西村潤; 浜本毅司; 仁田山晃寛, 電子情報通信学会技術研究報告, 107, 1(ICD2007 1-16), 1, 4, 2007
    Technologies and improved performance of the Floating Body RAM are demonstrated. Reducing SOI thickness to 43nm, a 16Mb chip yield of 68% has been obtained. Device simulation proves that the Floating Body Cell is scalable to the 32nm node keeping signal margin (threshold voltage difference) and data retention time constant., IEEE
  • A floating body cell (FBC) fully compatible with 90nm CMOS technology(CMOS IV) for 128Mb SOI DRAM
    Mutsuo Morikado; A. Sakamoto; Naoki Kusunoki; Takeshi Hamamoto; Hiroomi Nakajima; Kosuke Hatsuda; K. Inoh; Takashi Ohsawa; Hiroyoshi Tanimoto; Katsuyuki Fujita; Tomoki Higashi; Yoshihiro Minami; Tomoaki Shino; Akihiro Nitayama; Nobutoshi Aoki, IEEE InternationalElectron Devices Meeting, 2005. IEDM Technical Digest., 307, 310, 06 Apr. 2006
    A 128Mb SOI DRAM with FBC (floating body cell) has been successfully developed for the first time. Two technologies have been newly implemented. (i) In order to realize full functionality and good retention characteristics, the well design has been optimized both for the array device and the peripheral circuit. (ii) Cu wiring has been used for bit line (BL) and source line (SL), which leads to increasing the signal of the worst bit in the array and also realizes the full compatibility with 90nm CMOS technology, IEEE
  • Technology development of 128Mb-FBC (Floating Body Cell) Memory by 90nm CMOS process
    南良博; 篠智彰; 坂本篤史; 東知輝; 楠直樹; 藤田勝之; 初田幸輔; 大沢隆; 青木伸俊; 谷本弘吉; 森門六月生; 中島博臣; 井納和美; 浜本毅司; 仁田山晃寛, 電子情報通信学会技術研究報告, 106, 2, 25, 30, Apr. 2006
    東京 : 電子情報通信学会, Japanese
  • A 128Mb DRAM Using a 1T Gain Cell (FBC) on SOI
    大沢隆; 藤田勝之; 初田幸輔; 東知輝; 森門六月生; 南良博; 篠智彰; 中島博臣; 井納和美, 電子情報通信学会技術研究報告, 105, 1(ICD2005 1-12), 2005
  • FBC (Floating Body Cell) for embedded DRAM on SOI
    K. Inoh; Hidemi Ishiuchi; Tamio Ikehashi; Takeshi Kajiyama; Takeshi Hamamoto; Takashi Ohsawa; Yoshiaki Fukuzumi; Katsuyuki Fujita; Yoshihiro Minami; Tomoki Higashi; Tomoaki Shino; Hiroomi Nakajima; T. Yamada; Hiroaki Yamada, 2003 Symposium on VLSI Technology. Digest of Technical Papers (IEEE Cat. No.03CH37407), 63, 64, 02 Mar. 2004
    The memory cell characteristics of the FBC (Floating Body Cell) have been experimentally verified by 0.175 /spl mu/m cell array for the first time. The FBC is a one-transistor gain cell, which is a suitable structure for the future embedded DRAM on SOI wafer. The memory cell layout and the process integration have been designed from the viewpoint of the logic process compatibility without sacrificing the data retention characteristics. The salicide process with the poly-Si plug is implemented into the process integration. The most important device characteristics for realizing the FBC is the threshold voltage difference (/spl Delta/ Vth) of the cell transistor between "1" state and "0" state. The key device parameters in order to enlarge the /spl Delta/ Vth are experimentally clarified. A /spl Delta/ Vth of 0.4 V has been obtained, which leads to 99.77% function bit yield of 96 Kbit ADM (Array Diagnostic Monitor). The retention time of 5 sec has been realized at the room temperature., Japan Soc. Applied Phys
  • A memory using one-transistor gain cell on SOI(FBC) with performance suitable for embedded DRAM's
    Hiroaki Yamada; Yoshiaki Fukuzumi; Tomoaki Shino; K. Inoh; T. Yamada; Tamio Ikehashi; Hiroomi Nakajima; Yoshihiro Minami; Takeshi Kajiyama; Takashi Ohsawa; Tomoki Higashi; Katsuyuki Fujita; Takeshi Hamamoto, 2003 Symposium on VLSI Circuits. Digest of Technical Papers (IEEE Cat. No.03CH37408), 93, 96, 01 Mar. 2004
    A 288 Kbit memory chip featuring a one-transistor gain cell on SOI of the size 0.21 /spl mu/m/sup 2/(7F/sup 2/ with F=0.175 /spl mu/m) which we named the floating body transistor cell (FBC) is presented and basic characteristics of the cell and the memory chip performance are disclosed. The threshold voltages of a cell transistor in the chip for the data "1" and for the data "0" are measured by using a direct access test circuit and a fail bit map for the 96 Kbit array is obtained. A sensing scheme which was designed to eliminate the effect of cell characteristics variation due to process and temperature fluctuation as common mode noise is verified to be working and the random access time is measured to be less than 100 ns. The characteristics of data hold demonstrate that the FBC can satisfy retention time specifications for some embedded memories. The access time and the data retention time show that the FBC has a potential to be used as a future embedded DRAM memory cell., Japan Soc. Appl. Phys
  • Highly scalable FBC (Floating Body Cell) with 25nm BOX structure for embedded DRAM applications
    K. Inoh; Takeshi Hamamoto; Katsuyuki Fujita; Akihiro Nitayama; I. Higashi; T. Yamada; Takashi Ohsawa; Mutsuo Morikado; Yoshihiro Minami; Hiroomi Nakajima; Tomoaki Shino, Digest of Technical Papers. 2004 Symposium on VLSI Technology, 2004., 132, 133, 01 Jan. 2004
    A novel FBC with 25nm-thick BOX (buried oxide) structure has been developed. A feature of new FBC is scalability in the case of thinner SOI, which promises embedded DRAM on SOI in future generations. Using 96Kbit array, the pause time distribution of FBC is demonstrated for the first time. Due to simplified structure, pause time variation of new FBC is significantly suppressed compared with conventional FBC., IEEE
  • Analysis of process margins for emitter-base self-alignment structures through a combination of simulation and experiment
    Toshihiko Iinuma; Nobuyuki Itoh; K. Inou; M. Kondo; Y. Tsuboi; Hiroomi Nakajima; C. Yoshino; Yasuhiro Katsumata; Hiroshi Iwai, Proceedings of the 1992 Bipolar/BiCMOS Circuits and Technology Meeting, 113, 116, 02 Jan. 2003
    The process margins of an emitter-base self-alignment structure were analyzed using two-dimensional simulations and experiments. The margins were obtained quantitatively in terms of ECL propagation delay time. It was found that the margin for emitter opening overetching was very large when the intrinsic base impurity was introduced before base sidewall formation. Misalignment of the emitter opening and the base opening was also analyzed. It was found that an alignment error of less than 0.2 mu m, which is within the misalignment margin of currently available steppers, does not lead to serious problems. >, IEEE
  • Memory cell for Embeded DRAM on SOI-FBC (Floating Boyd Cell)-
    南良博; 井納和美; 篠智彰; 山田浩玲; 中島博臣; 山田敬; 大沢隆; 東知輝; 石内秀美, 電子情報通信学会技術研究報告, 103, 262(ICD2003 66-79), 2003
  • 52 GHz epitaxial base bipolar transistor with high Early voltage of 26.5 V with box-like base and retrograded collector impurity profiles
    S. Matsuda; Hiroshi Iwai; S. Imai; Naoharu Sugiyama; K. Inou; Y. Kawaguchi; Hiroomi Nakajima; K. Yamada; Yasuhiro Katsumata; K. Usuda, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 217, 220, 17 Dec. 2002
    UHV-CVD epitaxial base transistors having 52 GHz cutoff frequency and 26.5 V Early voltage have been fabricated by adopting a box like base and retrograded collector impurity profiles. In addition, to improve the epitaxial film quality, a hydrotermination technique is used., IEEE
  • 0.5 μm silicon bipolar transistor technology for analog applications
    Toshihiko Iinuma; K. Inou; Yasuhiro Katsumata; S. Matsuda; Hiroshi Iwai; Hiroomi Nakajima; C. Yoshino; Nobuyuki Itoh, Proceedings of IEEE Bipolar/BiCMOS Circuits and Technology Meeting, 213, 216, 17 Dec. 2002
    A silicon bipolar technology for low power analog applications with a 0.5 /spl mu/m design rule has been developed. A maximum fT value of 24 GHz (@ VCE=2 V, IC=260 /spl mu/A) is obtained, as well as a 1/32 prescaler free-run frequency of 8.0 GHz (@ VCC=5 V, IC=600 /spl mu/A)., IEEE
  • Three-dimensional mechanical stress analysis of trench isolation along {111} gliding planes
    Yasuhiro Katsumata; C. Yoshino; Hiroomi Nakajima; K. Inou; Sadayuki Yoshitomi; S. Matsuda; Hiroshi Iwai, Proceedings of 1994 IEEE International Electron Devices Meeting, 885, 888, 17 Dec. 2002
    Three dimensional mechanical stress simulation has been applied to the trench isolation structure for bipolar LSIs. The accuracy of the simulation was confirmed by the micro Raman measurements of the actual trench structure. Considering the three dimensional analysis of the dislocation formation in the silicon crystal, there are 4 different {111} gliding planes at each point, and 3 specific gliding directions for each {111} plane along which the dislocation of silicon occurs. Thus 12 gliding directions exist at each point. Resolved shear stresses along the 12 directions have been calculated by the simulation. The simulated results basically agree with the results of dislocation formation in the experiment. This method is a very useful tool to analyze the dislocation or defect formation along {111} gliding planes of the trench isolation structure. >, IEEE
  • 0.3 μm BiCMOS technology for mixed analog/digital application systems
    K. Inoh; Hiroomi Nakajima; Hiroshi Naruse; Hiroshi Iwai; Yasuhiro Katsumata; Nobuyuki Itoh; Hiroyuki Sugaya; H. Nii; T. Yoshino, Proceedings of the 1997 Bipolar/BiCMOS Circuits and Technology Meeting, 68, 71, 23 Nov. 2002
    In this paper, 0.3 /spl mu/m BiCMOS technology for mixed analog/digital application is presented. This technology includes high f/sub max/ and high BVceo NPN transistor, 0.3 /spl mu/m CMOS, and passive elements. These elements are successfully implemented., IEEE
  • A 62.8 GHz fmax LP-CVD epitaxially grown silicon base bipolar transistor with extremely high early voltage of 85.7 V
    Hiroshi Naruse; C. Yoshino; K. Inou; S. Matsuda; Hiroomi Nakajima; Yasuhiro Katsumata; Hiroshi Iwai; Y. Tsuboi; Hiroyuki Sugaya, 1995 Symposium on VLSI Technology. Digest of Technical Papers, 131, 132, 19 Nov. 2002
    Optimization of fmax and VA values was investigated by changing Wcpi and NB Values of low temperature LP-CVD epitaxial base. It was found that there are optimum conditions which can realize concurrent extremely high fmax value-more than 50 GHz-and extremely high Vn value-more than 50V-in the case of silicon epitaxial base bipolar transistors with silicided emitter and base electrodes. Relatively flat profile of boron in the epitaxial base region can realize high Vn value with high fmax. NiSi emitter and base electrodes technology can further increase the fmax value. The highest fmax value of 62.86 Hz at a collector current of 1.7 mA was achieved. High BVCBO of 4.7 V, high VA of 85.7 V and low p/sub BI/ value of 8.5 k/spl Omega//sq were also realized at the same time., Japan Soc. Appl. Phys
  • High Performance 90nm node PD SOI CMOS Devices.
    中島博臣; 川中繁; 新居英明; 篠智彰; 東篤志; 井納和美; 幸山裕亮; 勝又康弘; 石内秀美, 電子情報通信学会技術研究報告, 102, 273, 31, 36, 22 Aug. 2002
    東京 : 電子情報通信学会, Japanese
  • Optimization of Low Power Shallow Trench Isolation BiCMOS Technology for Mixed Analog/Digital Application Systems
    TAKIMOTO K.; NAKAJIMA H.; KAWAI H.; YOSHINO C.; MIYAKAWA H.; SUGAYA H.; KATSUMATA Y.; NII H.; INOH K.; ISHIUCHI H., 電気学会電子デバイス研究会資料, 2002, 46, 7, 12, 07 Mar. 2002
    Japanese
  • 低消費電力型BiCMOS用シャロウトレンチ最適化の検討
    中島博臣; 古屋浩美; 新居英明; 井納和美; 勝又康弘; 川井博文; 吉野千博; 宮川裕之, 応用物理学会学術講演会講演予稿集, 61st, 2, 2000
  • An 0.3-μm Si epitaxial base BiCMOS technology with 37-GHz f/sub max/ and 10-V BV/sub ceo/ for RF telecommunication
    H. Furuya; Hiroshi Naruse; K. Inoh; C. Yoshino; Sadayuki Yoshitomi; Hiroshi Iwai; Hiroyuki Sugaya; Yasuhiro Katsumata; H. Nii; Hiroomi Nakajima, IEEE Transactions on Electron Devices, 46, 712, 721, 01 Apr. 1999
    In this paper, a 0.3-/spl mu/m BiCMOS technology for mixed analog/digital application is presented. A typical emitter area of this technology is 0.3 /spl mu/m/spl times/1.0 /spl mu/m. This technology includes high f/sub max/ of 37 GHz at the low collector current of 300 /spl mu/A and high BV/sub ceo/ of 10 V NPN transistor, CMOS with L/sub eff/=0.3 /spl mu/m, and passive elements. By using the shallow and deep trench isolation technology and nonselective epitaxial intrinsic base, the C/sub jc/ can be reduced to 1.6 fF, which is the lowest value reported so far. As a results, we have managed to obtain the high f/sub max/ at the low current region and high BV/sub ceo/ concurrently. These features will contribute to the development of high-performance BiCMOS LSI's for various mixed analog/digital applications., Institute of Electrical and Electronics Engineers (IEEE)
  • Semiconductor device and its manufacturing method.
    中島博臣, 東芝技術公開集, 17, 29, 1999
  • Semiconductor device and its manufacturing method.
    中島博臣, 東芝技術公開集, 17, 68, 1999
  • Manufacturing technique for semiconductor device.
    中島博臣, 東芝技術公開集, 14, 59, 1996
  • Sub-20 ps high-speed ECL bipolar transistor with low parasitic architecture
    Nobuyuki Itoh; S. Matsuda; C. Yoshino; T. Iinuma; Hiroomi Nakajima; K. Inou; Yasuhiro Katsumata; Y. Tsuboi; Hiroshi Iwai, IEEE Transactions on Electron Devices, 42, 399, 405, 01 Mar. 1995
    Reducing parasitic capacitance and resistance is an effective means of both improving ECL gate delay and increasing f/sub T/ values. In this paper, we demonstrate a device with sub-20 ps t/sub pd/ values even at f/sub T/=23 GHz, a performance which has been achieved by implementing a number of techniques. These include 1) low-stress deep- and shallow-trench isolation to reduce C/sub CB/, 2) a low-concentration collector design to reduce C/sub CB/, 3) NiSi-salicided base and emitter electrodes to reduce R/sub B/, and 4) a shallow base formed by double diffusion technology for relatively high f/sub T/ with a low-concentration collector design. The low-concentration collector design gives the device a high breakdown voltage of 6.2 V. >, Institute of Electrical and Electronics Engineers (IEEE)
  • Study on Ultra Low Power Operation of Bipolar Transistor.
    中島博臣; 伊藤信之; 井納和美; 松田聡; 吉野千博; 勝又康弘; 岩井洋, 応用物理学関係連合講演会講演予稿集, 42nd, Pt 2, 1995
  • Planalized Al contact technology for sub-μm poly-emitter.
    中島博臣; 篠宮日出雄; 依田孝; 仁平裕之, 応用物理学会学術講演会講演予稿集, 51st, 2, 1990
  • The effect of unsymmetrical external base for self aligned bipolar transistors.
    伊藤信之; 中島博臣; 山口寿男; 月岡英了; 平川顕二; 仁平裕之, 電子情報通信学会全国大会講演論文集, 1989, Spring Pt.5, 1989
  • Anisotropic superconducting transition in ZrTe3
    Hiroomi Nakajima; Kazushige Nomura; Takashi Sambongi, Physica B+C, 143, 1-3, 240, 242, Nov. 1986
    Electrical resistivity and magnetic susceptibility of ZrTe3 were measured. The superconductivity below 2K is found not bulk but of filamentary., Elsevier BV
  • 7.ZrTe_3の異方的超伝導転移(北海道大学理学部物理学教室,修士論文題目・アブストラクト(1985年度)その1)
    中島, 博臣, 物性研究, 46, 4, 581, 582, 20 Jul. 1986
    この論文は国立情報学研究所の電子図書館事業により電子化されました。, 物性研究刊行会, Japanese
  • 1a-FB-6 ZrTe_3の超伝導II(半導体(擬一次元物質))
    中島 博臣; 野村 一成; 三本木 孝, 年会講演予稿集, 41.2, 192, 1986
    一般社団法人 日本物理学会, Japanese
  • 4a-F-2 ZrTe_3の超電導
    中島 博臣; 只木 進二; 三本木 孝, 秋の分科会予稿集, 1985.2, 196, 1985
    一般社団法人 日本物理学会, Japanese