Researcher Database

Researcher Profile and Settings

Master

Affiliation (Master)

  • Faculty of Information Science and Technology Media and Network Technologies Information Communication Systems

Affiliation (Master)

  • Faculty of Information Science and Technology Media and Network Technologies Information Communication Systems

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Profile and Settings

Degree

  • Doctor of Informatics(Kyoto University)

Profile and Settings

  • Name (Japanese)

    Tsutsui
  • Name (Kana)

    Hiroshi
  • Name

    201301093331929718

Alternate Names

Achievement

Research Interests

  • Wireless Communication   Processor Architecture   Image Processing   電子回路CAD   集積回路設計   

Research Areas

  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Communication and network engineering
  • Manufacturing technology (mechanical, electrical/electronic, chemical engineering) / Electronic devices and equipment
  • Informatics / Information networks
  • Informatics / Computer systems

Research Experience

  • 2019/04 - Today Hokkaido University Faculty of Information Science and Technology Associate Professor
  • 2013/05 - 2019/03 Hokkaido University Graduate School of Information Science and Technology Associate Professor
  • 2010/04 - 2013/04 Kyoto University Graduate School of Informatics Assistant Professor
  • 2007/04 - 2010/03 Osaka University Graduate School of Information Science and Technology Assistant Professor
  • 2005/04 - 2007/03 Kyoto University Graduate School of Informatics Assistant Professor

Education

  • 2000/04 - 2005/03  Kyoto University  Graduate School of Informatics  Department of Communications and Computer Engineering
  • 1996/04 - 2000/03  Kyoto University  Faculty of Engineering  School of Electrical and Electronic Engineering

Committee Memberships

  • 2016/01 - Today   IEEE Hokkaido University Student Branch   Counselor
  • 2021/01 -2022/12   IEEE Sapporo Section   Student Activities Committee Chair
  • 2022   SASIMI 2022 (The 24th Workshop on Synthesis And System Integration of Mixed Information technologies) Publication Chair
  • 2021   SASIMI 2021 (The 23rd Workshop on Synthesis And System Integration of Mixed Information technologies)   Publication Chair
  • 2021   2021 International Symposium on Communications and Information Technologies (ISCIT 2021)   Publication Chair
  • 2021   2021 International Workshop on Smart Info-Media Systems in Asia (SISA 2021)   General Chair
  • 2020   IEEE TENCON 2020   Japan Sections Supporting Committee Member
  • 2019   2019 IEEE International Symposium on Circuits and Systems (ISCAS 2019)   Management Co-Chair

Awards

  • 2013/10 SASIMI Organizing Committee SASIMI 2013 Outstanding Paper Award
     Place-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy 
    受賞者: Takashi Imagawa;Masayuki Hiromoto;Hiroshi Tsutsui;Hiroyuki Ochi;Takashi Sato
  • 2009/10 IEEE/ACM/IFIP 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia2009) Best Paper Award
     A high-throughput pipelined architecture for JPEG XR encoding 
    受賞者: Koichi Hattori;Hiroshi Tsutsui;Hiroyuki Ochi;Yukihiro Nakamura
  • 2008/07 IPSJ Multimedia, Distributed, Cooperative and Mobile Symposium 2008 (DICOMO2008) Excellent Paper Award
     Dynamic Rate Control for Media Streaming in High-speed Mobile Network 
    受賞者: Masayuki Hiromoto;Hiroshi Tsutsui;Hiroyuki Ochi;Tomoyuki Osano;Norihiro Ishikawa;Yukihiro Nakamura
  • 2007/09 IEICE IEICE Society Conference, Video Compression Contest, First Prize
     Video Coding Scheme for Video Sequences Degraded by Noise of Old Motion Picture Films 
    受賞者: Hiroshi Tsutsui
  • 2005/09 IEICE IEICE Young Researcher's Award
     Efficient SRAM Architecture for JPEG2000 Entropy Coder 
    受賞者: Hiroshi Tsutsui;Hiroki Sugano;Takahiko Masuzaki;Hiroyuki Ochi;Takao Onoye;Yukihiro Nakamura
  • 2001/05 PARTHENON Technical Society PARTHENON Technical Society, ASIC Design Contest, Award of Excellence
     Design of 16bit Free CPU 
    受賞者: Hiroshi Tsutsui;Takahiko Masuzaki
  • 2000/05 PARTHENON Technical Society PARTHENON Technical Society, ASIC Design Contest, Encouragement Award
     Design of 16bit Free CPU 
    受賞者: Ryusuke Miyamoto;Hiroshi Tsutsui;Ryuta Nakanishi

Published Papers

  • Kota Hirai, Hiroshi Tsutsui, Ying He, Takeo Ohgane
    ISCIT 231 - 234 2023
  • Experimental Evaluation and Field Tests of LoRa Energy Consumption Optimization Approach Using Software-Defined Radio
    Kyotaro Kunii, Takuya Yasugi, Hiroshi Tsutsui, Takeo Ohgane
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 45 - 50 2022/09 [Refereed][Not invited]
  • Haojiong Wang, Hiroshi Tsutsui, Matteo Convertino
    4th IEEE Global Conference on Life Sciences and Technologies(LifeTech) 286 - 288 2022
  • Shingo Kato, Hiroshi Tsutsui
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 154 - 157 2021/09 [Refereed][Not invited]
  • Jimpu Suzuki, Hiroshi Tsutsui, Takeo Ohgane
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 71 - 76 2021/09 [Refereed][Not invited]
  • An Approach to Maximize SDMA Uplink Communication in an IoT Media Access Control Protocol
    Atsuki Kuriyama, Hiroshi Tsutsui
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 49 - 52 2020/12 [Refereed][Not invited]
  • Haruki Inaba, Hiroshi Tsutsui, Takuya Yasugi
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 135 - 138 2020/12 [Refereed]
  • Tomotaka Kawabata, Hiroshi Tsutsui
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 114 - 117 2020/12 [Refereed]
  • Jimpu Suzuki, Hiroshi Tsutsui, Takeo Ohgane
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 110 - 113 2020/12 [Refereed]
  • Takuto Fukusaki, Hiroshi Tsutsui, Takeo Ohgane
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 100 - 103 2020/12 [Refereed]
  • Myat Hsu AUNG, Hiroshi TSUTSUI, Yoshikazu MIYANAGA
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A (12) 1483 - 1493 0916-8508 2020/12/01
  • Robot Speech Recognition of Child Isolated Words
    Yoshikazu Miyanaga, Yu Tian, Hiroshi Tsutsui
    International STEM Education Conference (iSTEM-Ed 2020) 2020/11 [Refereed][Not invited]
  • Hiroshi Tsutsui, Kentaro Yamada, Akihiro Sudou, Yoshikazu Miyanaga
    2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC) 1423 - 1426 2309-9402 2019/11 [Refereed][Not invited]
  • Improvement on Children Speech Recognition under Low Signal-to-Noise Ratio Environment
    Yu Tian, Jiayue Tang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 4 - 6 2019/08 [Refereed][Not invited]
  • Robust Isolated Speech Recognition for Keyword Detection System Using Hidden Markov Model
    Jiayue Tang, Yu Tian, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 161 - 163 2019/08 [Refereed][Not invited]
  • Voice Activity Detection Using Running Spectrum Analysis for Noise Robust Speech Recognition
    Riku Takanashi, Tatsuya Nakagoshi, Noboru Hayasaka, Yoshikazu Miyanaga, Hiroshi Tsutsui
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 164 - 166 2019/08 [Refereed][Not invited]
  • Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of the 23rd Multi-conference on Systemics, Cybernetics and Informatics (WMSCI 2019) 2 7 - 10 2019/07 [Refereed][Not invited]
  • Dabwitso KASAUKA, Kenta SUGIYAMA, Hiroshi TSUTSUI, Hiroyuki OKUHATA, Yoshikazu MIYANAGA
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A (6) 775 - 782 0916-8508 2019/06/01 [Refereed][Not invited]
  • Yoshikazu Miyanaga, Masaki Miura, Tohru Gotoh, Junji Yamano, Takashi Imagawa, Hiroshi Tsutsui
    2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) 107 - 110 2018/11 [Refereed]
  • Jiayue Tang, Yu Tian, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2018 18th International Symposium on Communications and Information Technologies (ISCIT) 2018/09 [Refereed]
  • Keyword Detection Using F0-VAD in Robust Isolated Phase Recognition System
    Jiayue Tang, Yu Tian, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 121 - 124 2018/08 [Refereed][Not invited]
  • Robust Children Isolated Speech Recognition System Using RSA and RSF
    Yu Tian, Jiayue Tang, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 113 - 116 2018/08 [Refereed][Not invited]
  • An Evaluation of Entropy Coding Approaches in Block-Based Adaptive Lossless Image Coding Method for Embedded Systems
    Yunako Katagishi, So Tsuyuguchi, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2018/08 [Refereed][Not invited]
  • Takashi Imagawa, Takahiro Ikeshita, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 2017/11 [Not refereed][Not invited]
  • Robust Isolated Phrase Recognition System Using Running Spectrum Analysis
    Xiaonan Jiang, Tatsuya Nakagoshi, George Mufungulwa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Shini-ichi Abe
    Proceedings of Intelligent Transportation Society of America World Congress (ITS 2017) 2017/10 [Refereed][Not invited]
  • George Mufungulwa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Shin-Ichi Abe, Mitsuru Ochi
    ISSCS 2017 - International Symposium on Signals, Circuits and Systems 2017/09/12 [Refereed][Not invited]
     
    This paper proposes a new noisy robust speech recognition method. Under noise circumstances, several noise reduction methods have been developed and they are applied in various noise conditions. However, in case of similar pronunciation speech, for example, it is still not easy to realize high recognition accuracy. In this paper, the new processing algorithm into speech modulation spectrum is proposed as running spectrum analysis (RSA) and it is adequately applied to observed speech data. Using this method, the proposed system can improve about 1-4 % compared to current conventional methods.
  • An Evaluation of Phrase Rejection Using K-means Clustering for Robust Speech Recognition
    Xiaonan Jiang, Tatsuya Nakagoshi, Noboru Hayasaka, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 154 - 157 2017/09 [Refereed][Not invited]
  • An Accuracy Evaluation of WiFi Based Indoor Positioning System Using Estimated Reference Locations
    Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 321 - 326 2017/09 [Refereed][Not invited]
  • An Evaluation of Foreground Extraction Using Background Subtraction and GrabCut
    Kentaro Yamada, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 27 - 30 2017/08 [Refereed][Not invited]
  • Low-Cost Adaptive Block-Based Lossless Compression Method for Memory Bandwidth Reduction
    So Tsuyuguchi, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 97 - 100 2017/08 [Refereed][Not invited]
  • Robust Speech Recognition Using Low-pass Processing RSA in the Frequency Domain
    Tatsuya Nakagoshi, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 139 - 142 2017/08 [Refereed][Not invited]
  • Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga
    GI-CoRE GSQ, GSB & IGM Joint Symposium 2017/07 [Not refereed][Not invited]
  • Enhanced Running Spectrum Analysis for Robust Speech Recognition Under Adverse Conditions: Case of Japanese Speech
    George Mufungulwa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Shini-ichi Abe
    ECTI Transactions on Computer and Information Technology (ECTI-CIT) 2017/07 [Refereed][Not invited]
  • An Evaluation of Atmospheric Light Estimation in Haze Removal Method Using Variational Model Based Transmission Map Estimation
    Kenta Sugiyama, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of Workshop on Circuits and Systems 57 - 60 2017/05 [Not refereed][Not invited]
  • Speech Recognition Using TVLPC Based MFCC for Similar Pronunciation Phrases
    George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Shini-ichi Abe, Yoshikazu Miyanaga
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 1918 - 1921 2017/05 [Refereed][Not invited]
  • An FPU-based hardware implementation of Gauss-Jordan matrix inversion operation for MIMO-OFDM demodulation
    Takahiro Ikeshita, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido 174 - 175 2016/11 [Not refereed][Not invited]
  • An Evaluation of Haze Removal Method Using Variational Model Based Transmission Map Estimation
    Kenta Sugiyama, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Society Conference 2016/09 [Not refereed][Not invited]
  • Robust Speech Recognition using MFCC with Triangular Mel Filtered Time Varying LPC
    George Mufungulwa, Hiroshi Tsutsui, Alia Asheralieva, Yoshikazu Miyanaga
    IEICE Society Conference 2016/09 [Not refereed][Not invited]
  • An Accuracy Evaluation of Motion-Compensated Frame Interpolation Using High-Resolution Video and High-Frame-Rate Video
    Hiroki Uesaka, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 2016/09 [Refereed][Not invited]
  • One-block shared memory FFT processor by using new memory addressing approach
    Licheng Rao, Shingo Yoshizawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2016/08 [Refereed][Not invited]
  • New MFCC with Triangular Mel Filtered Time Varying LPC
    George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2016/08 [Refereed][Not invited]
  • Speech Recognition using MFCC with Time Varying LPC for Similar Pronunciation Phrases
    George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Yoshikazu Miyanaga
    The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2016/07 [Refereed][Not invited]
  • Na Zhu, Yoshikazu Miyanaga, Hiroshi Tsutsui, Masumi Watanabe
    IEICE Technical Report 電子情報通信学会 116 (81) 61 - 64 0913-5685 2016/06 [Not refereed][Not invited]
  • George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 電子情報通信学会 116 (81) 55 - 59 0913-5685 2016/06 [Not refereed][Not invited]
  • An Evaluation of Data Traffic Reduction for 3D Reconstruction Using a Wireless Network Camera System
    Hikaru Aoki, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of IEICE Hokkaido Section Student Council Internet Symposium 2016/02 [Not refereed][Not invited]
  • An Evaluation of Frame-based Parallel Processing for Iterative Shrinkage Smoothing Using Multi-core Processor
    Seijiro Imai, Dabwitso Kasauka, Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Okuhata, Yoshikazu Miyanaga
    Proceedings of IEICE Hokkaido Section Student Council Internet Symposium 2016/02 [Not refereed][Not invited]
  • Dabwitso Kasauka, Hiroshi Tsutsui, Seijiro Imai, Takashi Imagawa, Hiroyuki Okuhata, Yoshikazu Miyanaga
    2016 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) 1 - 5 2016 [Refereed][Not invited]
     
    Recently, edge preserving image smoothing techniques have been developed based on fast Fourier transformation (FFT) methods. In this paper, we present an alternative implementation for an existing image smoothing algorithm using a spatial iterative method, multigrid conjugate gradient (MGCG). In the case of FFT solvers, so-called wraparound error occurs in the image boundary due to the periodicity implied by the discrete Fourier transformation. Since the proposed method utilizes iterative methods in the spatial domain, wraparound error free image smoothing can be archived. Experimental results shows that the proposed method provides superior results compared to an FFT solver in terms of computational cost and smoothing quality.
  • Seijiro Imai, Dabwitso Kasauka, Hiroshi Tsutsui, Takashi Imagawa, Hiroyuki Okuhata, Yoshikazu Miyanaga
    2016 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS) 211 - 214 2016 [Refereed][Not invited]
     
    Iterative shrinkage smoothing algorithm can perform image smoothing with eliminating fine details and preserving principal edges in an image. However, real time processing is difficult due to large processing time when input image size is large. By utilizing downscaled image of an input image, the processing time can be dramatically reduced. In this case, however, the information of preserved principal edges is not accurate. Considering the applications utilizing such edge preserving smoothing algorithms, such as image tone mapping and detail enhancement, inaccurate principal edge information degrades the quality of resulted images. In this paper, we focus on tone mapping in the applications and propose processing time reduction method of tone mapping based on iterative shrinkage smoothing by utilizing parallel processing. Experimental results show that the proposed method improves the frame rates to 16 and 10 times for VGA and full HD resolutions, respectively, compared to single process implementation.
  • Sukeyuki Iwata, Masahito Umehara, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 115 (348) 73 - 76 2015/12 [Not refereed][Not invited]
  • Seijiro Imai, Dabwitso Kasauka, Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Okuhata, Yoshikazu Miyanaga
    IEICE Technical Report 115 (348) 57 - 60 2015/12 [Not refereed][Not invited]
  • Shingo Kokami, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 電子情報通信学会 115 (348) 95 - 98 0913-5685 2015/12 [Not refereed][Not invited]
  • Hikaru Aoki, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 115 (348) 53 - 56 2015/12 [Not refereed][Not invited]
  • Hiroki Uesaka, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 115 (348) 89 - 94 2015/12 [Not refereed][Not invited]
  • A Power Allocation Method in OFDMA System
    Wenheng Zhang, Alia Asheralieva, Gengfa Fang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido 2015/11 [Not refereed][Not invited]
  • An evaluation of high quality synchronization method in MIMO-OFDM using measured value
    Sukeyuki Iwata, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido 2015/11 [Not refereed][Not invited]
  • Shinya Moriyama, Kosuke Morinaga, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Masaki Miura, Tohru Gotoh, Junji Yamano
    IEICE Technical Report 115 (208) 31 - 36 2015/09 [Not refereed][Not invited]
  • Image Shrinking Based Computational Cost Reduction of Moving Area Extraction with Global Motion Estimation and Background Subtraction
    Shingo Kokami, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Society Conference 143  2015/09 [Not refereed][Not invited]
  • Computational Cost Reduction of Iterative Shrinkage Smoothing Based Image Enhancement
    Seijiro Imai, Dabwitso Kasauka, Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Okuhata, Yoshikazu Miyanaga
    IEICE Society Conference 144  2015/09 [Not refereed][Not invited]
  • An Evaluation of Motion Compensated Frame Interpolation from Multiple Resolution and Multiple Frame Rate Video Based on Global Motion
    Hiroki Uesaka, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Society Conference 145  2015/09 [Not refereed][Not invited]
  • An Evaluation towards Highly Efficient 3D Reconstruction Using Multiple Cameras
    Hikaru Aoki, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Society Conference 147  2015/09 [Not refereed][Not invited]
  • A Feasibility Study of a Flexible OFDM Transmitter Towards an Adaptive Control of Communication Quality
    Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 77 - 79 2015/09 [Refereed][Not invited]
  • Carrier and Sampling Frequency Offset Compensation in 8×8 MIMO-OFDM Systems and its Performance Evaluation Using Measured Data
    Shinya Moriyama, Kosuke Morinaga, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Masaki Miura, Tohru Gotoh, Junji Yamano
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 73 - 76 2015/09 [Refereed][Not invited]
  • 画像処理装置、画像処理方法及び画像処理用プログラム
    Hiroshi Tsutsui, Hiroki Uesaka, Shingo Kokami
    2015年8月21日 特願2015-163487 2015/08 [Not refereed][Not invited]
  • Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi
    PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014) 428 - + 1948-3287 2015 [Refereed][Not invited]
     
    Sub- and near-threshold circuits have been attracting growing interests because they are suitable for realizing extremely low power and low energy circuits. The estimation of the minimum operating voltage (V-DDmin), under which the circuit does not function correctly, is one of the most important issues in their design. In this paper, the distribution of V-DDmin is explored through simulations and measurements. Lognormal model-approximation and a quick V-DDmin estimation method are validated by the measurements of 124k FFs. Assuming that the V-DDmin of a circuit is limited by that of the FFs, V-DDmin distribution for any circuits can be efficiently estimated. The measurements of 192 DCT circuits show that the estimation matches with silicon data very well within 10mV error.
  • Dabwitso Kasauka, Hiroshi Tsutsui, Hiroyuki Okuhata, Takashi Imagawa, Yoshikazu Miyanaga
    2015 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) 779 - 783 2015 [Refereed][Not invited]
     
    In recent years, much research interest has developed in image smoothing techniques. With increasing application in various fields, there is a motivation to explore various modes of algorithm implementation of image smoothing. Recently, edge-aware image smoothing techniques have been developed based on fast Fourier transformation methods. In this paper, we present an alternative implementation for an existing image smoothing algorithm using spatial iterative methods. The motivation of this is to create a performance baseline using spatial iterative methods such as multigrid (MG), conjugate gradient (CG), and preconditioned conjugate gradient (PCG) methods, for the purpose that the algorithm can be easily adapted to parallel computing systems. We also determine the competitiveness compared with FFT implementation in terms of computational cost. From experimental results, multigrid preconditioned conjugate gradient (MGCG) method provides superior results both in smoothing quality and computational cost compared to all the spatial iterative methods considered. Furthermore, with relaxed tolerance, it demonstrates lower computational complexity compared with FFT implementation, with similar smoothing results but having minor quality compromise. Hence, MGCG provides a relatively competitive spatial domain alternative to frequency domain solver, FFT. In applications which do not require computation of an exact solution, spatial iterative methods can provide a reasonable computation alternative to FFT implementation as their convergence conditions can easily be altered by the user to fit a specific application, as well as possessing the ease for parallel computing adaptation.
  • Federico Ang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2015 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS) 1 - 4 2015 [Refereed][Not invited]
     
    Current state-of-the-art automatic, continuous speech recognition systems have enjoyed huge leaps in accuracy using speech features that assumes stationarity in the signals that are being processed. However, the said performance can often be attributed to the inclusion of lexical information. For the case of isolated word tasks, without the use of a priori models for the expected words, the static speech representation breaks down. For example, words that only differ in one unvoiced part are often misrecognized. Thus, time-varying speech representations has become an interest in the field. This paper is concerned with the use of simple time-varying features based on an autoregressive modeling of speech that provides high resolution features. In particular, how the said high resolution features fit into a finite-length Hidden Markov Model-based acoustic model that was originally used for static features. Its performance is compared with the best performing static features (Mel-Frequency Cepstral Coefficients) and while it is currently viewed as suboptimal, ample rooms for improvement are also emphasized.
  • Federico Ang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP) 302 - 306 1546-1874 2015 [Refereed][Not invited]
     
    Isolated word speech recognition for small vocabulary tasks has found great success with Mel-frequency cepstral coefficients as the speech feature of choice. Voice-controlled embedded systems, using word models as the basic units of speech, have found their way in a variety of commercial products. While the recognition rates for these products can be considered commercially acceptable under clean environments, channel noise and other external factors can still degrade recognition performance in practice. We propose the use of cepstral features derived from time-varying linear predictive coding, where the autoregressive model of the speech signal is represented by coefficients that are linear combinations of some simple basis functions. Variations in the usage of the features are investigated, such as skipping adjacent features, averaging and hybrid features with the goal of improving the performance of a 142 vocabulary, isolated words Japanese speech recognition task.
  • Takahiro Inatsuki, Masato Matsuura, Kosuke Morinaga, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP) 1062 - 1066 1546-1874 2015 [Refereed][Not invited]
     
    In this paper, we present an FPGA implementation of low-latency video transmission system. The proposed system is capable of lossless video transmission using line-based compression. Assuming transmission over wireless communication channel where the data throughput dynamically changes, our system supports lossless to near-lossless scalable compression. According to the FPGA implementation result, we confirmed that our system can archive 45% of data reduction in average and can be implemented using 14,777 slice LUTs and 4,343 slice registers.
  • An Approach of Doppler-Tolerant Channel Estimation Using RLS Algorithm for MIMO-OFDM Systems
    Masahito Umehara, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 197 - 202 2014/10 [Refereed][Not invited]
  • Masahito Umehara, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 一般社団法人電子情報通信学会 114 (126(SIS)) 135 - 140 0913-5685 2014/07 [Not refereed][Not invited]
     
    Frequency deviation by the Doppler shift in the multipath environment deteriorates the demodulation accuracy significantly. In this paper, we introduce the recursive least squares (RLS) algorithm which is one of the adaptive algorithms for MIMO detector of multiple-input multiple-output - orthogonal frequency division multiplexing (MIMO-OFDM) systems and propose a channel estimation method which has a Doppler resistance. In addition, we focus on the preamble structure of transmission frames to improve further demodulation accuracy. As a result, we report that the channel estimation accuracy is improved utilizing the extension high throughput - long training field (HT-LTF).
  • Effect of Receiver Diversity in IDMA Outdoor Transmission Experiment
    Shingo Yoshizawa, Yasuyuki Hatakawa, Satoshi Konishi, Yuki Hikiyama, Hiroki Iwaizumi, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE General Conference 441  2014/03 [Not refereed][Not invited]
  • Characteristic Evaluation of IDMA in Outdoor Transmission Experiment
    Yuki Hikiyama, Hiroki Iwaizumi, Shingo Yoshizawa, Yasuyuki Hatakawa, Satoshi Konishi, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE General Conference 440  2014/03 [Not refereed][Not invited]
  • Overview of Outdoor Transmission Experiment of IDMA
    Yasuyuki Hatakawa, Satoshi Konishi, Shingo Yoshizawa, Hiroki Iwaizumi, Yuki Hikiyama, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE General Conference 439  2014/03 [Not refereed][Not invited]
  • Dabwitso Kasauka, Hiroshi Tsutsui, Hiroyuki Okuhata, Yoshikazu Miyanaga
    2014 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) 1 - 4 2014 [Refereed][Not invited]
     
    In this paper, we present a computational cost analysis result of accelerated iterative shrinkage smoothing algorithm, which is one of promising image smoothing algorithms with sufficient smoothing quality results and reduced processing time. The main motivation of this cost analysis is to provide a base for efficient hardware implementation. We implemented it in a lower level programming language with OpenCV library as opposed to the MATLAB implementation. The resolution dependency of the processing time is also illustrated.
  • Hiroki Lwaiztani, Masahiro Sugnani, Baiko Sai, Hiroshi Tsutsui, Voshikazu Miyanaga
    2014 6TH INTERNATIONAL SYMPOSIUM ON COMMUNICATIONS, CONTROL AND SIGNAL PROCESSING (ISCCSP) 586 - 589 2014 [Refereed][Not invited]
     
    In this paper. we propose a new hardware design of 8 x 8 multiple-input multiple-output - orthogonal frequency division multiplexing (MIMO-OFDM) system which has floating-point data processors in its receiver. For the hardware design of MIMO-OFDM systems, it is efficient to use fixed-point data processing in terms of high speed processing time and low power consumption. However, tinder some of poor wireless communication environments, a floating-point data processing is required because of the accurate calculation for the MIMO decoding. In this report. high accuracy and real-time processing of MIMO decoding are realized by using an application specific instruction-set processor (ASIP). The performance of the proposed system is also evaluated and explored in this report.
  • Masahiro Sugitani, Hiroki Iwaizumi, Baiko Sai, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 一般社団法人電子情報通信学会 113 (343) 41 - 46 0913-5685 2013/12 [Not refereed][Not invited]
     
    An 8×8 MIMO-OFDM system is designed to achieve a large capacity and high-speed communication system. However, it is needed to reduce circuit scale and power consumption since the receiver needs huge calculation cost in interference cancellation. In this paper, we introduce Strassen's algorithm in a part of MIMO detection inverse matrix calculation process to reduce the calculation cost. Also, we designed an 9-step MIMO detector which reduces circuit scale by dividing all calculation into 9 steps in MMSE weight matrix calculator. We propose a low-power 8×8 MIMO-OFDM wireless communication system with performance evaluation results.
  • Hiroki Iwaizumi, Masahiro Sugitani, Baiko Sai, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 一般社団法人電子情報通信学会 113 (343) 35 - 40 0913-5685 2013/12 [Not refereed][Not invited]
     
    In this paper, we propose a hardware design of highly accurate 8×8 multiple-input multiple-output - or -thogonal frequency division multiplexing (MIMO-OFDM) system which has floating-point processors in its receiver. For hardware design of MIMO-OFDM systems, it is efficient to use fixed-point processing in terms of processing speed and power consumption. However, in poor environments, floating-point processing is necessary since highly accurate processing is required for MIMO decoding. In this research, we have realized high accuracy and realtime processing of MIMO decoding by employing application specific instruction-set processor (ASIP) and making algorithm more efficient.
  • Yuya Inoue, Hiroshi Tsutsui, Yoshikazu Miyanaga
    ISPACS 2013 - 2013 International Symposium on Intelligent Signal Processing and Communication Systems 363 - 368 2013/11 [Refereed][Not invited]
     
    This paper presents a study of peak-to-average power ratio (PAPR) reduction using coded partial transmit sequence (PTS) in 88 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems. MIMO-OFDM achieves large-capacity wireless communication, and has been adopted in such as IEEE802.11n/ac standard wireless LAN systems. PAPR indicates the ratio of peak power to average power. High PAPR causes waveform distortion due to nonlinear amplifier characteristics. PTS is one of PAPR reduction methods to prevent communication quality degradation. PTS performs phase rotation to OFDM modulated signals to reduce the peak power. We have to increase the number of possible phase patterns in order to obtain enough PAPR reduction. Coded PTS is used to reduce computational cost of PTS by using codebook. In the case of MIMO-OFDM systems, we have to use the same phase pattern of PTS for each stream due to difficulty of detection. In this paper, we have evaluated PAPR reduction by the proposed coded PTS in 8x8 MIMO-OFDM systems. The evaluation result shows that low error transmission can be achieved by using coded PTS and RS code, and PAPR reduction is about 1.7dB. In comparison with PTS, coded PTS can achieve 94% computational cost reduction. © 2013 IEEE.
  • Place-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy
    Takashi Imagawa, Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of the 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2013) 76 - 81 2013/10 [Refereed][Not invited]
  • An Evaluation of Channel Estimation Using RLS Algorithm in MIMO-OFDM Systems
    Masahito Umehara, Baiko Sai, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 145 - 150 2013/10 [Refereed][Not invited]
  • Kosuke Morinaga, Hiroshi Tsutsui, Yoshikazu Miyanaga
    13th International Symposium on Communications and Information Technologies: Communication and Information Technology for New Life Style Beyond the Cloud, ISCIT 2013 685 - 690 2013/09 [Refereed][Not invited]
     
    In recent years, digital high-definition television is widely used due to the start of digital terrestrial television broadcasting. In addition to such situation, ultra high definition television format such as 4K and 8K has been standardized. On the other hand, high-speed wireless transmission systems using MIMO-OFDM including IEEE 802.11n and 802.11ac wireless LAN standards have become popular. Using such high-speed transmission systems, it is expected that high-definition video sequences can be transmitted without any degradation of quality. Therefore, we are trying to develop such high-quality video transmission systems over a wireless environment by combining lossless video compression algorithms and MIMO-OFDM wireless transmission technology considering both hardware implementation and wireless transmission conditions. In this paper, we evaluate a configuration of lossless video transmission systems. Experimental result shows that video sequences can be transmitted over 22db carrier to noise ratio (CNR) wireless channels with 99.99% pixel restoration rate. © 2013 IEEE.
  • Yuki Hikiyama, Hiroshi Tsutsui, Yoshikazu Miyanaga
    13th International Symposium on Communications and Information Technologies: Communication and Information Technology for New Life Style Beyond the Cloud, ISCIT 2013 674 - 679 2013/09 [Refereed][Not invited]
     
    Recently, multiple-input multiple-output (MIMO) technologies are adopted to wireless communication systems for high-speed, large capacity and high reliability communications. However, there can be variations of communication quality and throughput performance, because MIMO technologies depend on propagation channel environments, where communication property widely changes. An optimal wireless communication systems design which adaptively changes transmission systems depending on channel propagation is effective to realize stable wireless communications therefore, it is important that a transceiver knows propagation environment accurately. In this paper, we propose a new discrimination method for MIMO propagation scenarios by using channel state information (CSI), where azimuth spread (AS) and K-Factor estimation are considered. In addition, we evaluate discrimination performance by simulation, and then we get a discrimination result of high accuracy. © 2013 IEEE.
  • Masumi Watanabe, Hiroshi Tsutsui, Yoshikazu Miyanaga
    13th International Symposium on Communications and Information Technologies: Communication and Information Technology for New Life Style Beyond the Cloud, ISCIT 2013 802 - 807 2013/09 [Refereed][Not invited]
     
    In this paper, we propose a robust speech recognition method for similar pronunciation phrases. Along with the popularization of information devices such as personal computers and smart-phones, many applications controlled by voice have spread in the society. In order to increase the speech accuracy under a real environment, it is extremely important to discriminate similar pronunciation phrases. In the proposed method, linear prediction theory (LPC) is used for spectral analysis while cepstrum mean subtraction (CMS) and dynamic range adjustment (DRA) is used for a noise reduction method. The speech accuracy was recorded 68.7 % in SNR 10 dB by using the proposed methods. In conclusion, LPC+CMS/DRA is the most effective method to discriminate similar pronunciation phrases. © 2013 IEEE.
  • Masato Matsuura, Hiroshi Tsutsui, Yoshikazu Miyanaga
    13th International Symposium on Communications and Information Technologies: Communication and Information Technology for New Life Style Beyond the Cloud, ISCIT 2013 797 - 801 2013/09 [Refereed][Not invited]
     
    Recently, video quality on TV programs and the Internet has become dramatically high. In this situation, demand for sharing high quality video sequences without wiring is increasing. Considering the bit rate of wireless channels, we should use lossy compression to transmit video sequences. However, this approach is not always ideal in terms of video quality. Therefore, our group is trying to develop a system of wireless transmission and lossless video compression. In this paper, we evaluated the system in computer simulation. As for the compression part, we confirmed that the combination of hierarchical average and copy prediction (HACP) algorithm and Huffman coding has good compression performance and suitable for hardware implementation. As for the transmission part, we adopted 8×8 MIMO-OFDM, which is employed in IEEE802.11ac, because this system can transmit data of about 1Gbps or more. Considering noise by transmission errors, we propose a packet construction method to reduce noise. In the evaluation, we explore conditions of wireless systems where noise does not appear and stable image is obtained by simulating. The experimental results show that stable transmission can be achieved in case of 18 dB CNR, 16QAM moduration, and 1/2 coding rate. © 2013 IEEE.
  • Takafumi Fujita, Junya Kawashima, Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Technical Report 電子情報通信学会 113 (112) 129 - 134 1342-6893 2013/07 [Not refereed][Not invited]
  • Tsuyoshi Okazaki, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of Workshop on Circuits and Systems [電子情報通信学会] 26 472 - 477 2013/07 [Refereed][Not invited]
  • Takafumi Fujita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of Workshop on Circuits and Systems [電子情報通信学会] 26 397 - 402 2013/07 [Refereed][Not invited]
  • Kazunori Kimura, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of Workshop on Circuits and Systems [電子情報通信学会] 26 374 - 379 2013/07 [Refereed][Not invited]
  • Hiroshi Tsutsui
    IEICE Technical Report 一般社団法人電子情報通信学会 113 (78) 47 - 52 0913-5685 2013/06 [Not refereed][Not invited]
     
    In recent years, the demand for image processing has been growing steadily with the wide use of digital imaging devices such as smart phones and camcorders. In the case of image processing for video data, since the amount of data per unit time is relatively large, it is implemented in hardware instead of software especially when real-time processing is required. This paper provides an overview of image processing IP core design using a development case of Retinex-based adaptive image enhancement IP core.
  • Histogram Propagation Based Statistical Timing Analysis Using Dependent Node Selection
    Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 321 - 324 2013/06 [Refereed][Not invited]
  • Architecture for Sealed Wafer-scale Mask ROM for Long-term Digital Data Preservation
    Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
    The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 274 - 277 2013/06 [Refereed][Not invited]
  • Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 95 - 100 2013/05 [Refereed][Not invited]
     
    Power grid analysis for modern LSI is computationally challenging in terms of both runtime and memory usage. In this paper, we implement Krylov subspace based linear circuit solvers on a graphics processing unit (GPU) to realize fast power grid analysis. Efficiencies of memory space and access performance are pursued by improving a data structure that stores elements of large sparse matrices. Experimental results on benchmark circuits show that the proposed data structures are more suitable than widely used compressed sparse row (CSR) format and our GPU implementations can achieve up to 17x speedup over CPU implementations. © 2013 ACM.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON ELECTRONICS E96C (4) 454 - 462 0916-8524 2013/04 [Refereed][Not invited]
     
    This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.
  • Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON ELECTRONICS E96C (4) 473 - 481 0916-8524 2013/04 [Refereed][Not invited]
     
    We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than x10 is achieved compared to conventional methods including GPU implementation.
  • Takafumi Fujita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE General Conference 2013 78  1349-1369 2013/03 [Not refereed][Not invited]
  • Evaluation of Dependent Node Selection of Histogram Propagation Based Statistical Timing Analysis
    Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the 2013 IEICE general conference, Fundamentals on Electronics, Communications and Computer Sciences 62  2013/03 [Not refereed][Not invited]
  • Tsuyoshi Okazaki, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE General Conference 2013 61  1349-1369 2013/03 [Not refereed][Not invited]
  • Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) 597 - 602 1948-3295 2013/03 [Refereed][Not invited]
     
    This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) 538 - 545 1948-3287 2013 [Refereed][Not invited]
     
    In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    DESIGN, AUTOMATION & TEST IN EUROPE 701 - 706 1530-1591 2013 [Refereed][Not invited]
     
    This paper proposes a method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of an application circuit to a coarse-grained reconfigurable architecture (CGRA). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the features and parameters of each node in the DFG which characterize impact of the SEU in the node to the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.
  • Zoltan Endre Rakossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
    DESIGN, AUTOMATION & TEST IN EUROPE 535 - 540 1530-1591 2013 [Refereed][Not invited]
     
    Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units (FUs), that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data-path switching realized by the proposed hot-swapping algorithm and structures, by use of which functional units are tested and replaced by spares, at lower overheads than traditional modular redundancy. For a case study architecture, hot-swapping support could be added with only 29% area overhead. In this paper we focus on experimental evaluation of the hot-swapping system from a fabricated chip in 65nm CMOS process. Autonomous testing of the hot-swapping system is enhanced with back-bias circuitry to attain an early fault detection and restoration system. Experimental measurements prove that the proposed concept works well, predicting fault occurrence with a configurable prediction interval, while power measurements reveal that with only 20% power overhead the proposed system can attain reliability levels similar to triple modular redundancy. Additionally, measurements reveal that manufacturing randomness across the die can significantly influence identical sub-circuit reliability located in different parts in the die, although identical layout has been employed.
  • Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 169 - 174 2013/01 [Refereed][Not invited]
     
    This paper presents the realization of frequency-domain circuit analysis based on random walk framework for the first time. In conventional random walk based circuit analyses, the sample movement at a node is randomly chosen to follow the edge probabilities. The probabilities are determined by edge-admittances connecting to the node, which is impossible to apply for the frequency-domain analysis because the probabilities are imaginary numbers. By applying the idea of importance sampling, the intractable imaginary probabilities are converted into real numbers while maintaining the estimation correctness. Runtime acceleration through incremental analysis is also proposed. © 2013 IEEE.
  • Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A (12) 2272 - 2283 1745-1337 2012/12 [Refereed][Not invited]
     
    Random telegraph noise (RTN) is a phenomenon that is considered to limit the reliability and performance of circuits using advanced devices. The time constants of carrier capture and emission and the associated change in the threshold voltage are important parameters commonly included in various models, but their extraction from time-domain observations has been a difficult task. In this study, we propose a statistical method for simultaneously estimating interrelated parameters: the time constants and magnitude of the threshold voltage shift. Our method is based on a graphical network representation, and the parameters are estimated using the Markov chain Monte Carlo method. Experimental application of the proposed method to synthetic and measured time-domain RTN signals was successful. The proposed method can handle interrelated parameters of multiple traps and thereby contributes to the construction of more accurate RTN models.
  • Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A (12) 2242 - 2250 0916-8508 2012/12 [Refereed][Not invited]
     
    We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (V-DDmin) of a circuit is dominated by flip-flops (FFs), and V-DDmin of an FF can be improved by upsizing a few key transistors, (2) V-DDmin of an FF is stochastically modeled by a log-normal distribution, (3) V-DDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving V-DDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
  • Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Technical Report 一般社団法人電子情報通信学会 112 (320) 117 - 122 0913-5685 2012/11 [Not refereed][Not invited]
     
    With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65 nm CMOS technology. The proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.
  • Hirofumi Shimizu, Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of IPSJ DA Symposium 2012 (5) 49 - 54 1344-0640 2012/08 [Refereed][Not invited]
  • Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of Workshop on Circuits and Systems [電子情報通信学会] 25 432 - 437 2012/07 [Refereed][Not invited]
  • A Study for Improving Minimum Operation Voltage and Its Estimation Accuracy
    Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
    in Proc. of Workshop on Circuits and Systems 313 - 318 2012/07 [Refereed][Not invited]
  • Tatsuo Maeno, Hiroshi Tsutsui, Takao Onoye
    IEICE Technical Report 112 (78) 77 - 82 0913-5685 2012/06 [Not refereed][Not invited]
  • GPU Acceleration of Cycle-based Soft-Error Simulation for Reconfigurable Array Architectures
    Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2012) 88 - 93 2012/03 [Refereed][Not invited]
  • Hardware Architecture for Accelerating Monte Carlo based SSTA using Generalized STA Processing Element
    Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2012) 205 - 210 2012/03 [Refereed][Not invited]
  • Acceleration Scheme for Monte Carlo based SSTA using Generalized STA Processing Element
    Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of ACM/IEEE International Workshop on Timing Issues (TAU) 2012/01 [Refereed][Not invited]
  • Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 11 (4) 1 - 25 1539-9087 2012 [Refereed][Not invited]
     
    JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft Corporation. It supports high compression performance twice as high as the de facto image coding system, namely, JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this article, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. In addition, each module of our architecture, which can be regarded as a pipeline stage, can be parallelized. As a result, our architecture can achieve 12.8 pixel/cycle at its maximum. To demonstrate our architecture, we designed three versions of our architecture with different degrees of parallelism of one, two, and four. Our four-way parallel architecture achieves 579 Mpixel/sec at 181MHz clock frequency for grayscale images.
  • Hiroshi Tsutsui, Satoshi Yoshikawa, Hiroyuki Okuhata, Takao Onoye
    2012 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA ASC) 2012 [Refereed][Not invited]
     
    In this paper, we propose a novel halo reduction method for variational based Retinex image enhancement. In variational based Retinex image enhancement, a cost function is designed based on the illumination characteristics. The enhanced image is obtained by extracting the illumination component, which gives minimum cost, from the given input image. Although this approach gives good enhancement quality with less computational cost, a problem that dark regions near edges remain dark after image enhancement, known as halo artifact, still exists. In order to suppress such artifacts effectively, the proposed method adaptively adjusts the parameter of the cost function, which influences the trade-off relation between reducing halo artifacts and preserving image contrast. The proposed method is applicable to an existing realtime Retinex image enhancement hardware implementation.
  • Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi
    2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) 306 - 311 1948-3287 2012 [Refereed][Not invited]
     
    Performance variability of miniaturized devices has become a major obstacle for designing electronic systems. Temporal degradation of threshold voltages and its variation are going to be an additional concerns to ensure their reliability. In this paper, based on measurement results on large number of devices, we present statistical properties of device degradation and recovery. The measurement data is obtained by using a device-array circuit suitable for efficiently collect statistical data on degradations and recoveries of very small channel-area devices. Stair-like change of threshold voltages found in our measurement suggests that charge trapping and emission may play a key role in the device degradation process.
  • Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Technical Report 111 (324) 67 - 71 0913-5685 2011/11 [Not refereed][Not invited]
  • Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Technical Report 111 (324) 85 - 90 0913-5685 2011/11 [Not refereed][Not invited]
  • Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Technical Report 111 (324) 73 - 78 0913-5685 2011/11 [Not refereed][Not invited]
  • Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Society Conference 2011 93  1349-1369 2011/09 [Not refereed][Not invited]
  • Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of IEICE Society Conference 一般社団法人電子情報通信学会 120 120 - 120 2011/09 [Not refereed][Not invited]
  • Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE Society Conference 2011 84  1349-1369 2011/09 [Not refereed][Not invited]
  • Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi
    European Solid-State Device Research Conference 143 - 146 1930-8876 2011/09 [Refereed][Not invited]
     
    A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed. © 2011 IEEE.
  • Kentaro Katayama, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of IPSJ DA Symposium 2011 (5) 93 - 98 1344-0640 2011/08 [Refereed][Not invited]
  • Takashi Imagawa, Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    in Proc. of IPSJ DA Symposium 2011 (5) 111 - 116 1344-0640 2011/08 [Refereed][Not invited]
  • Tatsuo Maeno, Hiroshi Tsutsui, Takao Onoye
    IEICE Technical Report 111 (78) 99 - 104 0913-5685 2011/06 [Not refereed][Not invited]
  • Satoshi Yoshikawa, Hiroshi Tsutsui, Hiroyuki Okuhata, Takao Onoye
    IEICE Technical Report 一般社団法人電子情報通信学会 111 (78) 93 - 98 0913-5685 2011/06 [Not refereed][Not invited]
     
    In Retinex-based image enhancement schemes, an image is enhanced by removing an estimated illumination included in the input image. As for illumination estimation method, in this paper, we focus on the variational model which utilizes spatially smooth property of the illumination and formulates the illumination estimation problem as a quadratic programming optimization problem. In this method, the ordinary halo effect, which over-enhances bright regions adjacent with dark regions, does not occur. However, dark regions adjacent with bright regions remain as it was since they cannot be sufficiently enhanced. This effect is called a reverse halo effect in this paper. To suppress this effect, we propose a method to control the parameter in the cost function based on each pixel value and the amount of edge component. The experimental results show that the proposed method can suppress the reverse halo effect maintaining other features of the Retinex-based image enhancement.
  • A stress-parallelized device array for efficient bias-temperature stability measurement
    Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi
    Proc. of IEEE International Workshop on Design for Manufacturability and Yield 2011 (DFM&Y) 19 - 22 2011/06 [Refereed][Not invited]
  • Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 211 - 216 2011/05 [Refereed][Not invited]
     
    This paper proposes an importance sampling (IS) technique based on quasi-zero-variance estimation for accelerating convergence of random-walk-based power grid analysis. In our approach, the alternative probability for IS is incrementally updated after every Mr samples of random walk so that more recent and thus more accurate node voltages are utilized to asymptotically achieve ideal zero-variance estimation. We also propose a method to determine efficient Mr for the r-th probability update although smaller M r results more aggressive update of alternative probability, the alternative probability becomes inaccurate if Mr is too small. The estimation error of the proposed method decreases O((M/r)-r/2), which breaks O(M-1/2), the slow convergence-rate barrier of normal Monte Carlo analysis. Our trial implementation achieved 790x speedup compared with a conventional random-walk-based circuit analysis for analyzing IBM power grid benchmark circuits at 1mV accuracy. Copyright © 2011 by ASME.
  • Hardware Implementation of Real-time Motion Adaptive Deinterlacing based on Inpainting
    Tatsuo Maeno, Hiroshi Tsutsui, Takao Onoye
    Proceedings of International Conference on Embedded Systems and Intelligent Technology (ICESIT) 2011/02 [Refereed][Not invited]
  • Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
    2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) 57 - 62 2011 [Refereed][Not invited]
     
    The paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (V-DDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) V-DDmin of a FF is stochastically modeled by a log-normal distribution, 3) V-DDmin of a large circuit can be estimated using the above model without extensive Monte-Carlo simulations, and 4) improving V-DDmin may substantially contribute to reduce energy consumption.
  • Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
    2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) 57 - 62 2011 [Refereed][Not invited]
     
    The paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (V-DDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) V-DDmin of a FF is stochastically modeled by a log-normal distribution, 3) V-DDmin of a large circuit can be estimated using the above model without extensive Monte-Carlo simulations, and 4) improving V-DDmin may substantially contribute to reduce energy consumption.
  • Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) 785 - 790 1948-3287 2011 [Refereed][Not invited]
     
    We propose an efficient implementation of Monte Carlo based statistical static timing analysis (MC-SSTA) on FPGAs. MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference because of its ability to handle any timing distributions and correlations. Extremely long CPU time has been required for the MC-SSTA, which prevented it from adopting as a mainstream timing analyzer. Motivated by its inherent parallelism, we propose a hardware acceleration of MC-SSTA. In our approach, timing graph of a target netlist will be translated into an RTL description that can be mapped into an FPGA as a dedicated STA engine. Each delay arc is realized as the random delay generator of specified parameters with a register, which explores full pipelining operation for the logic gates in a path. Linear feedback shift registers and normal distribution generators based on the central limit theorem are used as the random delay generator to suppress hardware resources. With our implementation, both path-and gate-level parallelisms are realized, achieving 87 times acceleration compared to a software implementation in the case of analyzing a 6 bit multiplier. The analysis accuracy comparable to the Mersenne Twister and the Box Muller methods, which are the well-known high quality normal distribution random number generator, has been also experimentally verified.
  • Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) 703 - 708 1933-7760 2010/11 [Refereed][Not invited]
     
    In this paper, a significant acceleration of estimating low-failure rate in a high-dimensional SRAM yield analysis is achieved using sequential importance sampling. The proposed method systematically, autonomously, and adaptively explores failure region of interest, whereas all previous works needed to resort to brute-force search. Elimination of brute-force search and adaptive trial distribution significantly improves the efficiency of failure-rate estimation of hitherto unsolved high-dimensional cases wherein a lot of variation sources including threshold voltages, channel-length, carrier mobility, etc. are simultaneously considered. The proposed method is applicable to wide range of Monte Carlo simulation analyses dealing with high-dimensional problem of rare events. In SRAM yield estimation example, we achieved 10(6) times acceleration compared to a standard Monte Carlo simulation for a failure probability of 3 x 10(-9) in a six-dimensional problem. The example of 24-dimensional analysis on which other methods are ineffective is also presented.
  • An Approach to Motion-Compensated Frame Interpolation based on Feature Tracking
    Hideyuki Nakamura, Hiroshi Tsutsui, Takao Onoye
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 2010/09 [Refereed][Not invited]
  • Hiroshi Tsutsui, Hideyuki Nakamura, Ryoji Hashimoto, Hiroyuki Okuhata, Takao Onoye
    Proc. of World Automation Congress (WAC), International Forum on Multimedia and Image Processing (IFMIP) 2010/09 [Refereed][Not invited]
  • Satoshi Yoshikawa, Hiroshi Tsutsui, Takao Onoye
    IEICE Technical Report 110 (74) 93 - 98 0913-5685 2010/06 [Not refereed][Not invited]
  • Tatsuo Maeno, Hiroshi Tsutsui, Takao Onoye
    IEICE Technical Report 110 (74) 87 - 92 0913-5685 2010/06 [Not refereed][Not invited]
  • Media Streaming System with Dynamic Rate Control for High Speed Mobile Networks
    Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
    IPSJ Journal 50 (10) 2532 - 2542 2009/10 [Refereed][Not invited]
  • Hideyuki Nakamura, Hiroshi Tsutsui, Ryoji Hashimoto, Takao Onoye
    IEICE Society Conference 一般社団法人電子情報通信学会 2009 204 - 204 1349-1369 2009/09 [Not refereed][Not invited]
  • Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A (8) 1970 - 1977 0916-8508 2009/08 [Refereed][Not invited]
     
    The encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of the entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process the entropy encoding/decoding. This module, however, requests many small-size memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory organization framework for the entropy encoding/decoding module is proposed, in which not only existing memory organizations but also our proposed novel memory organization methods are attempted to expand the design space to be explored. As a result, the efficient memory organization for a target process technology can be explored.
  • Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Yusuke Mizuno, Gen Sasaki, Yukihiro Nakamura
    Journal of the Institute of Image Electronics Engineers of Japan 38 (3) 296 - 304 1348-0316 2009/05 [Refereed][Not invited]
     
    A system architecture of JPEG2000 codec LSI is developed, which is dedicated to high resolution digital images. When single-tile processing technique is employed in order to maintain image quality, the requirement for on-chip memory amount and I/O bandwidth becomes serious issue. A line-based DWT is devised for our system architecture, in which image data is processed by rectangle pieces. In addition, we introduce a scheme to calculate required system resources with varying image sizes, DWT levels, and use of intermediate data buffer so as to investigate an efficient system architecture. Based on the proposed system architecture, a JPEG2000 codec LSI, supporting 8,192 X 8,192 images by single-tile processing, is implemented by using 2.1 M gates, which dissipates 137.1 mW from 1.8 V (core) power supply at 27 MHz operation. © 2009, The Institute of Image Electronics Engineers of Japan. All rights reserved.
  • Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
    IEEE Wireless Communications and Networking Conference, WCNC 1525-3511 2009/04 [Refereed][Not invited]
     
    Emerging high-speed mobile networks enable us to receive media streaming data by mobile terminals on demand. However, media streaming with fixed bitrate causes some problems such as annoying artificial noise, interruption, and so forth, since link quality fluctuates dramatically in such mobile networks. Motivated by this, in this paper, we propose a novel media streaming system with dynamic rate control scheme to achieve continuous streaming on such unstable networks. The proposed rate control scheme uses the delay of the transcoding process to estimate network bandwidth, and adjusts the bitrate of media streams dynamically. To demonstrate our system and scheme, the proposed streaming system is evaluated under some typical models of bandwidth change in high-speed mobile networks. The results show that stable and high-quality streaming without interruption can be achieved by the proposed scheme. Moreover, we successfully demonstrate that our system performs continuous streaming on real mobile networks even in the severe network condition such as on a moving train. © 2009 IEEE.
  • Ryoji Hashimoto, Hiroshi Tsutsui, Takao Onoye, Tomohiro Ikai
    IEICE Technical Report 一般社団法人 映像情報メディア学会 108 (425) 31 - 36 2009/02 [Not refereed][Not invited]
     
    Distributed Video Coding (DVC), which is a new image compression paradigm, attracts a lot of attention from video researchers. While computational cost of DVC encoding is lower than that of MPEG-2, low coding efficiency has been an issue for practical DVC applications. In this paper, a likelihood estimation method for transform domain DVC is proposed, which uses Cauchy distribution as a virtual channel model. In the decoder, virtual channel is estimated by utilizing error between forward and backward predicted images for each frequency component. Likelihood is obtained from estimated virtual channel. Simulation results show that the proposed method can estimate the error rate with 1.6% error on average.
  • Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    2009 IEEE/ACM/IFIP 7TH WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA 9 - + 2009 [Refereed][Not invited]
     
    JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft. It supports high compression performance twice as high as the de facto image coding system, namely JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this paper, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. The proposed fully-pipelined architecture achieves 100 M pixel/sec at 125 MHz which could not be achieved by previous works.
  • Dynamic Rate Control for Media Streaming in High-speed Mobile Network
    Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
    in Proc. of Multimedia, Distributed, Cooperative and Mobile Symposium 2008 1167 - 1176 2008/07 [Refereed][Not invited]
  • Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    IEICE Technical Report 108 (85) 39 - 44 0913-5685 2008/06 [Not refereed][Not invited]
  • Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 1592 - + 2008 [Refereed][Not invited]
     
    In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image data into frequency domain in HD Photo, an emerging image coding system developed by Microsoft. In order to support various memory bus bandwidths used in system-on-a-chip (SoC) design, an implementation for each bandwidth can be derived based on our architecture. In addition, in order to reduce the local memory size and the traffic between the main and local memories, we propose a novel data transfer and storing scheme for PCT. The experimental results show that hardware modules corresponding to the given bus bandwidths can be reasonably derived from the proposed architecture.
  • Hiroshi Tsutsui
    IEICE Society Conference 2007 SS.8 - SS.9 1349-1369 2007/09 [Not refereed][Not invited]
  • Hiroshi Tsutsui, Norimasa Fujita, Takao Onoye, Yukihiro Nakamura
    IEICE Technical Report 一般社団法人電子情報通信学会 107 (93) 13 - 18 0913-5685 2007/06 [Not refereed][Not invited]
     
    In this paper, we propose a novel multi-symbol arithmetic decoder for JPEG2000, which is the most cost-intensive part in JPEG2000 decoding. The experimental result shows that by using the proposed arithmetic decoders which decode two and three symbols per cycle, the time required by arithmetic decoding with a single-symbol decoder can be reduced to 83% and 78% respectively.
  • Ryusuke Miyamoto, Jaehoon Yu, Hiroshi Tsutsui, Yukihiro Nakamura
    Journal of the Institute of Image Electronics Engineers of Japan 36 (3) 210 - 218 1348-0316 2007/05 [Refereed][Not invited]
     
    Stereo matching, the corresponding problem of stereo vision, requires much computational cost, especially highly accurate matching algorithm needs huge computational cost. Therefore realtime systems for stereo matching based on specific processors are developed. However, there is no system which enables both highly accurate matching and real time processing. In this paper, we propose a novel processor architecture based on variable window approach, in order to develop a specific processor which achieves highly accurate matching required for realtime systems using stereo vision. A processor based on the proposed architecture implemented on Xilinx Virtex-4 FPGA achieves real-time stereo matching at 70 MHz when the resolution and the frame rate of input images are QVGA and 30 fps, respectively. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.
  • Ryusuke Miyamoto, Jumpei Ashida, Hiroshi Tsutsui, Yukihiro Nakamura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E90A (3) 606 - 617 1745-1337 2007/03 [Refereed][Not invited]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian for a state space model and distance transformed images for likelihood computation. The 6-stick skeleton model used in the proposed approach is very distinctive in representing a pedestrian simply but effectively. By the experiment using the real sequences provided by PETS, it is shown that the target pedestrian is tracked adequately by the proposed approach with a simple silhouette extraction method which consists of only background subtraction, even if the tracking target moves so complicatedly and is often so cluttered by other obstacles that the pedestrian can not be tracked by the conventional methods. Moreover, it is demonstrated that the proposed scheme can track the multiple targets in the complex case that their trajectories intersect.
  • Hiromitsu Sumino, Yoshitaka Uchida, Norihiro Ishikawa, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    2007 4TH IEEE CONSUMER COMMUNICATIONS AND NETWORKING CONFERENCE, VOLS 1-3 793 - + 2331-9852 2007 [Refereed][Not invited]
     
    Design and implementation of home appliance control applications on a peer-to-peer network are presented in this paper. Home networks today exist in an environment where a mixture of various communication networks and different type of home appliances coexist, move, and communicate with one another over such heterogeneous networks. Peer-to-peer is one of the suitable technologies for such ubiquitous networking since it supports discovery mechanisms, simple one-to-one communication, free and extensible distribution of resources, and distributed search to handle the enormous number of resources. In our system, protocols defined by Peer-to-peer Universal Computing Consortium (PUCC) are used to control various kinds of devices over a Peer-to-peer network. This prototype system successfully controls home appliances, such as air conditioner, light, refrigerator, TV and video recorder, from mobile phones.
  • Hiroshi Tsutsui, Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida, Norihiro Ishikawa
    2007 4TH IEEE CONSUMER COMMUNICATIONS AND NETWORKING CONFERENCE, VOLS 1-3 778 - + 2331-9852 2007 [Refereed][Not invited]
     
    In this paper, a prototype implementation of streaming system that allows listening to and viewing multimedia contents using a mobile terminal, as part of our efforts toward realizing services linked with home networks and mobile networks is presented. In our system, appliances are detected and connected to a mobile terminal by use of peer-to-peer (P2P) network based on the PUCC protocols, and they are controlled by use of P2P messages and IEEE1394 AV/C. Streaming is managed by a gateway on the P2P network, where multimedia contents are converted to another format suitable to be sent to mobile terminals. This prototype system successfully achieves video data streaming over two different networks by using P2P network which conceals the differences among the networks.
  • Ryusuke Miyamoto, Hiroki Sugano, Hiroaki Saito, Hiroshi Tsutsui, Hiroyuki Ochi, Ken'ichi Hatanaka, Yukihiro Nakamura
    IEICE Society Conference 2006 178  1349-1369 2006/09 [Not refereed][Not invited]
  • A Retargetable Compiler for Cell-Array Based Self-Reconfigurable Architecture
    Masayuki Hiromoto, Sinichi Koyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    in Proc. of IPSJ DA Symposium 181 - 186 2006/07 [Refereed][Not invited]
  • A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Significant Extra Bits
    Fumihiko Hyuga, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Yukihiro Nakamura
    Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2006) 3 97 - 100 2006/07 [Refereed][Not invited]
  • Fumihiko Hyuga, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Yukihiro Nakamura
    IEICE Technical Report 一般社団法人電子情報通信学会 106 (96) 31 - 36 0913-5685 2006/06 [Not refereed][Not invited]
     
    In this paper, a novel JPEG coding scheme for high fidelity images is proposed. When high fidelity images are compressed with JPEG, the information which cannot be represented by JPEG-compliant 8-bit data must be truncated. This truncation causes the quality degradation, In order to suppress this quality degradation, in the proposed scheme, halftoning is used to represent pixels of a high fidelity image with JPEG-compliant 8-bit data. The effect of halftoning depends on the characteristics of image. So halftoning and rounding is applied for each of 8×8 size block to truncate the extra information, then the method which is applied for each block is decided by the quality criteria. Moreover, optimization of halftoning parameters using simulated annealing is demonstrated.
  • Ryusuke Miyamoto, Jumpei Ashida, Hiroshi Tsutsui, Yukihiro Nakamura
    IEICE Technical Report 一般社団法人電子情報通信学会 106 (96) 25 - 30 0913-5685 2006/06 [Not refereed][Not invited]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which uses a skeleton model of a pedestrian and distance transformed images for likelihood estimation. The six-stick skeleton model used in the proposed approach is very distinctive in representing a pedestrian simply but effectively, with which the efficient state space for the pedestrian tracking can be derived. Experimental results by using PETS sample sequences demonstrate that the proposed approach achieves high-accurate pedestrian tracking without any of prior learning.
  • Masayuki Hiromoto, Sinichi Koyama, Kentaro Nakahara, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    IEICE Technical Report 106 (49) 7 - 12 2006/05 [Not refereed][Not invited]
  • Ryusuke Miyamoto, Yuuki Hara, Hiroshi Tsutsui, Yukihiro Nakamura
    in Proc. of Workshop on Circuits and Systems in Karuizawa [電子情報通信学会] 19 189 - 192 2006/04 [Refereed][Not invited]
  • 可変ウィンドウステレオマッチングプロセッサのアーキテクチャ
    Ryusuke Miyamoto, Jaehoon Yu, Hiroshi Tsutsui, Yukihiro Nakamura
    in Proc. of Workshop on Circuits and Systems in Karuizawa 165 - 170 2006/04 [Refereed][Not invited]
  • Hiroshi Tsutsui, Takahiko Masuzaki, Yoshiteru Hayashi, Yoshitaka Taki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    INTELLIGENT AUTOMATION AND SOFT COMPUTING 12 (3) 331 - 343 1079-8587 2006 [Refereed][Not invited]
     
    For the exploration of system architecture dedicated to JPEG2000 coding, decoding and codec, a novel design framework is constructed. In order to utilize the scalability of JPEG2000 algorithm aggressively in system implementation, three types of modules are prepared for JPEG2000 coding/decoding/codec processes, i.e. software, software accelerated with user-defined instructions, and dedicated hardware. Specifically, dedicated hardware modules for forward and inverse discrete wavelet transformation (shortly DWT), entropy coder, entropy decoder, and entropy codec as well as software acceleration for the DWT process arc devised to be used in the framework. Furthermore, a JPEG2000 encoder LSI, which consists of a configurable processor Xtensa, the DWT module, and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
  • Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS 2881 - 2884 0271-4302 2006 [Refereed][Not invited]
     
    An encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process entropy encoding/decoding. This module, however, requests many smallsize memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory architecture of the entropy encoding/decoding module is proposed, in which three approaches are attempted by utilizing one-bank SRAMs and internal registers. As a result, the efficient memory organization for a target process technology can be explored.
  • Ryusuke Miyamoto, Hiroki Sugano, Hiroaki Saito, Hiroshi Tsutsui, Hiroyuki Ochi, Ken'ichi Hatanaka, Yukihiro Nakamura
    ADVANCES IN IMAGE AND VIDEO TECHNOLOGY, PROCEEDINGS 4319 483 - + 0302-9743 2006 [Refereed][Not invited]
     
    Nowadays, pedestrian recognition in far-infrared images toward realizing a night vision system becomes a hot topic. However, sufficient performance could not be achieved by conventional schemes for pedestrian recognition in far-infrared images. Since the properties of far-infrared images are different from visible images, it is not known what kind of scheme is suitable for pedestrian recognition in far-infrared images. In this paper, a novel pedestrian recognition scheme combining boosting-based detection and skeleton-based stochastic tracking suitable for recognition in far-infrared images is proposed. Experimental results by using far-infrared sequences show the proposed scheme achieves highly accurate pedestrian recognition by combining accurate detection with few false positives and accurate tracking.
  • Ryusuke Miyamoto, Jumpei Ashida, Hiroshi Tsutsui, Yukihiro Nakamura
    WMSCI 2006: 10TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL V, PROCEEDINGS V 206 - + 2006 [Refereed][Not invited]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian as a state space model and uses distance transformed images for likelihood estimation. The skeleton model used in the Proposed approach is very distinctive in representing a pedestrian simply but effectively, with which the efficient state space for the pedestrian tracking can be derived. Experimental results by using PETS sample sequences shows that the proposed approach achieves highly accurate pedestrian tracking on far-view sequences.
  • Jumpei Ashida, Ryusuke Miyamoto, Hiroshi Tsutsui, Takao Onoye, Yukihiro Nakamura
    2006 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, ICIP 2006, PROCEEDINGS 2825 - + 1522-4880 2006 [Refereed][Not invited]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian as a state space model and uses distance transformed images for likelihood estimation. The six-stick skeleton model used in the proposed approach is very distinctive in representing a pedestrian simply but effectively, with which the efficient state space for the pedestrian tracking can be derived. Experimental results by using PETS sample sequences demonstrate that the proposed approach achieves highly accurate pedestrian tracking without any of prior learning.
  • Ryusuke Miyamoto, Hiroshi Tsutsui, Hiroaki Sugita, Takahiko Masuzaki, Hiroyuki Ochi, Takao Onoye, Yukihiro Nakamura
    IEICE Society Conference 2005 164  1349-1369 2005/09 [Not refereed][Not invited]
  • Hiroshi Tsutsui, Hiroki Sugano, Takahiko Masuzaki, Hiroyuki Ochi, Takao Onoye, Yukihiro Nakamura
    IEICE Society Conference 2005 22  1349-1369 2005/09 [Not refereed][Not invited]
  • JPEG2000 符復号器のためのスケーラブルデザインフレームワーク
    Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Yukihiro Nakamura
    VDEC LSI デザイナーフォーラム 2005/08 [Not refereed][Not invited]
  • R Miyamoto, H Sugita, Y Hayashi, H Tsutsui, T Masuzaki, T Onoye, Y Nakamura
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2096 - 2099 0271-4302 2005 [Refereed][Not invited]
     
    A novel high quality Motion JPEG2000 coding scheme is proposed, which is based on the human visual system being insensitive to high frequency component of image. This method enhances subjective video quality by controlling the amount of data allocated to each code-block according to amount of its motion. The proposed method enables video coding without degrading subjective quality of existing method at lower bitrate.
  • Video quality enhancement for Motion JPEG2000 encoding based on the human visual system
    Ryusuke Miyamoto, Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Yukihiro Nakamura
    Proc. of 2004 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2004) 1161 - 1164 2004/12 [Refereed][Not invited]
  • 視覚特性を用いた Motion JPEG2000 レート制御手法
    Hiroshi Tsutsui, Yoshiteru Hayashi, Ryusuke Miyamoto, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    第6回 YRP移動体通信産学官交流シンポジウム 152 - 153 2004/07 [Not refereed][Not invited]
  • J Ashida, R Miyamoto, H Tsutsui, T Onoye, Y Nakamura
    Proceedings of the Fourth IASTED International Conference on Visualization, Imaging, and Image Processing 6 - 11 2004 [Refereed][Not invited]
     
    In recent years, detection of moving objects from image sequence is applied to various areas. One of the techniques for this detection is using estimation of the focus of expansion (FOE). Conventional approaches, however, bring some errors to detected motion vectors required for the estimation of the FOE. In this paper, an accurate and scalable approach for estimation of the FOE is proposed. The proposed approach reduces errors included in motion vectors so as to enable accurate estimation of the FOE. To achieve practical processing time of the FOE estimation, a hardware architecture for the proposed approach is also discussed.
  • T Onoye, H Tsutsui, G Fujita, Y Nakamura, Shirakawa, I
    Image Processing, Biomedicine, Multimedia, Financial Engineering and Manufacturing, Vol 18 18 243 - 250 2004 [Refereed][Not invited]
     
    Embedded system architecture, which call be used for scalable and object-based video coding, is discussed in this paper. As for scalable video coding, namely JPEG2000, design framework for system architecture is Constructed with the main theme focused oil the ability of exploring implementation scheme for each process of JPEG2000 encoding. In order to demonstrate the practicability of the framework, a JPEG2000 encoder LSI has been implemented by using 0.18 mu m CMOS technology, which consists of two hardware modules and a configurable processor. This paper also describes real-time human object extraction algorithm, which call be used for video phone. Software simulation result of face and hair object extraction with the use of XScale processor claims that QCIF 15fps video call be processed in real-time.
  • H Tsutsui, T Masuzaki, Y Hayashi, Y Taki, T Izumi, T Onoye, Y Nakamura
    ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS 3189 296 - 308 0302-9743 2004 [Refereed][Not invited]
     
    For the exploration of system architecture dedicated to JPEG2000 coding, decoding and codec, a novel design framework is constructed. In order to utilize the scalability of JPEG2000 algorithm aggressively in system implementation, three types of modules are prepared for JPEG2000 coding/decoding/codec procedures, i.e. software, software accelerated with user-defined instructions, and dedicated hardware. Specifically, dedicated hardware modules for forward and inverse discrete wavelet transformation (shortly DWT), entropy coder, entropy decoder, and entropy codec as well as software acceleration of DWT procedure are devised to be used in the framework. Furthermore, a JPEG2000 encoder LSI, which consists of a configurable processor Xtensa, the DWT module, and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
  • H Sugita, VQ Minh, T Masuzaki, H Tsutsui, T Izumi, T Onoye, Y Nakamura
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS 3 873 - 876 2004 [Refereed][Not invited]
     
    An efficient scheme for JPEG2000 progressive decoding is proposed, which is capable of handling image codestreams with SNR progressiveness. In order to avoid processing, the same codestream data more than once when decoding SNR progressive images, a pair of techniques are introduced in our decoding scheme; reusing of intermediary decoded data and differential IDWT. Comprehensive evaluation of our scheme demonstrating that with 20% increase of required memory size, more than 40% of computational costs can be reduced in comparison with conventional (nonprogressive) decoding scheme.
  • High-Level Synthesis Design System for VLSI Processors in the 21st Century
    Yukihiro Nakamura, Hiroshi Tsutsui
    ASEAN Microelectronics 2003, AUN/SEED-Net Field-wise Seminar 2003/08 [Not refereed][Not invited]
  • 高度通信情報システムのためのアーキテクチャと設計技術
    Yukihiro Nakamura, Tomonori Izumi, Hiroshi Tsutsui
    第5回 YRP移動体通信産学官交流シンポジウム 2003/07 [Not refereed][Not invited]
  • Scalable Design Framework for JPEG2000 Encoder Architecture
    Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proc. of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2003) 372 - 377 2003/04 [Refereed][Not invited]
  • Y Hayashi, H Tsutsui, T Masuzaki, T Izumi, T Onoye, Y Nakamura
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II 2 740 - 743 2003 [Refereed][Not invited]
     
    A novel design framework for exploring JPEG2000 encoding system architecture is proposed. In this framework, each procedure of JPEG200 encoding is selectively implemented among those by software, software accelerated with user-defined instructions, or dedicated hardware, while maintaining the compliance with the requirements and constraints of each terminals and applications, so as to optimize the encoding system organization. Dedicated hardware modules for DWT and entropy coder as well as software acceleration of DWT procedure are devised to be used in the framework. Furthermore, an LSI, which consists of the DWT module and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
  • Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proceedings of the Society Conference of IEICE 一般社団法人電子情報通信学会 2002 89 - 89 1349-1369 2002/09 [Not refereed][Not invited]
  • JPEG2000 Fully Scalable Image Encoder by Configurable Processor
    Hiroshi Tsutsui, Takahiko Masuzaki, Masayuki Oyamatsu, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proc. of Euromedia Conference 168 - 172 2002/04 [Refereed][Not invited]
  • Takahiko Masuzaki, Hiroshi Tsutsui, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    IEICE General Conference 一般社団法人電子情報通信学会 2002 121 - 121 1349-1369 2002/03 [Not refereed][Not invited]
  • H Tsutsui, T Masuzaki, T Izumi, T Onoye, Y Nakamura
    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS 1 45 - 50 2002 [Refereed][Not invited]
     
    This paper discusses a design of high speed JPEG2000 encoder. JPEG2000 entropy coding is realized by hardware module since its computational cost accounts for roughly 65% of total according to software profiling.. Discrete wavelet transformation (DWT) is accelerated by attaching user-defined instructions to Tensilica's configurable processor Xtensa. Utilizing the 8,700 gate entropy coder with 27 kbit of memory and the custom instructions implemented by 8,000 gates, the number of cycles needed to encode an image is reduced to 31%.
  • T Masuzaki, H Tsutsui, T Izumi, T Onoye, Y Nakamura
    2002 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL III, PROCEEDINGS 3 77 - 80 2002 [Refereed][Not invited]
     
    To cope with the recent mobile scenes where images are used aggressively, a novel rate control scheme is proposed in this paper. The proposed scheme, dedicated for JPEG2000 image coding, is aiming at achieving low computational cost and small working memory size yet maintaining high image quality. By predicting the adequate number of coding passes and updates it adaptively in code-block coding, the proposed scheme reduces both computational cost and working memory size for bitstream buffering down to 29% and 13%, respectively.
  • T Masuzaki, H Tsutsui, T Izumi, T Onoye, Y Nakamura
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS 4 333 - 336 2002 [Refereed][Not invited]
     
    A novel rate control scheme is proposed dedicatedly for, JPEG2000 image coding. By predicting bitrate of coded data and updating it adaptively, the proposed scheme can be executed in parallel with the code-block coding of code-block coding such as coefficient bit modeling and arithmetic coding. The proposed scheme successfully reduces computational cost and working memory size of the process down to 29% and 13%, respectively, comparing to a conventional approach in case of 1/16 compression, and hence is suitable, to be used in embedded systems.
  • H Tsutsui, A Tomita, S Sugimoto, K Sakai, T Izumi, T Onoye, Y Nakamura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A (11) 2681 - 2689 0916-8508 2001/11 [Refereed][Not invited]
     
    In this paper, a design of Programmable Logic Device (PLD) and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array (PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables (LUTs). A series of cascaded LUTs in the array call generate more complex terms, which we call generalized complex terms (GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by ail existing approach. We design our PLD based oil a fundamental unit named nGCT cell which call be used as LUTs in multiple sizes or random access memories Implementation of the PLD based oil a fundamental unit named nGCT cell which call be used as LUTs or random access memories is also described.
  • Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    IEICE Society Conference 2001 115  1349-1369 2001/09 [Not refereed][Not invited]
  • Design of JPEG2000 Encoder for Fully Scalable Image Coding
    Hiroshi Tsutsui, Takahiko Masuzaki, Masayuki Oyamatsu, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proc. of World Multi-Conference on Systemics, Cybernetics and Informatics (SCI2001) XV 546 - 551 2001/07 [Refereed][Not invited]
  • Takahiko Masuzaki, Hiroshi Tsutsui, Masayuki Oyamatsu, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Technical report of IEICE. DSP 一般社団法人電子情報通信学会 101 (141(CAS2001 1-28)) 63 - 70 0913-5685 2001/06 [Not refereed][Not invited]
     
    This paper describes an architecture of JPEG2000 encoder for fully scalable image coding. To exploit different aspects of scalability inherent in JPEG2000, a set of novel mechanisms for pass termination, layering, and tilepart organization is devised. In addition, the proposed JPEG2000 encoder is implemented through the use of Xtensa configurable processor and optimized by user defined specific instructions. As a result, the number of processor cycles for encoding is reduced approximately by 40 %.
  • 16bit Free CPU の設計
    Hiroshi Tsutsui, Takahiko Masuzaki
    in Proc. of the 18th PARTHENON Workshop 2001/05 [Not refereed][Not invited]
  • Hiroshi Tsutsui, Kazuhiro Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 5 203 - 206 2001/05 [Refereed][Not invited]
  • Akihiko Tomita, Shigenori Sugimoto, Hiroshi Tsutsui, Kazuhisa Sakai, Tomonori Izumi, Yukihiro Nakamura
    システムLSI琵琶湖ワークショップ 243 - 246 2000/11 [Not refereed][Not invited]
  • LUTアレイ型PLDの設計と試作
    Shigenori Sugimoto, Akihiko Tomita, Hiroshi Tsutsui, Kazuhisa Sakai, Kazuhiro Hiwada, Yukihiro Nakamura
    VDEC LSI デザイナーフォーラム 85  2000/09 [Not refereed][Not invited]
  • Hiroshi Tsutsui, Kazuhiro Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    in Proc. of IPSJ DA Symposium 2000 (8) 21 - 26 1344-0640 2000/07 [Refereed][Not invited]
  • PCAデバイスの設計と試作
    Shigenori Sugimoto, Akihiko Tomita, Hiroshi Tsutsui, Kazuhisa Sakai, Kazuhiro Hiwada, Yukihiro Nakamura
    in Proc. of the 16th PARTHENON Workshop 31 - 42 2000/05 [Not refereed][Not invited]
  • 16bit Free CPU の設計
    Ryusuke Miyamoto, Hiroshi Tsutsui, Ryuta Nakanishi
    in Proc. of the 16th PARTHENON Workshop 2000/05 [Not refereed][Not invited]

MISC

  • Shingo Yoshizawa, Hiroshi Tsutsui  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences  106-  (3)  454  -455  2023/03
  • An Evaluation of Energy Consumption Under Different Spreading Factors for LoRa Modulation
    Takuya Yasugi, Hiroshi Tsutsui, Takeo Ohgane  Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido  151  -152  2021/09  [Not refereed][Not invited]
  • Promoting Wagyu Beef Traceability Between Australia and Japan Using Blockchain and IoT Technologies
    Hiroshi Tsutsui, Ying He, Takeo Ohgane  The Summaries of Research Announcements, FOOMA JAPAN 2021 Academic Plaza  28-  88  -91  2021/06  [Not refereed][Not invited]
  • An Evaluation of Lightweight Image Compression Using Line-By-Line Adaptive Processing with Golomb Coding
    大塚 祐大, 片岸 由奈子, 筒井 弘  Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido  89  -90  2020/11  [Not refereed][Not invited]
  • An Evaluation of SVM Based Color Detection for Stack Light Indicator Monitoring Systems Using Web Cameras for Automatic Production Lines
    髙杉 豪, 筒井 弘, 宮永 喜一  IEICE Society Conference  85  -85  2020/09  [Not refereed][Not invited]
  • Yunzhe Wang, Yu Tian, Yoshikazu Miyanaga, Hiroshi Tsutsui  IEICE Technical Report  120-  (51)  49  -54  2020/06  [Not refereed][Not invited]
  • An Experimental Evaluation of Parking Detection Using Web Cameras in a Parking Area
    Takuto Fukusaki, Hiroshi Tsutsui, Yoshikazu Miyanaga  IEICE General Conference  139  -139  2020/03  [Not refereed][Not invited]
  • High-Throughput Scalable Radix-4 FFT Processor Design and Its Area Evaluation
    Tomotaka Kawabata, Hiroshi Tsutsui, Yoshikazu Miyanaga  IEICE General Conference  124  -124  2020/03  [Not refereed][Not invited]
  • Hardware Design of High Efficient Wireless Communication Systems for 5G Mobile Networks
    Mariko Hirayama, Hiroshi Tsutsui, Yoshikazu Miyanaga  Proceedings of IEICE Hokkaido Section Student Council Internet Symposium  2020/02  [Not refereed][Not invited]
  • 中越達也, 早坂昇, 筒井弘, 宮永喜一  電子情報通信学会大会講演論文集(CD-ROM)  2019-  ROMBUNNO.A‐15‐2  2019/03/05  [Not refereed][Not invited]
  • 山田健太郎, 筒井弘, 須藤彰紘, 宮永喜一  電子情報通信学会大会講演論文集(CD-ROM)  2019-  ROMBUNNO.A‐15‐10  2019/03/05  [Not refereed][Not invited]
  • Yoshikazu Miyanaga, Junji Yamano, Masaki Miura, Tohru Gotoh, Takashi Imagawa, Hiroshi Tsutsui  2018 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2018 - Proceedings  1087  -1090  2019/03/04  [Not refereed][Not invited]
     
    © 2018 APSIPA organization. This paper shows the total system of real-time FHD video communication over wireless system. The wireless system can realize the data rate of 3Gbps by use of an 80-MHz baseband bandwidth and a 8\times 8 MIMO-OFDM scheme. A low-latency and the optimum pipelined architecture are realized into all processing blocks. In addition, the video compression is based on loss-less coding/decoding. By using this mechanism, the original video can be transferred by a wireless system. In addition, the minimum latency can be realized by using a small size block based video coding. It provides the real-time operations of video communications. The proposed architecture realizes low power consumption.
  • 福元敦己, 今川隆司, 筒井弘, 宮永喜一, 越智裕之  電子情報通信学会技術研究報告  118-  (473(SIS2018 37-52))  5‐9  2019/02/27  [Not refereed][Not invited]
  • 浮橋慶太, 今川隆司, 筒井弘, 宮永喜一, 越智裕之  電子情報通信学会技術研究報告  118-  (473(SIS2018 37-52))  53‐58  2019/02/27  [Not refereed][Not invited]
  • An Evaluation of Offline Video Analysis Acceleration for Surveillance Cameras Utilizing Multi-core Processors with Frame-level Parallelization
    福﨑 卓人, 筒井 弘, 宮永 喜一  Proceedings of IEICE Hokkaido Section Student Council Internet Symposium  2019/02  [Not refereed][Not invited]
  • Yu Tian, Jiayue Tang, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga  ISCIT 2018 - 18th International Symposium on Communication and Information Technology  101  -104  2018/12/24  [Not refereed][Not invited]
     
    © 2018 IEEE. This paper is mainly about the accuracy on the children speech recognition under noisy circumstances and methods to improve it. The power of the children's speech is lower than the adult. The accuracy of children speech recognition is unavoidably affected by the ambient noise. We executed a series of experiments to calculate the recognition accuracy for children speech under clean condition and different noisy conditions. It has been reported that running spectrum analysis (RSA) and running spectrum filtering (RSF) have the capability to enhance the robustness in the speech recognition system under noisy conditions. In subsequent experiments, we added RSA and RSF to the speech feature extraction and obtained a children recognition system with enhanced noise suppression capability and achieved higher recognition accuracy.
  • An Accuracy Evaluation of Fingerprint Database Constructed by Mean-Shift Clustering for WiFi Indoor Positioning Systems
    Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga  Proceedings of 2018 Winter International Symposium on Big-Data, Cybersecurity and IoT  2018/12  [Not refereed][Not invited]
  • WiFi Indoor Positioning System Using Fingerprint Database Constructed by Mean-Shift Clustering with Estimated Reference Locations
    Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga  Proceedings of the GSB Student Workshop, The 2nd GI-CoRE GSQ, GSB & IGM Joint Symposium  2018/08  [Not refereed][Not invited]
  • 渡辺大詩, 筒井弘, 今川隆司, 宮永喜一  映像情報メディア学会技術報告  42-  (23(BCT2018 60-72))  47‐50  2018/07/19  [Not refereed][Not invited]
  • Xiaonan Jiang, Tatsuya Nakagoshi, Jiayue Tang, Riku Takanashi, Yu Tian, Hiroshi Tsutsui, Yoshikazu Miyanaga  IEICE Technical Report  118-  (149)  53  -58  2018/07  [Not refereed][Not invited]
  • 池下貴大, 渡辺大詩, 筒井弘, 宮永喜一  映像情報メディア学会技術報告  42-  (11(BCT2018 38-49))  25‐28  2018/03/02  [Not refereed][Not invited]
  • 井原大文, 今川隆司, 上坂浩貴, 鴻上慎吾, 筒井弘, 宮永喜一, 越智裕之  電子情報通信学会技術研究報告  117-  (455(VLD2017 89-128))  55‐60  2018/02/21  [Not refereed][Not invited]
  • Yoshikazu Miyanaga, Hiroshi Tsutsui, Takashi Imagawa  2017 17th International Symposium on Communications and Information Technologies, ISCIT 2017  2018-January-  1  -5  2018/01/16  [Not refereed][Not invited]
     
    © 2017 IEEE. The developed system has achieved the data rate of 3Gbps by use of an 80-MHz baseband bandwidth and a 8×8 MIMO-OFDM scheme. This paper describes the VLSI implementation of the 8×8 MIMO-OFDM system. A low-latency and the optimum pipelined architecture are realized into all processing blocks. It provides the real-time operations on OFDM modulation and MIMO detection. The proposed architecture also realizes low power consumption. This system has been applied for high-quality video communication. With some of results on field experiments, the system performance for video communications is described under real environments.
  • 渡辺大詩, 池下貴大, 筒井弘, 今川隆司, 宮永喜一  電気・情報関係学会北海道支部連合大会講演論文集(CD-ROM)  2017-  ROMBUNNO.71  2017/10/28  [Not refereed][Not invited]
  • Hiroshi Tsutsui, Mitsuji Muneyasu  IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences  100-A-  (11)  2219  -2220  2017
  • チップ試作による最小動作電圧予測手法の評価
    川島 潤也, 筒井 弘, 越智 裕之, 佐藤 高史  電子情報通信学会ICD研究会  ICD2012-87-  3  -8  2012/12  [Not refereed][Not invited]
  • Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato  研究報告システムLSI設計技術(SLDM)  2012-  (21)  1  -6  2012/11/19  
    With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65nm CMOS technology, the proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65nm CMOS technology, the proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.
  • 粟野 皓光, 清水 裕史, 筒井 弘, 越智 裕之, 佐藤 高史  研究報告システムLSI設計技術(SLDM)  2011-  (15)  1  -6  2011/11/21  
    ランダムテレグラフノイズ (Random Telegraph Noise: RTN) は微細デバイスの信頼性や回路特性に関わる物理現象であり,様々なモデル化手法が提案されている.閾値電圧の変動'|届と変動時定数は,種々のモデルに共通する特に重要なパラメータであるが,測定データからこれらを求めることは困難な課題となっている.本研究では,キャリアの捕獲と放出の過程を統計的モデルとして表現し,マルコフ連鎖モンテカルロ法 (MCMC) を用いて各パラメータをベイズ推定する手法を提案する.人工的に生成した RTN 信号に提案手法を適用し,良好な結果が得られたが,実測信号については課題も見られた.Random Telegraph Noise (RTN) is a physical phenomenon that is considered to determine reliability and performance of circuits. Time constants of carrier capture and emission, and an associated change of threshold voltage are the important parameters commonly involved in various models, but their extraction from time-domain observations has been a difficult task. In this study, we propose a statistical method for estimating the time constants and the magnitude of threshold voltage shift. Our method is based on a graphical network representation and the parameters are estimated using Markov Chain Monte Carlo (MCMC) method. Experimental application of the proposed method on a synthetic time-domain RTN signal was very successful, while estimation examples on measured RTN signals suggest there is room for further improvement.
  • 宮川 哲朗, 筒井 弘, 越智 裕之, 佐藤 高史  研究報告システムLSI設計技術(SLDM)  2011-  (13)  1  -6  2011/11/21  
    ランダムウオークによる線形回路の過渡解析を高速化する手法を提案する.提案手法では,準ゼロ分散推定法に基づいて逐次的な確率更新を行う際に,一解析時刻前の節点電圧を利用して解析に必要なサンプル数を削減する.また解析中にサンプル数を自動的決定することにより,節点電位の変動による推定の不安定化を防止しつつ高速化を図る.提案手法により,従来のランダムウォーク法に基づく過渡解析に対して 10 倍以上の高速化を実現し,サンプル数自動決定により高速化と解析の安定化の両立を実現した.We propose a method to accelerate random walk based transient analysis of linear circuits. Our method uses quasi-zero-variance estimation with adaptive sample number determination, in which walk probabilities are adaptively updated to reduce estimation variance. The node voltages of previous time step are reused to give initial guesses for alternative probabilities at every time point, which reduces the total number of required samples. An adaptive determination of the number of samples makes estimation very stable and accelerate the analysis even further. The proposed analysis achieves more than 10x speedup against the conventional method.
  • 森下 拓海, 筒井 弘, 越智 裕之, 佐藤 高史  研究報告システムLSI設計技術(SLDM)  2011-  (12)  1  -5  2011/11/21  
    半導体プロセスの微細化が進み,電源回路網の解析が重要になっている.また,電源回路網それ自体の規模も大きく,今後のさらなる巨大化に対応するためにも,回路解析の高速化省メモリ化が大きな課題となっている.ブロック反復法は直接法と反復法を組み合わせた解析方法であり,大規模電源回路網解析への応用が期待されている.本稿ではブロック反復法の高速化を目的として,SOR 法およびブロック分割の観点から収束の加速方法を検討する.Because of its extremely large size, power grid analysis has been a computationally challenging problem both in terms of runtime and memory usage. LU factorization has been widely used to analyze voltage drop simulations due to its stability, but contiguous technology scaling demands even more efficient calculation methods. In this paper, application of block-iterative method, which combines LU factorization and iterative method, is proposed for efficient analysis of power grid analysis. Automatic adjustment of relaxation factor in successive over-relaxation method and block decomposition algorithm are proposed. Evaluation results are also presented.
  • TOMITA Akihiko, SUGIMOTO Shigenori, TSUTSUI Hiroshi, SAKAI Kazuhisa, HIWADA Kazuhiro, IZUMI Tomonori, ONOYE Takao, NAKAMURA Yukihiro  Technical report of IEICE. VLD  100-  (473)  173  -178  2000/11/23  
    This paper proposes an architecture of LUT-array-based PLD, which is based on an 3-inputs LUT array instead of an AND array that PLA is based on. Utilizing cascaded 3-inputs LUTs, each of which can express an arbitrary Boolean function with three inputs, logic circuits can be mapped effectively to the PLD in compared with ordinary PLAs. In addition, an address decoding mechanism is devised to have an ability to treat a set of LUTs as an LUT with large number of inputs or a memory. Experimental results show that benchmark circuits can be mapped with 14.9% less number of terms to LUT-array-based PLD than that to PLA.

Presentations

  • Design Techniques for Wireless Communication and Image Processing IP Cores  [Invited]
    Hiroshi Tsutsui
    The 1st Hokkaido Young Professionals Workshop  2021/10

Teaching Experience

  • Media Processing SystemMedia Processing System Hokkaido University
  • Exercise in Media Network ⅠExercise in Media Network Ⅰ Hokkaido University
  • Media Network Laboratory ⅡBMedia Network Laboratory ⅡB
  • Media Network Laboratory ⅠBMedia Network Laboratory ⅠB Hokkaido University
  • Exercise in Media Network ⅡExercise in Media Network Ⅱ Hokkaido University
  • Network DesignNetwork Design Hokkaido University
  • Network SystemsNetwork Systems Hokkaido University

Association Memberships

  • THE INSTITUTE OF IMAGE INFORMATION AND TELEVISION ENGINEERS   INFORMATION PROCESSING SOCIETY OF JAPAN   ACM   THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS   IEEE   THE INSTITUTE OF ELECTRICAL ENGINEERS OF JAPAN   パルテノン研究会   THE INSTITUTE OF IMAGE ELECTRONICS ENGINEERS OF JAPAN   

Research Projects

  • 日本学術振興会:科学研究費助成事業
    Date (from‐to) : 2023/04 -2027/03 
    Author : 大鐘 武雄, 筒井 弘, 西村 寿彦
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research
    Date (from‐to) : 2023/04 -2026/03 
    Author : 筒井 弘
  • 極低消費電力型マルチメディアIoTシステムの研究開発
    総務省:戦略的情報通信研究開発推進事業(SCOPE)先進的電波有効利用型
    Date (from‐to) : 2020/04 -2021/03 
    Author : 筒井 弘
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    Date (from‐to) : 2016/04 -2020/03 
    Author : Sakamoto Yuji
     
    We succeeded in developing head-mounted displays (holo-HMDs) with the world's smallest and lightest electronic holography technology. In addition, we have proposed a method that enables real-time calculation and communication at the current level of hardware technology though researches of high-speed calculation methods and data compression methods. These researches indicate that the holo-HMD can be realized as a system. On the other hand, the deterioration of image quality due to speckles is a remained problem, but we have proposed the suppression method using an algorithm and showed the possibility of suppression. It is necessary to continue to study the measurement of physiological responses.
  • 極低消費電力型マルチメディアIoTシステムの研究開発
    総務省:戦略的情報通信研究開発推進事業(SCOPE)先進的電波有効利用型
    Date (from‐to) : 2018/03 -2020/03 
    Author : 宮永 喜一, 筒井 弘
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research Grant-in-Aid for Young Scientists (B)
    Date (from‐to) : 2014/04 -2017/03 
    Author : Tsutsui Hiroshi
     
    Recent CMOS image sensors have several image acquisition modes such as (1) high-resolution and normal-frame-rate and (2) low-resolution and high-frame-rate. Assuming these two types of video, that is high-resolution video and high-frame-rate video, can be obtained simultaneously, a motion-compensated frame interpolation method to generate high-resolution and high-frame-rate video from these videos is proposed. By using the proposed approach, efficient video acquisition can be archived. Considering adaptive processing based on motions in video sequences, a image shrinking based high-speed moving region extraction method is also proposed.
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    Date (from‐to) : 2011 -2013 
    Author : OCHI Hiroyuki, SATO Takashi, TSUTSUI Hiroshi, NAKAMURA Yukihiro
     
    To realize digital data storage systems of extremely long lifetime, architecture for sealed wafer-scale mask ROM that is capable of contactless power delivery and contactless mutual communication has been investigated in order to enhance robustness of mask ROM device. As for contactless power delivery, on-chip solar cell has been investigated, and "boost interleaved solar cell" has been proposed. As for contactless mutual communication, low power Tx/Rx circuits to utilize on-chip dipole antenna. NAND-type high-density low operating voltage mask ROM has been designed and evaluated. Finally, hierarchical architecture with aggressive power-gating feature has been developed.
  • Japan Society for the Promotion of Science:Grants-in-Aid for Scientific Research Grant-in-Aid for Scientific Research (B)
    Date (from‐to) : 2010 -2012 
    Author : SATO Takashi, OCHI Hiroyuki, TSUTSUI Hiroshi
     
    Timing constraint is one of the most important objectives in advanced integrated circuit design. In this project, acceleration of the timing analysis is studied. Based on the measurements on test-chips, variability- and degradation-aware device models have been first proposed to accurately handle timing information of miniaturized devices. A new algorithm of timing analysis has then been implemented on a hardware, thorough which by more than ten times acceleration has been achieved while maintaining advantages of Monte Carlo based methods that can handle arbitrary delay distribution.
  • 日本学術振興会:科学研究費助成事業
    Date (from‐to) : 2002 -2004 
    Author : 筒井 弘
     
    本研究の目的は,スケーラブル動画像符号化の組込み機器への効率的な実装手法の提案である.前年度までに於て,JPEG2000スケーラブル符号化/復号化を対象として,様々なシステム要求に対して最適な実装を容易かつ効率的に実現可能とするスケーラブルなデザインフレームワークの実現を目標とし,検討および実装/評価を行っている.本年度は,これまでに実装を行ったソフトウェアならびにハードウェア処理モジュールを組合せ,フレームワークの全体の構築を行い,「組込み向けJPEG2000符号化方式の実装法」と題した博士論文にまとめた.提案デザインフレームワークでは,アプリケーションの要求や設計時の制約条件に応じて,共通モジュールを選択的に利用することによって,最適なJPEG2000復号器/復号器/コーデックの実装を得ることができる. さらに,JPEG2000で各フレームを圧縮する動画像符号化方式であるMotion JPEG2000に関して,組込み機器での利用が見込まれる,低ビットレート符号化時における主観画質の向上手法を提案した.提案手法ではJPEG2000の持つ特長と人間の視覚特性を利用して,Motion JPEG2000の主観的画質を向上させる.JPEG2000は変換に離散ウェーブレット変換(DWT)を用いているために,符号化の過程で画像内の位置に応じて符号量の割り当てを制御することが容易となっている.人間の視覚特性は刺激の空間周波数,時間周波数に依存して特性が変化し,周波数が高いほど感度が低下する.提案する手法は,人間の視覚特性を利用して,時間周波数,空間周波数が高い領域に割り当てる符号量を減らし,それ以外の領域に割り当てる符号量を増やす.その結果,動画像全体の主観的画質を向上させることに成功した.


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