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Last Updated :2024/09/09

研究者情報

マスター

アカウント（マスター）

  • 氏名

    筒井　弘(ツツイ　ヒロシ), ツツイ　ヒロシ

所属（マスター）

  • 情報科学研究院　メディアネットワーク部門　情報通信システム学分野

所属（マスター）

  • 情報科学研究院　メディアネットワーク部門　情報通信システム学分野

独自項目

syllabus

  • 2021, ネットワークシステム特論, Network Systems, 修士課程, 情報科学研究科, 通信プロトコル，ネットワーク・セキュリティ，ブロードバンド伝送，無線通信，orthogonal frequency-division multiplexing (OFDM)，集積回路，組込みシステム，ディジタルメディア処理，field-programmable gate array (FPGA)
  • 2021, ネットワークシステム特論, Network Systems, 修士課程, 情報科学院, 通信プロトコル，ネットワーク・セキュリティ，ブロードバンド伝送，無線通信，orthogonal frequency-division multiplexing (OFDM)，集積回路，組込みシステム，ディジタルメディア処理，field-programmable gate array (FPGA)
  • 2021, Blockchain, Blockchain, 博士後期課程, 情報科学院, Internet, Cybersecurity, Blockchain, IoT, Ethereum, DApps, Smart contracts
  • 2021, ネットワークシステム特論, Network Systems, 博士後期課程, 情報科学研究科, 通信プロトコル，ネットワーク・セキュリティ，ブロードバンド伝送，無線通信，orthogonal frequency-division multiplexing (OFDM)，集積回路，組込みシステム，ディジタルメディア処理，field-programmable gate array (FPGA)
  • 2021, ネットワークシステム特論, Network Systems, 博士後期課程, 情報科学院, 通信プロトコル，ネットワーク・セキュリティ，ブロードバンド伝送，無線通信，orthogonal frequency-division multiplexing (OFDM)，集積回路，組込みシステム，ディジタルメディア処理，field-programmable gate array (FPGA)
  • 2021, モバイル通信メディア, Mobile Media Communication, 学士課程, 工学部, フェージング，スマートフォン，Wi-Fi，LPWA，CDMA，OFDM
  • 2021, ネットワーク構成論, Network Design, 学士課程, 工学部, ネットワークトポロジー，通信プロトコル，ブロードバンドネットワーク，ネットワークサービス，ネットワークセキュリティ，待ち行列理論

researchmap

プロフィール情報

学位

  • 博士(情報学)（京都大学）

プロフィール情報

  • 姓

    筒井, ツツイ

  • 名

    弘, ヒロシ

  • ID各種

    201301093331929718

対象リソース

業績リスト

研究キーワード

  • 無線通信   プロセッサ・アーキテクチャ   画像処理   電子回路CAD   集積回路設計   

研究分野

  • ものづくり技術（機械・電気電子・化学工学） / 通信工学
  • ものづくり技術（機械・電気電子・化学工学） / 電子デバイス、電子機器
  • 情報通信 / 情報ネットワーク
  • 情報通信 / 計算機システム

経歴

  • 2019年04月 - 現在 北海道大学 情報科学研究院 准教授
  • 2013年05月 - 2019年03月 北海道大学 情報科学研究科 准教授
  • 2010年04月 - 2013年04月 京都大学 大学院・情報学研究科 助教
  • 2007年04月 - 2010年03月 大阪大学 情報科学研究科 特任助教
  • 2005年04月 - 2007年03月 京都大学 情報学研究科 特任助手

学歴

  • 2000年04月 - 2005年03月   京都大学   情報学研究科   通信情報システム専攻
  • 1996年04月 - 2000年03月   京都大学   工学部   電気電子工学科

委員歴

  • 2012年05月 - 2014年05月   電子情報通信学会 基礎境界ソサイエティ スマートインフォメディアシステム研究会   幹事
  • 2013年 - 2013年   2013 International Workshop on Smart Info-Media Systems in Asia (SISA 2013)   Technical Program Committee Member
  • 2013年   ISPACS 2013   Publicity Chair
  • 2010年05月 - 2012年05月   電子情報通信学会 基礎境界ソサイエティ スマートインフォメディアシステム研究会   幹事補佐
  • 2012年 - 2012年   2012 International Workshop on Smart Info-Media Systems in Asia (SISA 2012)   Technical Program Committee Member
  • 2011年 - 2011年   2011 International Workshop on Smart Info-Media Systems in Asia (SISA 2011)   Technical Program Committee Member
  • 2011年 - 2011年   2011 International Workshop on Smart Info-Media Systems in Asia (SISA 2011)   General Secretary
  • 2011年 - 2011年   電子情報通信学会2011年ソサイエティ大会 プログラム編成委員会   委員
  • 2010年 - 2010年   2010 International Workshop on Smart Info-Media Systems in Asia (SISA 2010)   Technical Program Committee Member
  • 2010年 - 2010年   電子情報通信学会2010年ソサイエティ大会 プログラム編成委員会   委員
  • 2009年 - 2009年   2009 International Workshop on Smart Info-Media Systems in Asia (SISA 2009)   Technical Program Committee Member
  • 2008年 - 2008年   2008 International Workshop on Smart Info-Media Systems in Bangkok (SISB 2008)   General Secretary
  • 2007年 - 2007年   SASIMI 2007, Technical Program Committee   Member
  • 2006年 - 2006年   ITC-CSCC 2006   General Secretary

受賞

  • 2013年10月 SASIMI Organizing Committee SASIMI 2013 Outstanding Paper Award
     Place-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy 
    受賞者: Takashi Imagawa;Masayuki Hiromoto;Hiroshi Tsutsui;Hiroyuki Ochi;Takashi Sato
  • 2009年10月 IEEE/ACM/IFIP 7th IEEE/ACM/IFIP Workshop on Embedded Systems for Real-Time Multimedia (ESTIMedia2009) Best Paper Award
     A high-throughput pipelined architecture for JPEG XR encoding 
    受賞者: Koichi Hattori;Hiroshi Tsutsui;Hiroyuki Ochi;Yukihiro Nakamura
  • 2008年07月 情報処理学会 マルチメディア，分散，協調とモバイル(DICOMO2008)シンポジウム優秀論文賞
     メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法の検討 
    受賞者: 廣本 正之;筒井 弘;越智 裕之;小佐野 智之;石川 憲洋;中村 行宏
  • 2007年09月 電子通信情報学会 電子情報通信学会ソサイエティ大会基礎・境界ソサイエティ特別企画「若手研究者のための映像圧縮コンテスト」最優秀賞
     古いフィルム映像を模擬した劣化動画像の符号化手法 
    受賞者: 筒井 弘
  • 2005年09月 電子通信情報学会 電子情報通信学会平成17年度学術奨励賞
     JPEG2000 エントロピ符号器における SRAM の構成方法 
    受賞者: 筒井 弘;菅野 裕揮;増崎 隆彦;越智 裕之;尾上 孝雄;中村 行宏
  • 2001年05月 パルテノン研究会 パルテノン研究会 ASICデザインコンテスト 優秀賞
     16bit Free CPU の設計 
    受賞者: 筒井 弘;増崎 隆彦
  • 2000年05月 パルテノン研究会 パルテノン研究会 ASICデザインコンテスト 奨励賞
     16bit Free CPU の設計 
    受賞者: 宮本 龍介;筒井 弘;中西 龍太

論文

  • Kota Hirai, Hiroshi Tsutsui, Ying He, Takeo Ohgane
    ISCIT 231 - 234 2023年
  • Experimental Evaluation and Field Tests of LoRa Energy Consumption Optimization Approach Using Software-Defined Radio
    Kyotaro Kunii, Takuya Yasugi, Hiroshi Tsutsui, Takeo Ohgane
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 45 - 50 2022年09月 [査読有り][通常論文]
  • Haojiong Wang, Hiroshi Tsutsui, Matteo Convertino
    4th IEEE Global Conference on Life Sciences and Technologies(LifeTech) 286 - 288 2022年
  • 吉澤 真吾, 筒井 弘
    電子情報通信学会 基礎・境界ソサイエティ Fundamentals Review 15 3 243 - 244 一般社団法人 電子情報通信学会 2022年
  • Shingo Kato, Hiroshi Tsutsui
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 154 - 157 2021年09月 [査読有り][通常論文]
  • Jimpu Suzuki, Hiroshi Tsutsui, Takeo Ohgane
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 71 - 76 2021年09月 [査読有り][通常論文]
  • An Approach to Maximize SDMA Uplink Communication in an IoT Media Access Control Protocol
    Atsuki Kuriyama, Hiroshi Tsutsui
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 49 - 52 2020年12月 [査読有り][通常論文]
  • Haruki Inaba, Hiroshi Tsutsui, Takuya Yasugi
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 135 - 138 2020年12月 [査読有り]
  • Tomotaka Kawabata, Hiroshi Tsutsui
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 114 - 117 2020年12月 [査読有り]
  • Jimpu Suzuki, Hiroshi Tsutsui, Takeo Ohgane
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 110 - 113 2020年12月 [査読有り]
  • Takuto Fukusaki, Hiroshi Tsutsui, Takeo Ohgane
    Asia-Pacific Signal and Information Processing Association Annual Summit and Conference(APSIPA) 100 - 103 2020年12月 [査読有り]
  • Myat Hsu AUNG, Hiroshi TSUTSUI, Yoshikazu MIYANAGA
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E103.A 12 1483 - 1493 2020年12月01日
  • Robot Speech Recognition of Child Isolated Words
    Yoshikazu Miyanaga, Yu Tian, Hiroshi Tsutsui
    International STEM Education Conference (iSTEM-Ed 2020) 2020年11月 [査読有り][通常論文]
  • Hiroshi Tsutsui, Kentaro Yamada, Akihiro Sudou, Yoshikazu Miyanaga
    2019 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference (APSIPA ASC) 1423 - 1426 2019年11月 [査読有り][通常論文]
  • Improvement on Children Speech Recognition under Low Signal-to-Noise Ratio Environment
    Yu Tian, Jiayue Tang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 4 - 6 2019年08月 [査読有り][通常論文]
  • Robust Isolated Speech Recognition for Keyword Detection System Using Hidden Markov Model
    Jiayue Tang, Yu Tian, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 161 - 163 2019年08月 [査読有り][通常論文]
  • Voice Activity Detection Using Running Spectrum Analysis for Noise Robust Speech Recognition
    Riku Takanashi, Tatsuya Nakagoshi, Noboru Hayasaka, Yoshikazu Miyanaga, Hiroshi Tsutsui
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 164 - 166 2019年08月 [査読有り][通常論文]
  • Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of the 23rd Multi-conference on Systemics, Cybernetics and Informatics (WMSCI 2019) 2 7 - 10 2019年07月 [査読有り][通常論文]
  • Dabwitso KASAUKA, Kenta SUGIYAMA, Hiroshi TSUTSUI, Hiroyuki OKUHATA, Yoshikazu MIYANAGA
    IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences E102.A 6 775 - 782 2019年06月01日 [査読有り][通常論文]
  • Yoshikazu Miyanaga, Masaki Miura, Tohru Gotoh, Junji Yamano, Takashi Imagawa, Hiroshi Tsutsui
    2018 International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) 107 - 110 2018年11月 [査読有り]
  • Jiayue Tang, Yu Tian, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2018 18th International Symposium on Communications and Information Technologies (ISCIT) 2018年09月 [査読有り]
  • Keyword Detection Using F0-VAD in Robust Isolated Phase Recognition System
    Jiayue Tang, Yu Tian, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 121 - 124 2018年08月 [査読有り][通常論文]
  • Robust Children Isolated Speech Recognition System Using RSA and RSF
    Yu Tian, Jiayue Tang, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 113 - 116 2018年08月 [査読有り][通常論文]
  • An Evaluation of Entropy Coding Approaches in Block-Based Adaptive Lossless Image Coding Method for Embedded Systems
    Yunako Katagishi, So Tsuyuguchi, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2018年08月 [査読有り][通常論文]
  • 今川 隆司, 池下 貴大, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 2017年11月 [査読無し][通常論文]
  • Robust Isolated Phrase Recognition System Using Running Spectrum Analysis
    Xiaonan Jiang, Tatsuya Nakagoshi, George Mufungulwa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Shini-ichi Abe
    Proceedings of Intelligent Transportation Society of America World Congress (ITS 2017) 2017年10月 [査読有り][通常論文]
  • George Mufungulwa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Shin-Ichi Abe, Mitsuru Ochi
    ISSCS 2017 - International Symposium on Signals, Circuits and Systems 2017年09月12日 [査読有り][通常論文]
     
    This paper proposes a new noisy robust speech recognition method. Under noise circumstances, several noise reduction methods have been developed and they are applied in various noise conditions. However, in case of similar pronunciation speech, for example, it is still not easy to realize high recognition accuracy. In this paper, the new processing algorithm into speech modulation spectrum is proposed as running spectrum analysis (RSA) and it is adequately applied to observed speech data. Using this method, the proposed system can improve about 1-4 % compared to current conventional methods.
  • An Evaluation of Phrase Rejection Using K-means Clustering for Robust Speech Recognition
    Xiaonan Jiang, Tatsuya Nakagoshi, Noboru Hayasaka, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 154 - 157 2017年09月 [査読有り][通常論文]
  • An Accuracy Evaluation of WiFi Based Indoor Positioning System Using Estimated Reference Locations
    Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 321 - 326 2017年09月 [査読有り][通常論文]
  • An Evaluation of Foreground Extraction Using Background Subtraction and GrabCut
    Kentaro Yamada, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 27 - 30 2017年08月 [査読有り][通常論文]
  • Low-Cost Adaptive Block-Based Lossless Compression Method for Memory Bandwidth Reduction
    So Tsuyuguchi, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 97 - 100 2017年08月 [査読有り][通常論文]
  • Robust Speech Recognition Using Low-pass Processing RSA in the Frequency Domain
    Tatsuya Nakagoshi, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 139 - 142 2017年08月 [査読有り][通常論文]
  • Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga
    GI-CoRE GSQ, GSB & IGM Joint Symposium 2017年07月 [査読無し][通常論文]
  • Enhanced Running Spectrum Analysis for Robust Speech Recognition Under Adverse Conditions: Case of Japanese Speech
    George Mufungulwa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Shini-ichi Abe
    ECTI Transactions on Computer and Information Technology (ECTI-CIT) 2017年07月 [査読有り][通常論文]
  • 変分法を用いた透過マップ推定によるヘイズ除去における環境光推定の一検討
    杉山 健太, 今川 隆司, 筒井 弘, 宮永 喜一
    第30回 回路とシステムワークショップ 57 - 60 2017年05月 [査読無し][通常論文]
  • Speech Recognition Using TVLPC Based MFCC for Similar Pronunciation Phrases
    George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Shini-ichi Abe, Yoshikazu Miyanaga
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 1918 - 1921 2017年05月 [査読有り][通常論文]
  • MIMO-OFDM復調のためのガウスジョルダン法を用いたFPUベースの逆行列演算のハードウェア実装
    池下 貴大, 今川 隆司, 筒井 弘, 宮永 喜一
    電気・情報関係学会北海道支部連合大会 174 - 175 2016年11月 [査読無し][通常論文]
  • 変分法を用いた透過マップ推定によるヘイズ除去の一検討
    杉山 健太, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会ソサイエティ大会 2016年09月 [査読無し][通常論文]
  • Robust Speech Recognition using MFCC with Triangular Mel Filtered Time Varying LPC
    George Mufungulwa, Hiroshi Tsutsui, Alia Asheralieva, Yoshikazu Miyanaga
    電子情報通信学会ソサイエティ大会 2016年09月 [査読無し][通常論文]
  • An Accuracy Evaluation of Motion-Compensated Frame Interpolation Using High-Resolution Video and High-Frame-Rate Video
    Hiroki Uesaka, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 2016年09月 [査読有り][通常論文]
  • One-block shared memory FFT processor by using new memory addressing approach
    Licheng Rao, Shingo Yoshizawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2016年08月 [査読有り][通常論文]
  • New MFCC with Triangular Mel Filtered Time Varying LPC
    George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 2016年08月 [査読有り][通常論文]
  • Speech Recognition using MFCC with Time Varying LPC for Similar Pronunciation Phrases
    George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Yoshikazu Miyanaga
    The 31st International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 2016年07月 [査読有り][通常論文]
  • Na Zhu, Yoshikazu Miyanaga, Hiroshi Tsutsui, Masumi Watanabe
    IEICE Technical Report 116 81 61 - 64 電子情報通信学会 2016年06月 [査読無し][通常論文]
  • George Mufungulwa, Alia Asheralieva, Hiroshi Tsutsui, Yoshikazu Miyanaga
    IEICE Technical Report 116 81 55 - 59 電子情報通信学会 2016年06月 [査読無し][通常論文]
  • 無線カメラシステムを用いた 3 次元再構成の通信量削減に向けた一評価
    青木 皓, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会北海道支部学生会インターネットシンポジウム予稿集 2016年02月 [査読無し][通常論文]
  • 繰り返し縮小画像平滑化のマルチコアプロセッサによるフレーム単位並列化の評価
    今井 誠二郎, カサウカ ダブィソ, 今川 隆司, 筒井 弘, 奥畑 宏之, 宮永 喜一
    電子情報通信学会北海道支部学生会インターネットシンポジウム予稿集 2016年02月 [査読無し][通常論文]
  • Dabwitso Kasauka, Hiroshi Tsutsui, Seijiro Imai, Takashi Imagawa, Hiroyuki Okuhata, Yoshikazu Miyanaga
    2016 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) 1 - 5 2016年 [査読有り][通常論文]
     
    Recently, edge preserving image smoothing techniques have been developed based on fast Fourier transformation (FFT) methods. In this paper, we present an alternative implementation for an existing image smoothing algorithm using a spatial iterative method, multigrid conjugate gradient (MGCG). In the case of FFT solvers, so-called wraparound error occurs in the image boundary due to the periodicity implied by the discrete Fourier transformation. Since the proposed method utilizes iterative methods in the spatial domain, wraparound error free image smoothing can be archived. Experimental results shows that the proposed method provides superior results compared to an FFT solver in terms of computational cost and smoothing quality.
  • Seijiro Imai, Dabwitso Kasauka, Hiroshi Tsutsui, Takashi Imagawa, Hiroyuki Okuhata, Yoshikazu Miyanaga
    2016 INTERNATIONAL SYMPOSIUM ON INTELLIGENT SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ISPACS) 211 - 214 2016年 [査読有り][通常論文]
     
    Iterative shrinkage smoothing algorithm can perform image smoothing with eliminating fine details and preserving principal edges in an image. However, real time processing is difficult due to large processing time when input image size is large. By utilizing downscaled image of an input image, the processing time can be dramatically reduced. In this case, however, the information of preserved principal edges is not accurate. Considering the applications utilizing such edge preserving smoothing algorithms, such as image tone mapping and detail enhancement, inaccurate principal edge information degrades the quality of resulted images. In this paper, we focus on tone mapping in the applications and propose processing time reduction method of tone mapping based on iterative shrinkage smoothing by utilizing parallel processing. Experimental results show that the proposed method improves the frame rates to 16 and 10 times for VGA and full HD resolutions, respectively, compared to single process implementation.
  • 岩田 祐之, 梅原 雅人, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 115 348 73 - 76 2015年12月 [査読無し][通常論文]
  • 今井 誠二郎, カサウカ ダブィソ, 今川 隆司, 筒井 弘, 奥畑 宏之, 宮永 喜一
    電子情報通信学会 信学技報 115 348 57 - 60 2015年12月 [査読無し][通常論文]
  • 鴻上 慎吾, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 115 348 95 - 98 電子情報通信学会 2015年12月 [査読無し][通常論文]
  • 青木 皓, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 115 348 53 - 56 2015年12月 [査読無し][通常論文]
  • 上坂 浩貴, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 115 348 89 - 94 2015年12月 [査読無し][通常論文]
  • A Power Allocation Method in OFDMA System
    Wenheng Zhang, Alia Asheralieva, Gengfa Fang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Joint Conference of Electrical, Electronics and Information Engineers in Hokkaido 2015年11月 [査読無し][通常論文]
  • MIMO-OFDMにおける高精度シンボルタイミング検出法の実測値を用いた評価
    岩田 祐之, 今川 隆司, 筒井 弘, 宮永 喜一
    電気・情報関係学会北海道支部連合大会 2015年11月 [査読無し][通常論文]
  • 森山 慎也, 森永 孝介, 今川 隆司, 筒井 弘, 宮永 喜一, 三浦 真樹, 後藤 透, 山野 純嗣
    電子情報通信学会 信学技報 115 208 31 - 36 2015年09月 [査読無し][通常論文]
  • グローバルモーション推定と背景差分法による動領域検出における縮小画像を用いた計算量削減
    鴻上 慎吾, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会ソサイエティ大会 143  2015年09月 [査読無し][通常論文]
  • 繰り返し縮小画像平滑化を用いた画像補正の計算量削減
    今井 誠二郎, カサウカ ダブィソ, 今川 隆司, 筒井 弘, 奥畑 宏之, 宮永 喜一
    電子情報通信学会ソサイエティ大会 144  2015年09月 [査読無し][通常論文]
  • 複数解像度・複数フレームレート動画像によるグローバルモーションを用いたフレーム補間手法の性能評価
    上坂 浩貴, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会ソサイエティ大会 145  2015年09月 [査読無し][通常論文]
  • 複数のカメラを用いた3次元再構成の効率化に向けた一評価
    青木 皓, 今川 隆司, 筒井 弘, 宮永 喜一
    電子情報通信学会ソサイエティ大会 147  2015年09月 [査読無し][通常論文]
  • A Feasibility Study of a Flexible OFDM Transmitter Towards an Adaptive Control of Communication Quality
    Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 77 - 79 2015年09月 [査読有り][通常論文]
  • Carrier and Sampling Frequency Offset Compensation in 8×8 MIMO-OFDM Systems and its Performance Evaluation Using Measured Data
    Shinya Moriyama, Kosuke Morinaga, Takashi Imagawa, Hiroshi Tsutsui, Yoshikazu Miyanaga, Masaki Miura, Tohru Gotoh, Junji Yamano
    Proceedings of International Symposium on Multimedia and Communication Technology (ISMAC) 73 - 76 2015年09月 [査読有り][通常論文]
  • 画像処理装置、画像処理方法及び画像処理用プログラム
    筒井 弘, 上坂 浩貴, 鴻上 慎吾
    2015年8月21日 特願2015-163487 2015年08月 [査読無し][通常論文]
  • Takashi Sato, Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi
    PROCEEDINGS OF THE FIFTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2014) 428 - + 2015年 [査読有り][通常論文]
     
    Sub- and near-threshold circuits have been attracting growing interests because they are suitable for realizing extremely low power and low energy circuits. The estimation of the minimum operating voltage (V-DDmin), under which the circuit does not function correctly, is one of the most important issues in their design. In this paper, the distribution of V-DDmin is explored through simulations and measurements. Lognormal model-approximation and a quick V-DDmin estimation method are validated by the measurements of 124k FFs. Assuming that the V-DDmin of a circuit is limited by that of the FFs, V-DDmin distribution for any circuits can be efficiently estimated. The measurements of 192 DCT circuits show that the estimation matches with silicon data very well within 10mV error.
  • Dabwitso Kasauka, Hiroshi Tsutsui, Hiroyuki Okuhata, Takashi Imagawa, Yoshikazu Miyanaga
    2015 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) 779 - 783 2015年 [査読有り][通常論文]
     
    In recent years, much research interest has developed in image smoothing techniques. With increasing application in various fields, there is a motivation to explore various modes of algorithm implementation of image smoothing. Recently, edge-aware image smoothing techniques have been developed based on fast Fourier transformation methods. In this paper, we present an alternative implementation for an existing image smoothing algorithm using spatial iterative methods. The motivation of this is to create a performance baseline using spatial iterative methods such as multigrid (MG), conjugate gradient (CG), and preconditioned conjugate gradient (PCG) methods, for the purpose that the algorithm can be easily adapted to parallel computing systems. We also determine the competitiveness compared with FFT implementation in terms of computational cost. From experimental results, multigrid preconditioned conjugate gradient (MGCG) method provides superior results both in smoothing quality and computational cost compared to all the spatial iterative methods considered. Furthermore, with relaxed tolerance, it demonstrates lower computational complexity compared with FFT implementation, with similar smoothing results but having minor quality compromise. Hence, MGCG provides a relatively competitive spatial domain alternative to frequency domain solver, FFT. In applications which do not require computation of an exact solution, spatial iterative methods can provide a reasonable computation alternative to FFT implementation as their convergence conditions can easily be altered by the user to fit a specific application, as well as possessing the ease for parallel computing adaptation.
  • Federico Ang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2015 INTERNATIONAL SYMPOSIUM ON SIGNALS, CIRCUITS AND SYSTEMS (ISSCS) 1 - 4 2015年 [査読有り][通常論文]
     
    Current state-of-the-art automatic, continuous speech recognition systems have enjoyed huge leaps in accuracy using speech features that assumes stationarity in the signals that are being processed. However, the said performance can often be attributed to the inclusion of lexical information. For the case of isolated word tasks, without the use of a priori models for the expected words, the static speech representation breaks down. For example, words that only differ in one unvoiced part are often misrecognized. Thus, time-varying speech representations has become an interest in the field. This paper is concerned with the use of simple time-varying features based on an autoregressive modeling of speech that provides high resolution features. In particular, how the said high resolution features fit into a finite-length Hidden Markov Model-based acoustic model that was originally used for static features. Its performance is compared with the best performing static features (Mel-Frequency Cepstral Coefficients) and while it is currently viewed as suboptimal, ample rooms for improvement are also emphasized.
  • Federico Ang, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP) 302 - 306 2015年 [査読有り][通常論文]
     
    Isolated word speech recognition for small vocabulary tasks has found great success with Mel-frequency cepstral coefficients as the speech feature of choice. Voice-controlled embedded systems, using word models as the basic units of speech, have found their way in a variety of commercial products. While the recognition rates for these products can be considered commercially acceptable under clean environments, channel noise and other external factors can still degrade recognition performance in practice. We propose the use of cepstral features derived from time-varying linear predictive coding, where the autoregressive model of the speech signal is represented by coefficients that are linear combinations of some simple basis functions. Variations in the usage of the features are investigated, such as skipping adjacent features, averaging and hybrid features with the goal of improving the performance of a 142 vocabulary, isolated words Japanese speech recognition task.
  • Takahiro Inatsuki, Masato Matsuura, Kosuke Morinaga, Hiroshi Tsutsui, Yoshikazu Miyanaga
    2015 IEEE INTERNATIONAL CONFERENCE ON DIGITAL SIGNAL PROCESSING (DSP) 1062 - 1066 2015年 [査読有り][通常論文]
     
    In this paper, we present an FPGA implementation of low-latency video transmission system. The proposed system is capable of lossless video transmission using line-based compression. Assuming transmission over wireless communication channel where the data throughput dynamically changes, our system supports lossless to near-lossless scalable compression. According to the FPGA implementation result, we confirmed that our system can archive 45% of data reduction in average and can be implemented using 14,777 slice LUTs and 4,343 slice registers.
  • An Approach of Doppler-Tolerant Channel Estimation Using RLS Algorithm for MIMO-OFDM Systems
    Masahito Umehara, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 197 - 202 2014年10月 [査読有り][通常論文]
  • 梅原 雅人, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 114 126(SIS) 135 - 140 一般社団法人電子情報通信学会 2014年07月 [査読無し][通常論文]
     
    マルチパス環境下でのドップラーシフトによる周波数ずれは,受信精度を著しく低下させる.本稿では, MIMO-OFDMシステムのMIMO検出部に対して,適応アルゴリズムの1つであるRLSアルゴリズムを導入し,ドップラー耐性を有するチャネル推定法を提案する.また,送信フレームのプリアンブル構成にも着目し,拡張HT-LTFを用いることでチャネル推定精度の向上を実現する.
  • IDMA屋外伝送実験における受信ダイバーシチ効果
    吉澤 真吾, 畑川 養幸, 小西 聡, 引山 裕貴, 岩泉 洋紀, 筒井 弘, 宮永 喜一
    電子情報通信学会総合大会 441  2014年03月 [査読無し][通常論文]
  • 屋外伝送実験によるIDMA方式の特性評価
    引山 裕貴, 岩泉 洋紀, 吉澤 真吾, 畑川 養幸, 小西 聡, 筒井 弘, 宮永 喜一
    電子情報通信学会総合大会 440  2014年03月 [査読無し][通常論文]
  • IDMA屋外伝送実験の概要
    畑川 養幸, 小西 聡, 吉澤 真吾, 岩泉 洋紀, 引山 裕貴, 筒井 弘, 宮永 喜一
    電子情報通信学会総合大会 439  2014年03月 [査読無し][通常論文]
  • Dabwitso Kasauka, Hiroshi Tsutsui, Hiroyuki Okuhata, Yoshikazu Miyanaga
    2014 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA) 1 - 4 2014年 [査読有り][通常論文]
     
    In this paper, we present a computational cost analysis result of accelerated iterative shrinkage smoothing algorithm, which is one of promising image smoothing algorithms with sufficient smoothing quality results and reduced processing time. The main motivation of this cost analysis is to provide a base for efficient hardware implementation. We implemented it in a lower level programming language with OpenCV library as opposed to the MATLAB implementation. The resolution dependency of the processing time is also illustrated.
  • Hiroki Iwaizumi, Masahiro Sugitani, Baiko Sai, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Communications, Control, and Signal Processing (ISCCSP) 586 - 589 2014年 [査読有り][通常論文]
     
    In this paper. we propose a new hardware design of 8 x 8 multiple-input multiple-output - orthogonal frequency division multiplexing (MIMO-OFDM) system which has floating-point data processors in its receiver. For the hardware design of MIMO-OFDM systems, it is efficient to use fixed-point data processing in terms of high speed processing time and low power consumption. However, tinder some of poor wireless communication environments, a floating-point data processing is required because of the accurate calculation for the MIMO decoding. In this report. high accuracy and real-time processing of MIMO decoding are realized by using an application specific instruction-set processor (ASIP). The performance of the proposed system is also evaluated and explored in this report.
  • 杉谷 将宏, 岩泉 洋紀, 斉 培恒, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 113 343 41 - 46 一般社団法人電子情報通信学会 2013年12月 [査読無し][通常論文]
     
    近年,高精細動画伝送システムの需要が高まっており,8×8 MIMO-OFDMシステムは高速・大容量通信を実現する通信方式として実用化の必要性が高まっている.本稿では,8×8 MIMO-OFDMシステムの設計を行い,性能評価を行った結果について述べる.本研究では,受信機で干渉分離を行うMIMO検出処理の一部において逆行列演算の演算量が少ないストラッセンのアルゴリズムを用い,MMSEウェイト行列計算部においてすべての演算を9つのステップに分割して回路規模の削減を実現する9ステップ型のMIMO検出器を用いる.
  • 岩泉 洋紀, 杉谷 将宏, 斉 培恒, 筒井 弘, 宮永 喜一
    電子情報通信学会 信学技報 113 343 35 - 40 一般社団法人電子情報通信学会 2013年12月 [査読無し][通常論文]
     
    本稿では,受信機に浮動小数点演算プロセッサを組み込んだ高精度8×8MIMO-OFDMシステムのハードウェア設計を提案する.MIMO-OFDMシステムのハードウェア設計において,固定小数点演算を用いた設計は有効であるが,悪環境下でのMIMO復号処理には高い精度が求められるため,システムの性能向上のためには浮動小数点演算を用いた処理が必要となる.本研究では,汎用性及び処理効率に優れたASIPを採用しアルゴリズムの効率化を行うことで,MIMO復号処理の高精度化及び実時間処理を実現している.
  • Yuya Inoue, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Intelligent Signal Processing and Communication Systems (ISPACS) 363 - 368 2013年11月 [査読有り][通常論文]
     
    This paper presents a study of peak-to-average power ratio (PAPR) reduction using coded partial transmit sequence (PTS) in 88 multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems. MIMO-OFDM achieves large-capacity wireless communication, and has been adopted in such as IEEE802.11n/ac standard wireless LAN systems. PAPR indicates the ratio of peak power to average power. High PAPR causes waveform distortion due to nonlinear amplifier characteristics. PTS is one of PAPR reduction methods to prevent communication quality degradation. PTS performs phase rotation to OFDM modulated signals to reduce the peak power. We have to increase the number of possible phase patterns in order to obtain enough PAPR reduction. Coded PTS is used to reduce computational cost of PTS by using codebook. In the case of MIMO-OFDM systems, we have to use the same phase pattern of PTS for each stream due to difficulty of detection. In this paper, we have evaluated PAPR reduction by the proposed coded PTS in 8x8 MIMO-OFDM systems. The evaluation result shows that low error transmission can be achieved by using coded PTS and RS code, and PAPR reduction is about 1.7dB. In comparison with PTS, coded PTS can achieve 94% computational cost reduction. © 2013 IEEE.
  • Place-and-Route Algorithms for a Reliability-Oriented Coarse-Grained Reconfigurable Architecture Using Time Redundancy
    Takashi Imagawa, Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of the 18th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2013) 76 - 81 2013年10月 [査読有り][通常論文]
  • An Evaluation of Channel Estimation Using RLS Algorithm in MIMO-OFDM Systems
    Masahito Umehara, Baiko Sai, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 145 - 150 2013年10月 [査読有り][通常論文]
  • Kosuke Morinaga, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Communications and Information Technologies (ISCIT) 685 - 690 2013年09月 [査読有り][通常論文]
     
    In recent years, digital high-definition television is widely used due to the start of digital terrestrial television broadcasting. In addition to such situation, ultra high definition television format such as 4K and 8K has been standardized. On the other hand, high-speed wireless transmission systems using MIMO-OFDM including IEEE 802.11n and 802.11ac wireless LAN standards have become popular. Using such high-speed transmission systems, it is expected that high-definition video sequences can be transmitted without any degradation of quality. Therefore, we are trying to develop such high-quality video transmission systems over a wireless environment by combining lossless video compression algorithms and MIMO-OFDM wireless transmission technology considering both hardware implementation and wireless transmission conditions. In this paper, we evaluate a configuration of lossless video transmission systems. Experimental result shows that video sequences can be transmitted over 22db carrier to noise ratio (CNR) wireless channels with 99.99% pixel restoration rate. © 2013 IEEE.
  • Yuki Hikiyama, Hiroshi Tsutsui, Yoshikazu Miyanaga
    13th International Symposium on Communications and Information Technologies: Communication and Information Technology for New Life Style Beyond the Cloud, ISCIT 2013 674 - 679 2013年09月 [査読有り][通常論文]
     
    Recently, multiple-input multiple-output (MIMO) technologies are adopted to wireless communication systems for high-speed, large capacity and high reliability communications. However, there can be variations of communication quality and throughput performance, because MIMO technologies depend on propagation channel environments, where communication property widely changes. An optimal wireless communication systems design which adaptively changes transmission systems depending on channel propagation is effective to realize stable wireless communications therefore, it is important that a transceiver knows propagation environment accurately. In this paper, we propose a new discrimination method for MIMO propagation scenarios by using channel state information (CSI), where azimuth spread (AS) and K-Factor estimation are considered. In addition, we evaluate discrimination performance by simulation, and then we get a discrimination result of high accuracy. © 2013 IEEE.
  • Masumi Watanabe, Hiroshi Tsutsui, Yoshikazu Miyanaga
    13th International Symposium on Communications and Information Technologies: Communication and Information Technology for New Life Style Beyond the Cloud, ISCIT 2013 802 - 807 2013年09月 [査読有り][通常論文]
     
    In this paper, we propose a robust speech recognition method for similar pronunciation phrases. Along with the popularization of information devices such as personal computers and smart-phones, many applications controlled by voice have spread in the society. In order to increase the speech accuracy under a real environment, it is extremely important to discriminate similar pronunciation phrases. In the proposed method, linear prediction theory (LPC) is used for spectral analysis while cepstrum mean subtraction (CMS) and dynamic range adjustment (DRA) is used for a noise reduction method. The speech accuracy was recorded 68.7 % in SNR 10 dB by using the proposed methods. In conclusion, LPC+CMS/DRA is the most effective method to discriminate similar pronunciation phrases. © 2013 IEEE.
  • Masato Matsuura, Hiroshi Tsutsui, Yoshikazu Miyanaga
    Proceedings of International Symposium on Communications and Information Technologies (ISCIT) 797 - 801 2013年09月 [査読有り][通常論文]
     
    Recently, video quality on TV programs and the Internet has become dramatically high. In this situation, demand for sharing high quality video sequences without wiring is increasing. Considering the bit rate of wireless channels, we should use lossy compression to transmit video sequences. However, this approach is not always ideal in terms of video quality. Therefore, our group is trying to develop a system of wireless transmission and lossless video compression. In this paper, we evaluated the system in computer simulation. As for the compression part, we confirmed that the combination of hierarchical average and copy prediction (HACP) algorithm and Huffman coding has good compression performance and suitable for hardware implementation. As for the transmission part, we adopted 8×8 MIMO-OFDM, which is employed in IEEE802.11ac, because this system can transmit data of about 1Gbps or more. Considering noise by transmission errors, we propose a packet construction method to reduce noise. In the evaluation, we explore conditions of wireless systems where noise does not appear and stable image is obtained by simulating. The experimental results show that stable transmission can be achieved in case of 18 dB CNR, 16QAM moduration, and 1/2 coding rate. © 2013 IEEE.
  • 藤田 隆史, 川島 潤也, 廣本 正之, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会 信学技報 113 112 129 - 134 電子情報通信学会 2013年07月 [査読無し][通常論文]
  • 岡崎 剛, 筒井 弘, 越智 裕之, 佐藤 高史
    第26回 回路とシステムワークショップ 26 472 - 477 [電子情報通信学会] 2013年07月 [査読有り][通常論文]
  • 藤田 隆史, 筒井 弘, 越智 裕之, 佐藤 高史
    第26回 回路とシステムワークショップ 26 397 - 402 [電子情報通信学会] 2013年07月 [査読有り][通常論文]
  • 木村 和紀, 筒井 弘, 越智 裕之, 佐藤 高史
    第26回 回路とシステムワークショップ 26 374 - 379 [電子情報通信学会] 2013年07月 [査読有り][通常論文]
  • 筒井 弘
    電子情報通信学会 信学技報 113 78 47 - 52 一般社団法人電子情報通信学会 2013年06月 [査読無し][通常論文]
     
    近年,デジタルビデオカメラやスマートフォンといったデジタル撮像デバイスの普及により,画像処理の需要がますます高まっている.一般に動画像データは単位時間あたりのデータ量が大きいため,動画像に対する画像処理は,リアルタイム性が要求される場合,ソフトウェアではなくハードウェアにより実現されることが多い.そこで本稿では,適応的階調補正IPの開発を例に,画像処理ハードウェアIPの設計を概観する.
  • Histogram Propagation Based Statistical Timing Analysis Using Dependent Node Selection
    Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 321 - 324 2013年06月 [査読有り][通常論文]
  • Architecture for Sealed Wafer-scale Mask ROM for Long-term Digital Data Preservation
    Shinya Matsuda, Takashi Imagawa, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
    The 28th International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC) 274 - 277 2013年06月 [査読有り][通常論文]
  • Takumi Morishita, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 95 - 100 2013年05月 [査読有り][通常論文]
     
    Power grid analysis for modern LSI is computationally challenging in terms of both runtime and memory usage. In this paper, we implement Krylov subspace based linear circuit solvers on a graphics processing unit (GPU) to realize fast power grid analysis. Efficiencies of memory space and access performance are pursued by improving a data structure that stores elements of large sparse matrices. Experimental results on benchmark circuits show that the proposed data structures are more suitable than widely used compressed sparse row (CSR) format and our GPU implementations can achieve up to 17x speedup over CPU implementations. © 2013 ACM.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON ELECTRONICS E96C 4 454 - 462 2013年04月 [査読有り][通常論文]
     
    This paper proposes a novel method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of application circuits onto coarse-grained reconfigurable architectures (CGRAs). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the node parameters which characterize impact of the SEU in the node on the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.
  • Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON ELECTRONICS E96C 4 473 - 481 2013年04月 [査読有り][通常論文]
     
    We propose a novel acceleration scheme for Monte Carlo based statistical static timing analysis (MC-SSTA). MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference. A large number of random samples, however, should be processed to obtain accurate delay distributions, and software implementation of MC-SSTA, therefore, takes an impractically long processing time. In our approach, a generalized hardware module, the STA processing element (STA-PE), is used for the delay evaluation of a logic gate, and netlist-specific information is delivered in the form of instructions from an SRAM. Multiple STA-PEs can be implemented for parallel processing, while a larger netlist can be handled if only a larger SRAM area is available. The proposed scheme is successfully implemented on Altera's Arria II GX EP2AGX125EF35C4 device in which 26 STA-PEs and a 624-port Mersenne Twister-based random number generator run in parallel at a 116 MHz clock rate. A speedup of far more than x10 is achieved compared to conventional methods including GPU implementation.
  • 藤田 隆史, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会総合大会 エレクトロニクス講演論文集2 2013 78  2013年03月 [査読無し][通常論文]
  • Evaluation of Dependent Node Selection of Histogram Propagation Based Statistical Timing Analysis
    Shiyi Zhang, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the 2013 IEICE general conference, Fundamentals on Electronics, Communications and Computer Sciences 62  2013年03月 [査読無し][通常論文]
  • 岡崎 剛, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会総合大会 基礎・境界講演論文集 2013 61  2013年03月 [査読無し][通常論文]
  • Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) 597 - 602 2013年03月 [査読有り][通常論文]
     
    This paper presents a new analysis method for estimating the statistical parameters of random telegraph noise (RTN). RTN is characterized by the time constants of carrier capture and emission, and associated changes of threshold voltage. Because trap activities are projected on to the threshold voltage, the separation of time constants and amplitude for each trap is an ill-posed problem. The proposed method solves this problem by statistical method that can reflect the physical generation process of RTN. By using Gibbs sampling algorithm developed in statistical machine learning community, we decompose the measured threshold voltage sequence to time constants and amplitude of each trap. We also demonstrate that the proposed method estimates time constants about 2.1 times more accurately than the existing work that uses hidden Markov model, which contributes to enhance the accuracy of reliability-aware circuit simulation.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    PROCEEDINGS OF THE FOURTEENTH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED 2013) 538 - 545 2013年 [査読有り][通常論文]
     
    In this paper, we investigate a method to achieve cost-effective selective triple modular redundancy (selective TMR) against single event upset (SEU). This method enables us to minimize the vulnerability of the target application circuit implemented on a resource-constrained coarse-grained reconfigurable architecture (CGRA). The key of the proposed method is the evaluation function to determine the vulnerable node in the data flow graph (DFG) of the target application. Since the influence of the fault in a node to the primary outputs depends on its fains and fanouts as well as the node itself, this paper proposes an enhanced evaluation function that reflects the operation of fanins/fanouts of a node. This paper also improves the method to derive weight vector which is used in the evaluation function, by assuming exponential distribution instead of linear distribution for the vulnerability of nodes. To derive a generic weight vector, we propose to solve a concatenated linear equations obtained from multiple sample applications, instead of averaging the weight vectors for applications. Using generalized inverse matrix to solve the equation, the proposed method takes less than ten seconds to extract a reasonable priority for selective TMR, which is extremely faster than the exhaustive exploration for the optimal solution that takes more than 15 hours. This paper also compares the contributions of the features use in the evaluation function, which would be insightful for designing reliability-aware CGRA architecture and synthesis tools.
  • Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    DESIGN, AUTOMATION & TEST IN EUROPE 701 - 706 2013年 [査読有り][通常論文]
     
    This paper proposes a method to determine a priority for applying selective triple modular redundancy (selective TMR) against single event upset (SEU) to achieve cost-effective reliable implementation of an application circuit to a coarse-grained reconfigurable architecture (CGRA). The priority is determined by an estimation of the vulnerability of each node in the data flow graph (DFG) of the application circuit. The estimation is based on a weighted sum of the features and parameters of each node in the DFG which characterize impact of the SEU in the node to the output data. This method does not require time-consuming placement-and-routing processes, as well as extensive fault simulations for various triplicating patterns, which allows us to identify the set of nodes to be triplicated for minimizing the vulnerability under given area constraint at the early stage of design flow. Therefore, the proposed method enables us efficient design space exploration of reliability-oriented CGRAs and their applications.
  • Zoltan Endre Rakossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi
    DESIGN, AUTOMATION & TEST IN EUROPE 535 - 540 2013年 [査読有り][通常論文]
     
    Due to latest advances in semiconductor integration, systems are becoming more susceptible to faults leading to temporary or permanent failures. We propose a new architecture extension suitable for arrays of functional units (FUs), that will provide testing and replacement of faulty units, without interrupting normal system operation. The extension relies on data-path switching realized by the proposed hot-swapping algorithm and structures, by use of which functional units are tested and replaced by spares, at lower overheads than traditional modular redundancy. For a case study architecture, hot-swapping support could be added with only 29% area overhead. In this paper we focus on experimental evaluation of the hot-swapping system from a fabricated chip in 65nm CMOS process. Autonomous testing of the hot-swapping system is enhanced with back-bias circuitry to attain an early fault detection and restoration system. Experimental measurements prove that the proposed concept works well, predicting fault occurrence with a configurable prediction interval, while power measurements reveal that with only 20% power overhead the proposed system can attain reliability levels similar to triple modular redundancy. Additionally, measurements reveal that manufacturing randomness across the die can significantly influence identical sub-circuit reliability located in different parts in the die, although identical layout has been employed.
  • Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the Asia and South Pacific Design Automation Conference, ASP-DAC 169 - 174 2013年01月 [査読有り][通常論文]
     
    This paper presents the realization of frequency-domain circuit analysis based on random walk framework for the first time. In conventional random walk based circuit analyses, the sample movement at a node is randomly chosen to follow the edge probabilities. The probabilities are determined by edge-admittances connecting to the node, which is impossible to apply for the frequency-domain analysis because the probabilities are imaginary numbers. By applying the idea of importance sampling, the intractable imaginary probabilities are converted into real numbers while maintaining the estimation correctness. Runtime acceleration through incremental analysis is also proposed. © 2013 IEEE.
  • Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A 12 2272 - 2283 2012年12月 [査読有り][通常論文]
     
    Random telegraph noise (RTN) is a phenomenon that is considered to limit the reliability and performance of circuits using advanced devices. The time constants of carrier capture and emission and the associated change in the threshold voltage are important parameters commonly included in various models, but their extraction from time-domain observations has been a difficult task. In this study, we propose a statistical method for simultaneously estimating interrelated parameters: the time constants and magnitude of the threshold voltage shift. Our method is based on a graphical network representation, and the parameters are estimated using the Markov chain Monte Carlo method. Experimental application of the proposed method to synthetic and measured time-domain RTN signals was successful. The proposed method can handle interrelated parameters of multiple traps and thereby contributes to the construction of more accurate RTN models.
  • Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E95A 12 2242 - 2250 2012年12月 [査読有り][通常論文]
     
    We investigate a design strategy for subthreshold circuits focusing on energy-consumption minimization and yield maximization under process variations. The design strategy is based on the following findings related to the operation of low-power CMOS circuits: (1) The minimum operation voltage (V-DDmin) of a circuit is dominated by flip-flops (FFs), and V-DDmin of an FF can be improved by upsizing a few key transistors, (2) V-DDmin of an FF is stochastically modeled by a log-normal distribution, (3) V-DDmin of a large circuit can be efficiently estimated by using the above model, which eliminates extensive Monte Carlo simulations, and (4) improving V-DDmin may substantially contribute to decreasing energy consumption. The effectiveness of the proposed design strategy has been verified through circuit simulations on various circuits, which clearly show the design tradeoff between voltage scaling and transistor sizing.
  • Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    電子情報通信学会技術研究報告 112 320 117 - 122 一般社団法人電子情報通信学会 2012年11月 [査読無し][通常論文]
     
    With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65 nm CMOS technology. The proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.
  • 清水 裕史, 粟野 皓光, 筒井 弘, 越智 裕之, 佐藤 高史
    情報処理学会DAシンポジウム論文集 2012 5 49 - 54 2012年08月 [査読有り][通常論文]
  • 森下 拓海, 筒井 弘, 越智 裕之, 佐藤 高史
    第25回 回路とシステムワークショップ 25 432 - 437 [電子情報通信学会] 2012年07月 [査読有り][通常論文]
  • 回路の最小動作電圧改善とその予測精度向上の一検討
    川島 潤也, 越智 裕之, 筒井 弘, 佐藤 高史
    第25回 回路とシステムワークショップ 313 - 318 2012年07月 [査読有り][通常論文]
  • 前野 達生, 筒井 弘, 尾上 孝雄
    電子情報通信学会技術研究報告 112 78 77 - 82 2012年06月 [査読無し][通常論文]
  • GPU Acceleration of Cycle-based Soft-Error Simulation for Reconfigurable Array Architectures
    Takashi Imagawa, Takahiro Oue, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2012) 88 - 93 2012年03月 [査読有り][通常論文]
  • Hardware Architecture for Accelerating Monte Carlo based SSTA using Generalized STA Processing Element
    Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of the 17th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2012) 205 - 210 2012年03月 [査読有り][通常論文]
  • Acceleration Scheme for Monte Carlo based SSTA using Generalized STA Processing Element
    Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of ACM/IEEE International Workshop on Timing Issues (TAU) 2012年01月 [査読有り][通常論文]
  • Hiroshi Tsutsui, Koichi Hattori, Hiroyuki Ochi, Yukihiro Nakamura
    ACM TRANSACTIONS ON EMBEDDED COMPUTING SYSTEMS 11 4 1 - 25 2012年 [査読有り][通常論文]
     
    JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft Corporation. It supports high compression performance twice as high as the de facto image coding system, namely, JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this article, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. In addition, each module of our architecture, which can be regarded as a pipeline stage, can be parallelized. As a result, our architecture can achieve 12.8 pixel/cycle at its maximum. To demonstrate our architecture, we designed three versions of our architecture with different degrees of parallelism of one, two, and four. Our four-way parallel architecture achieves 579 Mpixel/sec at 181MHz clock frequency for grayscale images.
  • Hiroshi Tsutsui, Satoshi Yoshikawa, Hiroyuki Okuhata, Takao Onoye
    2012 ASIA-PACIFIC SIGNAL AND INFORMATION PROCESSING ASSOCIATION ANNUAL SUMMIT AND CONFERENCE (APSIPA ASC) 2012年 [査読有り][通常論文]
     
    In this paper, we propose a novel halo reduction method for variational based Retinex image enhancement. In variational based Retinex image enhancement, a cost function is designed based on the illumination characteristics. The enhanced image is obtained by extracting the illumination component, which gives minimum cost, from the given input image. Although this approach gives good enhancement quality with less computational cost, a problem that dark regions near edges remain dark after image enhancement, known as halo artifact, still exists. In order to suppress such artifacts effectively, the proposed method adaptively adjusts the parameter of the cost function, which influences the trade-off relation between reducing halo artifacts and preserving image contrast. The proposed method is applicable to an existing realtime Retinex image enhancement hardware implementation.
  • Takashi Sato, Hiromitsu Awano, Hirofumi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi
    2012 13TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) 306 - 311 2012年 [査読有り][通常論文]
     
    Performance variability of miniaturized devices has become a major obstacle for designing electronic systems. Temporal degradation of threshold voltages and its variation are going to be an additional concerns to ensure their reliability. In this paper, based on measurement results on large number of devices, we present statistical properties of device degradation and recovery. The measurement data is obtained by using a device-array circuit suitable for efficiently collect statistical data on degradations and recoveries of very small channel-area devices. Stair-like change of threshold voltages found in our measurement suggests that charge trapping and emission may play a key role in the device degradation process.
  • 森下 拓海, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会技術研究報告 111 324 67 - 71 2011年11月 [査読無し][通常論文]
  • 粟野 皓光, 清水 裕史, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会技術研究報告 111 324 85 - 90 2011年11月 [査読無し][通常論文]
  • 宮川 哲朗, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会技術研究報告 111 324 73 - 78 2011年11月 [査読無し][通常論文]
  • 清水 裕史, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会ソサイエティ大会 2011 93  2011年09月 [査読無し][通常論文]
  • Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proc. of IEICE Society Conference 120 120 - 120 一般社団法人電子情報通信学会 2011年09月 [査読無し][通常論文]
  • 森下 拓海, 筒井 弘, 越智 裕之, 佐藤 高史
    電子情報通信学会ソサイエティ大会 2011 84  2011年09月 [査読無し][通常論文]
  • Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi
    European Solid-State Device Research Conference 143 - 146 2011年09月 [査読有り][通常論文]
     
    A device array suitable for efficiently collecting statistical information on bias-temperature instability (BTI) parameters of a large number of transistors is presented. The proposed array structure substantially shortens measurement time of threshold voltage shifts under BTI conditions by parallelizing stress periods of multiple devices while maintaining 0.2mV precision. An implementation of BTI array consisting of 128 devices successfully validates stress-pipelining concept. Log-normal distributions of time exponents are experimentally observed. © 2011 IEEE.
  • 片山 健太朗, 筒井 弘, 越智 裕之, 佐藤 高史
    情報処理学会DAシンポジウム論文集 2011 5 93 - 98 2011年08月 [査読有り][通常論文]
  • 今川 隆司, 湯浅 洋史, 筒井 弘, 越智 裕之, 佐藤 高史
    情報処理学会DAシンポジウム論文集 2011 5 111 - 116 2011年08月 [査読有り][通常論文]
  • 前野 達生, 筒井 弘, 尾上 孝雄
    電子情報通信学会技術研究報告 111 78 99 - 104 2011年06月 [査読無し][通常論文]
  • 吉川 哲史, 筒井 弘, 奥畑 宏之, 尾上 孝雄
    電子情報通信学会技術研究報告 111 78 93 - 98 一般社団法人電子情報通信学会 2011年06月 [査読無し][通常論文]
     
    Retinex理論を利用した適応的階調補正では,入力画像に含まれる照明光成分を推定し,その成分を入力画像から除去することにより階調補正を実現する.本稿では,照明光に対してコストを定義し,そのコスト最小化問題を変分法で解くことで照明光成分を推定する手法を対象とする.この手法では,暗い領域に隣接する明るい領域が過剰に明るく補正される一般的なハロー効果は発生しないが,その一方で,明るい領域に隣接する暗い領域の補正が弱いため暗いまま残るという現象が生じる.この現象を本稿では逆ハロー効果と呼ぶ.本稿では,逆ハロー効果が顕著に現われやすい領域でそれを抑制するような照明光成分を推定するため,輝度値およびエッジ成分の大きさに応じてコスト関数のパラメータを適応的に変更する手法を提案する.
  • A stress-parallelized device array for efficient bias-temperature stability measurement
    Takashi Sato, Tadamichi Kozaki, Takumi Uezono, Hiroshi Tsutsui, Hiroyuki Ochi
    Proc. of IEEE International Workshop on Design for Manufacturability and Yield 2011 (DFM&Y) 19 - 22 2011年06月 [査読有り][通常論文]
  • Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    Proceedings of the ACM Great Lakes Symposium on VLSI, GLSVLSI 211 - 216 2011年05月 [査読有り][通常論文]
     
    This paper proposes an importance sampling (IS) technique based on quasi-zero-variance estimation for accelerating convergence of random-walk-based power grid analysis. In our approach, the alternative probability for IS is incrementally updated after every Mr samples of random walk so that more recent and thus more accurate node voltages are utilized to asymptotically achieve ideal zero-variance estimation. We also propose a method to determine efficient Mr for the r-th probability update although smaller M r results more aggressive update of alternative probability, the alternative probability becomes inaccurate if Mr is too small. The estimation error of the proposed method decreases O((M/r)-r/2), which breaks O(M-1/2), the slow convergence-rate barrier of normal Monte Carlo analysis. Our trial implementation achieved 790x speedup compared with a conventional random-walk-based circuit analysis for analyzing IBM power grid benchmark circuits at 1mV accuracy. Copyright © 2011 by ASME.
  • Hardware Implementation of Real-time Motion Adaptive Deinterlacing based on Inpainting
    Tatsuo Maeno, Hiroshi Tsutsui, Takao Onoye
    Proceedings of International Conference on Embedded Systems and Intelligent Technology (ICESIT) 2011年02月 [査読有り][通常論文]
  • Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato
    2011 IEEE INTERNATIONAL SOC CONFERENCE (SOCC) 57 - 62 2011年 [査読有り][通常論文]
     
    The paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (V-DDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) V-DDmin of a FF is stochastically modeled by a log-normal distribution, 3) V-DDmin of a large circuit can be estimated using the above model without extensive Monte-Carlo simulations, and 4) improving V-DDmin may substantially contribute to reduce energy consumption.
  • 川島 潤也, 越智 裕之, 筒井 弘, 佐藤 高史
    第24回 回路とシステムワークショップ 57 - 62 2011年 [査読有り][通常論文]
     
    The paper investigates a design strategy for sub-threshold circuits focusing on energy-consumption minimization and yield maximization under process variations. It is shown that 1) the minimum operation voltage (V-DDmin) of a circuit is dominated by FFs, and it can be improved by appropriate transistor sizing, 2) V-DDmin of a FF is stochastically modeled by a log-normal distribution, 3) V-DDmin of a large circuit can be estimated using the above model without extensive Monte-Carlo simulations, and 4) improving V-DDmin may substantially contribute to reduce energy consumption.
  • Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    2011 12TH INTERNATIONAL SYMPOSIUM ON QUALITY ELECTRONIC DESIGN (ISQED) 785 - 790 2011年 [査読有り][通常論文]
     
    We propose an efficient implementation of Monte Carlo based statistical static timing analysis (MC-SSTA) on FPGAs. MC-SSTA, which repeatedly executes ordinary STA using a set of randomly generated gate delay samples, is widely accepted as an accuracy reference because of its ability to handle any timing distributions and correlations. Extremely long CPU time has been required for the MC-SSTA, which prevented it from adopting as a mainstream timing analyzer. Motivated by its inherent parallelism, we propose a hardware acceleration of MC-SSTA. In our approach, timing graph of a target netlist will be translated into an RTL description that can be mapped into an FPGA as a dedicated STA engine. Each delay arc is realized as the random delay generator of specified parameters with a register, which explores full pipelining operation for the logic gates in a path. Linear feedback shift registers and normal distribution generators based on the central limit theorem are used as the random delay generator to suppress hardware resources. With our implementation, both path-and gate-level parallelisms are realized, achieving 87 times acceleration compared to a software implementation in the case of analyzing a 6 bit multiplier. The analysis accuracy comparable to the Mersenne Twister and the Box Muller methods, which are the well-known high quality normal distribution random number generator, has been also experimentally verified.
  • Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato
    2010 IEEE AND ACM INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN (ICCAD) 703 - 708 2010年11月 [査読有り][通常論文]
     
    In this paper, a significant acceleration of estimating low-failure rate in a high-dimensional SRAM yield analysis is achieved using sequential importance sampling. The proposed method systematically, autonomously, and adaptively explores failure region of interest, whereas all previous works needed to resort to brute-force search. Elimination of brute-force search and adaptive trial distribution significantly improves the efficiency of failure-rate estimation of hitherto unsolved high-dimensional cases wherein a lot of variation sources including threshold voltages, channel-length, carrier mobility, etc. are simultaneously considered. The proposed method is applicable to wide range of Monte Carlo simulation analyses dealing with high-dimensional problem of rare events. In SRAM yield estimation example, we achieved 10(6) times acceleration compared to a standard Monte Carlo simulation for a failure probability of 3 x 10(-9) in a six-dimensional problem. The example of 24-dimensional analysis on which other methods are ineffective is also presented.
  • An Approach to Motion-Compensated Frame Interpolation based on Feature Tracking
    Hideyuki Nakamura, Hiroshi Tsutsui, Takao Onoye
    Proceedings of International Workshop on Smart Info-Media Systems in Asia (SISA) 2010年09月 [査読有り][通常論文]
  • Hiroshi Tsutsui, Hideyuki Nakamura, Ryoji Hashimoto, Hiroyuki Okuhata, Takao Onoye
    Proc. of World Automation Congress (WAC), International Forum on Multimedia and Image Processing (IFMIP) 2010年09月 [査読有り][通常論文]
  • 吉川 哲史, 筒井 弘, 尾上 孝雄
    電子情報通信学会技術研究報告 110 74 93 - 98 2010年06月 [査読無し][通常論文]
  • 前野 達生, 筒井 弘, 尾上 孝雄
    電子情報通信学会技術研究報告 110 74 87 - 92 2010年06月 [査読無し][通常論文]
  • メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法
    廣本 正之, 筒井 弘, 越智 裕之, 小佐野 智之, 石川 憲洋, 中村 行宏
    情報処理学会論文誌 50 10 2532 - 2542 2009年10月 [査読有り][通常論文]
  • 中村 秀幸, 筒井 弘, 橋本 亮司, 尾上 孝雄
    電子情報通信学会ソサイエティ大会 2009 204 - 204 一般社団法人電子情報通信学会 2009年09月 [査読無し][通常論文]
  • Hiroki Sugano, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E92A 8 1970 - 1977 2009年08月 [査読有り][通常論文]
     
    The encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of the entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process the entropy encoding/decoding. This module, however, requests many small-size memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory organization framework for the entropy encoding/decoding module is proposed, in which not only existing memory organizations but also our proposed novel memory organization methods are attempted to expand the design space to be explored. As a result, the efficient memory organization for a target process technology can be explored.
  • 増崎 隆彦, 筒井 弘, 尾上 孝雄, 水野 雄介, 佐々木 元, 中村 行宏
    画像電子学会誌 38 3 296 - 304 2009年05月 [査読有り][通常論文]
     
    A system architecture of JPEG2000 codec LSI is developed, which is dedicated to high resolution digital images. When single-tile processing technique is employed in order to maintain image quality, the requirement for on-chip memory amount and I/O bandwidth becomes serious issue. A line-based DWT is devised for our system architecture, in which image data is processed by rectangle pieces. In addition, we introduce a scheme to calculate required system resources with varying image sizes, DWT levels, and use of intermediate data buffer so as to investigate an efficient system architecture. Based on the proposed system architecture, a JPEG2000 codec LSI, supporting 8,192 X 8,192 images by single-tile processing, is implemented by using 2.1 M gates, which dissipates 137.1 mW from 1.8 V (core) power supply at 27 MHz operation. © 2009, The Institute of Image Electronics Engineers of Japan. All rights reserved.
  • Masayuki Hiromoto, Hiroshi Tsutsui, Hiroyuki Ochi, Tomoyuki Osano, Norihiro Ishikawa, Yukihiro Nakamura
    IEEE Wireless Communications and Networking Conference, WCNC 2009年04月 [査読有り][通常論文]
     
    Emerging high-speed mobile networks enable us to receive media streaming data by mobile terminals on demand. However, media streaming with fixed bitrate causes some problems such as annoying artificial noise, interruption, and so forth, since link quality fluctuates dramatically in such mobile networks. Motivated by this, in this paper, we propose a novel media streaming system with dynamic rate control scheme to achieve continuous streaming on such unstable networks. The proposed rate control scheme uses the delay of the transcoding process to estimate network bandwidth, and adjusts the bitrate of media streams dynamically. To demonstrate our system and scheme, the proposed streaming system is evaluated under some typical models of bandwidth change in high-speed mobile networks. The results show that stable and high-quality streaming without interruption can be achieved by the proposed scheme. Moreover, we successfully demonstrate that our system performs continuous streaming on real mobile networks even in the severe network condition such as on a moving train. © 2009 IEEE.
  • 橋本 亮司, 筒井 弘, 尾上 孝雄, 猪飼 知宏
    電子情報通信学会技術研究報告 108 425 31 - 36 一般社団法人 映像情報メディア学会 2009年02月 [査読無し][通常論文]
     
    近年,新しい画像符号化パラダイムとして,Distributed Video Coding(DVC)が注目されている.DVCは既存のMPEG-2などと比べて,低演算量で符号化が可能である一方,符号化効率の面で実用化への課題がある.本稿では,DVCの符号化効率に影響を与える誤り訂正部において,誤り訂正部への入力ビットの尤度を推定する手法を提案する.提案手法では,周波数成分ごとに原画像と復号器で生成した予測画像の誤差の分布をコーシー分布でモデル化する.具体的には,復号済みである前後のキーフレームを用いてモデル化した後,各ビットの尤度を算出する.ソフトウェアシミュレーションで評価を行った結果,提案手法は平均誤差1.6%で誤り率を推定可能であった.
  • Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    2009 IEEE/ACM/IFIP 7TH WORKSHOP ON EMBEDDED SYSTEMS FOR REAL-TIME MULTIMEDIA 9 - + 2009年 [査読有り][通常論文]
     
    JPEG XR is an emerging image coding standard, based on HD Photo developed by Microsoft. It supports high compression performance twice as high as the de facto image coding system, namely JPEG, and also has an advantage over JPEG 2000 in terms of computational cost. JPEG XR is expected to be widespread for many devices including embedded systems in the near future. In this paper, we propose a novel architecture for JPEG XR encoding. In previous architectures, entropy coding was the throughput bottleneck because it was implemented as a sequential algorithm to handle data with dependency. We found that there is no dependency in intra-macroblock data, and we could safely pipeline all the encoding processes including the entropy coding. The proposed fully-pipelined architecture achieves 100 M pixel/sec at 125 MHz which could not be achieved by previous works.
  • メディアストリーミングにおける高速移動通信網に適した動的符号化レート制御手法の検討
    廣本 正之, 筒井 弘, 越智 裕之, 小佐野 智之, 石川 憲洋, 中村 行宏
    マルチメディア，分散，協調とモバイル(DICOMO2008)シンポジウム 1167 - 1176 2008年07月 [査読有り][通常論文]
  • 服部 幸市, 筒井 弘, 越智 裕之, 中村 行宏
    電子情報通信学会技術研究報告 108 85 39 - 44 2008年06月 [査読無し][通常論文]
  • Koichi Hattori, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    2008 IEEE ASIA PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS (APCCAS 2008), VOLS 1-4 1592 - + 2008年 [査読有り][通常論文]
     
    In this paper, we propose a novel architecture of photo core transform (PCT) which is used as transformation of image data into frequency domain in HD Photo, an emerging image coding system developed by Microsoft. In order to support various memory bus bandwidths used in system-on-a-chip (SoC) design, an implementation for each bandwidth can be derived based on our architecture. In addition, in order to reduce the local memory size and the traffic between the main and local memories, we propose a novel data transfer and storing scheme for PCT. The experimental results show that hardware modules corresponding to the given bus bandwidths can be reasonably derived from the proposed architecture.
  • 筒井 弘
    電子情報通信学会ソサイエティ大会 2007 SS.8 - SS.9 2007年09月 [査読無し][通常論文]
  • 筒井 弘, 藤田 憲正, 尾上 孝雄, 中村 行宏
    電子情報通信学会技術研究報告 107 93 13 - 18 一般社団法人電子情報通信学会 2007年06月 [査読無し][通常論文]
     
    本稿では,JPEG2000復号処理において最も演算量が必要な処理であるエントロピ復号処理に関して,1サイクルに複数シンボル処理可能なマルチシンボル算術復号器を提案する.実装及びシミュレーションの結果,1サイクルで1シンボルの復号を行う従来のものと比較し,2シンボル復号を行う場合で1.21倍,3シンボル復号を行う場合で1.28倍の高速化が達成できた.
  • 宮本 龍介, 劉 載勲, 筒井 弘, 中村 行宏
    画像電子学会誌 36 3 210 - 218 2007年05月 [査読有り][通常論文]
     
    Stereo matching, the corresponding problem of stereo vision, requires much computational cost, especially highly accurate matching algorithm needs huge computational cost. Therefore realtime systems for stereo matching based on specific processors are developed. However, there is no system which enables both highly accurate matching and real time processing. In this paper, we propose a novel processor architecture based on variable window approach, in order to develop a specific processor which achieves highly accurate matching required for realtime systems using stereo vision. A processor based on the proposed architecture implemented on Xilinx Virtex-4 FPGA achieves real-time stereo matching at 70 MHz when the resolution and the frame rate of input images are QVGA and 30 fps, respectively. © 2007, The Institute of Image Electronics Engineers of Japan. All rights reserved.
  • Ryusuke Miyamoto, Jumpei Ashida, Hiroshi Tsutsui, Yukihiro Nakamura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E90A 3 606 - 617 2007年03月 [査読有り][通常論文]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian for a state space model and distance transformed images for likelihood computation. The 6-stick skeleton model used in the proposed approach is very distinctive in representing a pedestrian simply but effectively. By the experiment using the real sequences provided by PETS, it is shown that the target pedestrian is tracked adequately by the proposed approach with a simple silhouette extraction method which consists of only background subtraction, even if the tracking target moves so complicatedly and is often so cluttered by other obstacles that the pedestrian can not be tracked by the conventional methods. Moreover, it is demonstrated that the proposed scheme can track the multiple targets in the complex case that their trajectories intersect.
  • Hiromitsu Sumino, Yoshitaka Uchida, Norihiro Ishikawa, Hiroshi Tsutsui, Hiroyuki Ochi, Yukihiro Nakamura
    2007 4TH IEEE CONSUMER COMMUNICATIONS AND NETWORKING CONFERENCE, VOLS 1-3 793 - + 2007年 [査読有り][通常論文]
     
    Design and implementation of home appliance control applications on a peer-to-peer network are presented in this paper. Home networks today exist in an environment where a mixture of various communication networks and different type of home appliances coexist, move, and communicate with one another over such heterogeneous networks. Peer-to-peer is one of the suitable technologies for such ubiquitous networking since it supports discovery mechanisms, simple one-to-one communication, free and extensible distribution of resources, and distributed search to handle the enormous number of resources. In our system, protocols defined by Peer-to-peer Universal Computing Consortium (PUCC) are used to control various kinds of devices over a Peer-to-peer network. This prototype system successfully controls home appliances, such as air conditioner, light, refrigerator, TV and video recorder, from mobile phones.
  • Hiroshi Tsutsui, Jaehoon Yu, Tomonori Izumi, Hiroyuki Ochi, Yukihiro Nakamura, Takaaki Komura, Yoshitaka Uchida, Norihiro Ishikawa
    2007 4TH IEEE CONSUMER COMMUNICATIONS AND NETWORKING CONFERENCE, VOLS 1-3 778 - + 2007年 [査読有り][通常論文]
     
    In this paper, a prototype implementation of streaming system that allows listening to and viewing multimedia contents using a mobile terminal, as part of our efforts toward realizing services linked with home networks and mobile networks is presented. In our system, appliances are detected and connected to a mobile terminal by use of peer-to-peer (P2P) network based on the PUCC protocols, and they are controlled by use of P2P messages and IEEE1394 AV/C. Streaming is managed by a gateway on the P2P network, where multimedia contents are converted to another format suitable to be sent to mobile terminals. This prototype system successfully achieves video data streaming over two different networks by using P2P network which conceals the differences among the networks.
  • 宮本 龍介, 菅野 裕揮, 齋藤 裕昭, 筒井 弘, 越智 裕之, 畑中 健一, 中村 行宏
    電子情報通信学会ソサイエティ大会 2006 178  2006年09月 [査読無し][通常論文]
  • 自己再構成アーキテクチャ評価検討のための合成ツール
    廣本 正之, 神山 真一, 中原 健太郎, 筒井 弘, 越智 裕之, 中村 行宏
    情報処理学会DAシンポジウム論文集 181 - 186 2006年07月 [査読有り][通常論文]
  • A JPEG Coding Scheme for High Fidelity Images by Halftoning Less Significant Extra Bits
    Fumihiko Hyuga, Takahiko Masuzaki, Hiroshi Tsutsui, Takao Onoye, Yukihiro Nakamura
    Proc. of International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC2006) 3 97 - 100 2006年07月 [査読有り][通常論文]
  • 日向 文彦, 増崎 隆彦, 筒井 弘, 尾上 孝雄, 中村 行宏
    電子情報通信学会技術研究報告 106 96 31 - 36 一般社団法人電子情報通信学会 2006年06月 [査読無し][通常論文]
     
    本稿ではハーフトーン処理を用いた高階調JPEG符号化を提案し,その最適化に関する検討を行う.JPEGで8ビット以上の深度を有する高階調画像を圧縮する際には,入力画像を8ビット深度の画像に変換する必要があり,元画像との間に画質の劣化が発生する.そこで,提案手法ではハーフトーン処理を用いることで高階調画像をJPEGで圧縮する際のビット深度減少に伴う画質劣化を抑えることを目指す.ハーフトーン処理は適用する画像によりその効果が有効な場合とそうでない場合があるため,提案手法では8×8サイズのブロックごとにハーフトーン処理および丸め処理を行い,視覚特性に基づく評価値の高い方の処理を選択する.
  • 宮本 龍介, 芦田 純平, 筒井 弘, 中村 行宏
    電子情報通信学会技術研究報告 106 96 25 - 30 一般社団法人電子情報通信学会 2006年06月 [査読無し][通常論文]
     
    本稿では,車載や監視用途において近年要求が高まっている歩行者トラッキング手法を提案する.提案手法では,モンテカルロフィルタに基づくトラッキングにおいて,歩行者のスケルトンモデルと距離変換画像からの尤度計算を利用することにより確率的歩行者トラッキングを実現する.提案手法をPETSから提供されている実シーケンスに適用することにより,その有効性を評価した.その結果,従来手法と比較し,大きな精度向上が達成できた.
  • 廣本 正之, 神山 真一, 中原 健太郎, 筒井 弘, 越智 裕之, 中村 行宏
    電子情報通信学会技術研究報告 106 49 7 - 12 2006年05月 [査読無し][通常論文]
  • 宮本 龍介, 原 悠記, 筒井 弘, 中村 行宏
    第19回 回路とシステム(軽井沢)ワークショップ 19 189 - 192 [電子情報通信学会] 2006年04月 [査読有り][通常論文]
  • 可変ウィンドウステレオマッチングプロセッサのアーキテクチャ
    宮本 龍介, 劉 載勲, 筒井 弘, 中村 行宏
    第19回 回路とシステム(軽井沢)ワークショップ 165 - 170 2006年04月 [査読有り][通常論文]
  • Efficient memory architecture for JPEG2000 entropy codec
    Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
    Proceedings - IEEE International Symposium on Circuits and Systems 2881 - 2884 2006年 
    An encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process entropy encoding/decoding. This module, however, requests many smallsize memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory architecture of the entropy encoding/decoding module is proposed, in which three approaches are attempted by utilizing one-bank SRAMs and internal registers. As a result, the efficient memory organization for a target process technology can be explored. © 2006 IEEE.
  • Hiroshi Tsutsui, Takahiko Masuzaki, Yoshiteru Hayashi, Yoshitaka Taki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    INTELLIGENT AUTOMATION AND SOFT COMPUTING 12 3 331 - 343 2006年 [査読有り][通常論文]
     
    For the exploration of system architecture dedicated to JPEG2000 coding, decoding and codec, a novel design framework is constructed. In order to utilize the scalability of JPEG2000 algorithm aggressively in system implementation, three types of modules are prepared for JPEG2000 coding/decoding/codec processes, i.e. software, software accelerated with user-defined instructions, and dedicated hardware. Specifically, dedicated hardware modules for forward and inverse discrete wavelet transformation (shortly DWT), entropy coder, entropy decoder, and entropy codec as well as software acceleration for the DWT process arc devised to be used in the framework. Furthermore, a JPEG2000 encoder LSI, which consists of a configurable processor Xtensa, the DWT module, and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
  • Hiroki Sugano, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Hiroyuki Ochi, Yukihiro Nakamura
    2006 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, PROCEEDINGS 2881 - 2884 2006年 [査読有り][通常論文]
     
    An encoding/decoding process of JPEG2000 requires much more computation power than that of conventional JPEG mainly due to the complexity of entropy encoding/decoding. Thus usually multiple entropy codec hardware modules are implemented in parallel to process entropy encoding/decoding. This module, however, requests many smallsize memories to store intermediate data, and when multiple modules are implemented on a chip, employment of the large number of SRAMs increases difficulty of whole chip layout. In this paper, an efficient memory architecture of the entropy encoding/decoding module is proposed, in which three approaches are attempted by utilizing one-bank SRAMs and internal registers. As a result, the efficient memory organization for a target process technology can be explored.
  • Ryusuke Miyamoto, Hiroki Sugano, Hiroaki Saito, Hiroshi Tsutsui, Hiroyuki Ochi, Ken'ichi Hatanaka, Yukihiro Nakamura
    ADVANCES IN IMAGE AND VIDEO TECHNOLOGY, PROCEEDINGS 4319 483 - + 2006年 [査読有り][通常論文]
     
    Nowadays, pedestrian recognition in far-infrared images toward realizing a night vision system becomes a hot topic. However, sufficient performance could not be achieved by conventional schemes for pedestrian recognition in far-infrared images. Since the properties of far-infrared images are different from visible images, it is not known what kind of scheme is suitable for pedestrian recognition in far-infrared images. In this paper, a novel pedestrian recognition scheme combining boosting-based detection and skeleton-based stochastic tracking suitable for recognition in far-infrared images is proposed. Experimental results by using far-infrared sequences show the proposed scheme achieves highly accurate pedestrian recognition by combining accurate detection with few false positives and accurate tracking.
  • Ryusuke Miyamoto, Jumpei Ashida, Hiroshi Tsutsui, Yukihiro Nakamura
    WMSCI 2006: 10TH WORLD MULTI-CONFERENCE ON SYSTEMICS, CYBERNETICS AND INFORMATICS, VOL V, PROCEEDINGS V 206 - + 2006年 [査読有り][通常論文]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian as a state space model and uses distance transformed images for likelihood estimation. The skeleton model used in the Proposed approach is very distinctive in representing a pedestrian simply but effectively, with which the efficient state space for the pedestrian tracking can be derived. Experimental results by using PETS sample sequences shows that the proposed approach achieves highly accurate pedestrian tracking on far-view sequences.
  • Jumpei Ashida, Ryusuke Miyamoto, Hiroshi Tsutsui, Takao Onoye, Yukihiro Nakamura
    2006 IEEE INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, ICIP 2006, PROCEEDINGS 2825 - + 2006年 [査読有り][通常論文]
     
    A novel pedestrian tracking scheme based on a particle filter is proposed, which adopts a skeleton model of a pedestrian as a state space model and uses distance transformed images for likelihood estimation. The six-stick skeleton model used in the proposed approach is very distinctive in representing a pedestrian simply but effectively, with which the efficient state space for the pedestrian tracking can be derived. Experimental results by using PETS sample sequences demonstrate that the proposed approach achieves highly accurate pedestrian tracking without any of prior learning.
  • 宮本 龍介, 筒井 弘, 杉田 弘晃, 増崎 隆彦, 越智 裕之, 尾上 孝雄, 中村 行宏
    電子情報通信学会ソサイエティ大会 2005 164  2005年09月 [査読無し][通常論文]
  • 筒井 弘, 菅野 裕揮, 増崎 隆彦, 越智 裕之, 尾上 孝雄, 中村 行宏
    電子情報通信学会ソサイエティ大会 2005 22  2005年09月 [査読無し][通常論文]
  • JPEG2000 符復号器のためのスケーラブルデザインフレームワーク
    筒井 弘, 増崎 隆彦, 尾上 孝雄, 中村 行宏
    VDEC LSI デザイナーフォーラム 2005年08月 [査読無し][通常論文]
  • R Miyamoto, H Sugita, Y Hayashi, H Tsutsui, T Masuzaki, T Onoye, Y Nakamura
    2005 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), VOLS 1-6, CONFERENCE PROCEEDINGS 2096 - 2099 2005年 [査読有り][通常論文]
     
    A novel high quality Motion JPEG2000 coding scheme is proposed, which is based on the human visual system being insensitive to high frequency component of image. This method enhances subjective video quality by controlling the amount of data allocated to each code-block according to amount of its motion. The proposed method enables video coding without degrading subjective quality of existing method at lower bitrate.
  • Video quality enhancement for Motion JPEG2000 encoding based on the human visual system
    Ryusuke Miyamoto, Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Takao Onoye, Yukihiro Nakamura
    Proc. of 2004 IEEE Asia Pacific Conference on Circuits and Systems (APCCAS2004) 1161 - 1164 2004年12月 [査読有り][通常論文]
  • 視覚特性を用いた Motion JPEG2000 レート制御手法
    筒井 弘, 林 宙輝, 宮本 龍介, 増崎 隆彦, 泉 知論, 尾上 孝雄, 中村 行宏
    第6回 YRP移動体通信産学官交流シンポジウム 152 - 153 2004年07月 [査読無し][通常論文]
  • J Ashida, R Miyamoto, H Tsutsui, T Onoye, Y Nakamura
    Proceedings of the Fourth IASTED International Conference on Visualization, Imaging, and Image Processing 6 - 11 2004年 [査読有り][通常論文]
     
    In recent years, detection of moving objects from image sequence is applied to various areas. One of the techniques for this detection is using estimation of the focus of expansion (FOE). Conventional approaches, however, bring some errors to detected motion vectors required for the estimation of the FOE. In this paper, an accurate and scalable approach for estimation of the FOE is proposed. The proposed approach reduces errors included in motion vectors so as to enable accurate estimation of the FOE. To achieve practical processing time of the FOE estimation, a hardware architecture for the proposed approach is also discussed.
  • T Onoye, H Tsutsui, G Fujita, Y Nakamura, Shirakawa, I
    Image Processing, Biomedicine, Multimedia, Financial Engineering and Manufacturing, Vol 18 18 243 - 250 2004年 [査読有り][通常論文]
     
    Embedded system architecture, which call be used for scalable and object-based video coding, is discussed in this paper. As for scalable video coding, namely JPEG2000, design framework for system architecture is Constructed with the main theme focused oil the ability of exploring implementation scheme for each process of JPEG2000 encoding. In order to demonstrate the practicability of the framework, a JPEG2000 encoder LSI has been implemented by using 0.18 mu m CMOS technology, which consists of two hardware modules and a configurable processor. This paper also describes real-time human object extraction algorithm, which call be used for video phone. Software simulation result of face and hair object extraction with the use of XScale processor claims that QCIF 15fps video call be processed in real-time.
  • H Tsutsui, T Masuzaki, Y Hayashi, Y Taki, T Izumi, T Onoye, Y Nakamura
    ADVANCES IN COMPUTER SYSTEMS ARCHITECTURE, PROCEEDINGS 3189 296 - 308 2004年 [査読有り][通常論文]
     
    For the exploration of system architecture dedicated to JPEG2000 coding, decoding and codec, a novel design framework is constructed. In order to utilize the scalability of JPEG2000 algorithm aggressively in system implementation, three types of modules are prepared for JPEG2000 coding/decoding/codec procedures, i.e. software, software accelerated with user-defined instructions, and dedicated hardware. Specifically, dedicated hardware modules for forward and inverse discrete wavelet transformation (shortly DWT), entropy coder, entropy decoder, and entropy codec as well as software acceleration of DWT procedure are devised to be used in the framework. Furthermore, a JPEG2000 encoder LSI, which consists of a configurable processor Xtensa, the DWT module, and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
  • H Sugita, VQ Minh, T Masuzaki, H Tsutsui, T Izumi, T Onoye, Y Nakamura
    2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 3, PROCEEDINGS 3 873 - 876 2004年 [査読有り][通常論文]
     
    An efficient scheme for JPEG2000 progressive decoding is proposed, which is capable of handling image codestreams with SNR progressiveness. In order to avoid processing, the same codestream data more than once when decoding SNR progressive images, a pair of techniques are introduced in our decoding scheme; reusing of intermediary decoded data and differential IDWT. Comprehensive evaluation of our scheme demonstrating that with 20% increase of required memory size, more than 40% of computational costs can be reduced in comparison with conventional (nonprogressive) decoding scheme.
  • High-Level Synthesis Design System for VLSI Processors in the 21st Century
    Yukihiro Nakamura, Hiroshi Tsutsui
    ASEAN Microelectronics 2003, AUN/SEED-Net Field-wise Seminar 2003年08月 [査読無し][通常論文]
  • 高度通信情報システムのためのアーキテクチャと設計技術
    中村 行宏, 泉 知論, 筒井 弘
    第5回 YRP移動体通信産学官交流シンポジウム 2003年07月 [査読無し][通常論文]
  • Scalable Design Framework for JPEG2000 Encoder Architecture
    Yoshiteru Hayashi, Hiroshi Tsutsui, Takahiko Masuzaki, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proc. of the 11th Workshop on Synthesis And System Integration of Mixed Information technologies (SASIMI2003) 372 - 377 2003年04月 [査読有り][通常論文]
  • Y Hayashi, H Tsutsui, T Masuzaki, T Izumi, T Onoye, Y Nakamura
    PROCEEDINGS OF THE 2003 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL II 2 740 - 743 2003年 [査読有り][通常論文]
     
    A novel design framework for exploring JPEG2000 encoding system architecture is proposed. In this framework, each procedure of JPEG200 encoding is selectively implemented among those by software, software accelerated with user-defined instructions, or dedicated hardware, while maintaining the compliance with the requirements and constraints of each terminals and applications, so as to optimize the encoding system organization. Dedicated hardware modules for DWT and entropy coder as well as software acceleration of DWT procedure are devised to be used in the framework. Furthermore, an LSI, which consists of the DWT module and the entropy coder, is fabricated to exemplify the system implementation designed through the use of proposed framework.
  • 筒井 弘, 増崎 隆彦, 泉 知論, 尾上 孝雄, 中村 行宏
    電子情報通信学会ソサイエティ大会 2002 89 - 89 一般社団法人電子情報通信学会 2002年09月 [査読無し][通常論文]
  • JPEG2000 Fully Scalable Image Encoder by Configurable Processor
    Hiroshi Tsutsui, Takahiko Masuzaki, Masayuki Oyamatsu, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proc. of Euromedia Conference 168 - 172 2002年04月 [査読有り][通常論文]
  • 増崎 隆彦, 筒井 弘, 泉 知論, 尾上 孝雄, 中村 行宏
    電子情報通信学会総合大会 2002 121 - 121 一般社団法人電子情報通信学会 2002年03月 [査読無し][通常論文]
  • H Tsutsui, T Masuzaki, T Izumi, T Onoye, Y Nakamura
    APCCAS 2002: ASIA-PACIFIC CONFERENCE ON CIRCUITS AND SYSTEMS, VOL 1, PROCEEDINGS 1 45 - 50 2002年 [査読有り][通常論文]
     
    This paper discusses a design of high speed JPEG2000 encoder. JPEG2000 entropy coding is realized by hardware module since its computational cost accounts for roughly 65% of total according to software profiling.. Discrete wavelet transformation (DWT) is accelerated by attaching user-defined instructions to Tensilica's configurable processor Xtensa. Utilizing the 8,700 gate entropy coder with 27 kbit of memory and the custom instructions implemented by 8,000 gates, the number of cycles needed to encode an image is reduced to 31%.
  • T Masuzaki, H Tsutsui, T Izumi, T Onoye, Y Nakamura
    2002 INTERNATIONAL CONFERENCE ON IMAGE PROCESSING, VOL III, PROCEEDINGS 3 77 - 80 2002年 [査読有り][通常論文]
     
    To cope with the recent mobile scenes where images are used aggressively, a novel rate control scheme is proposed in this paper. The proposed scheme, dedicated for JPEG2000 image coding, is aiming at achieving low computational cost and small working memory size yet maintaining high image quality. By predicting the adequate number of coding passes and updates it adaptively in code-block coding, the proposed scheme reduces both computational cost and working memory size for bitstream buffering down to 29% and 13%, respectively.
  • T Masuzaki, H Tsutsui, T Izumi, T Onoye, Y Nakamura
    2002 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL IV, PROCEEDINGS 4 333 - 336 2002年 [査読有り][通常論文]
     
    A novel rate control scheme is proposed dedicatedly for, JPEG2000 image coding. By predicting bitrate of coded data and updating it adaptively, the proposed scheme can be executed in parallel with the code-block coding of code-block coding such as coefficient bit modeling and arithmetic coding. The proposed scheme successfully reduces computational cost and working memory size of the process down to 29% and 13%, respectively, comparing to a conventional approach in case of 1/16 compression, and hence is suitable, to be used in embedded systems.
  • H Tsutsui, A Tomita, S Sugimoto, K Sakai, T Izumi, T Onoye, Y Nakamura
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES E84A 11 2681 - 2689 2001年11月 [査読有り][通常論文]
     
    In this paper, a design of Programmable Logic Device (PLD) and a synthesis approach are proposed. Our PLD is derived from traditional Programmable Logic Array (PLA). The key extension is that programmable AND devices in PLA is replaced by Look-Up Tables (LUTs). A series of cascaded LUTs in the array call generate more complex terms, which we call generalized complex terms (GCTs), than product terms. In order to utilize the capability, a synthesis approach to map a given function into the array is also proposed. Our approach generates a expression of the sum of GCTs aiming to minimize the number of terms. A number of experimental results demonstrate that the number of terms for our PLD generated by our approach is 14.9% fewer than that by ail existing approach. We design our PLD based oil a fundamental unit named nGCT cell which call be used as LUTs in multiple sizes or random access memories Implementation of the PLD based oil a fundamental unit named nGCT cell which call be used as LUTs or random access memories is also described.
  • 筒井 弘, 増崎 隆彦, 泉 知論, 尾上 孝雄, 中村 行宏
    電子情報通信学会ソサイエティ大会 2001 115  2001年09月 [査読無し][通常論文]
  • Design of JPEG2000 Encoder for Fully Scalable Image Coding
    Hiroshi Tsutsui, Takahiko Masuzaki, Masayuki Oyamatsu, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proc. of World Multi-Conference on Systemics, Cybernetics and Informatics (SCI2001) XV 546 - 551 2001年07月 [査読有り][通常論文]
  • 増崎 隆彦, 筒井 弘, 親松 昌幸, 泉 知論, 尾上 孝雄, 中村 行宏
    電子情報通信学会技術研究報告 101 141(CAS2001 1-28) 63 - 70 一般社団法人電子情報通信学会 2001年06月 [査読無し][通常論文]
     
    本稿ではスケーラブル符号化のためのJPEG2000符号器アーキテクチャについて述べる. JPEG2000がサポートする全てのプログレッシブ順序のピットストリームを生成するために必要となるパス終端計算, レイヤ分割, タイルパート構成の効率的な実装法を提案する. また, コンフィギュラブル・プロセッサXtensaを使用してユーザ定義の命令を追加することにより高速化を図り, 所要サイクル数を約40%削減した.
  • 16bit Free CPU の設計
    筒井 弘, 増崎 隆彦
    第18回パルテノン研究会 2001年05月 [査読無し][通常論文]
  • Hiroshi Tsutsui, Kazuhiro Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    Proceedings of IEEE International Symposium on Circuits and Systems (ISCAS) 5 203 - 206 2001年05月 [査読有り][通常論文]
  • 冨田 明彦, 杉本 成範, 筒井 弘, 境 和久, 泉 知論, 中村 行宏
    システムLSI琵琶湖ワークショップ 243 - 246 2000年11月 [査読無し][通常論文]
  • LUTアレイ型PLDの設計と試作
    杉本 成範, 冨田 明彦, 筒井 弘, 境 和久, 檜田 和浩, 中村 行宏
    VDEC LSI デザイナーフォーラム 85  2000年09月 [査読無し][通常論文]
  • 筒井 弘, 檜田 和浩, 泉 知論, 尾上 孝雄, 中村 行宏
    情報処理学会DAシンポジウム論文集 2000 8 21 - 26 2000年07月 [査読有り][通常論文]
  • PCAデバイスの設計と試作
    杉本 成範, 冨田 明彦, 筒井 弘, 境 和久, 檜田 和浩, 中村 行宏
    第16回パルテノン研究会 31 - 42 2000年05月 [査読無し][通常論文]
  • 16bit Free CPU の設計
    宮本 龍介, 筒井 弘, 中西 龍太
    第16回パルテノン研究会 2000年05月 [査読無し][通常論文]

MISC

  • Shingo Yoshizawa, Hiroshi Tsutsui IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 106 (3) 454 -455 2023年03月
  • LoRa変調における拡散率の変化に対する消費電力の評価
    八杉 拓哉, 筒井 弘, 大鐘 武雄 電気・情報関係学会北海道支部連合大会 151 -152 2021年09月 [査読無し][通常論文]
  • ブロックチェーンと IoT 技術を用いたオーストラリアと日本の間における和牛トレーサビリティの促進
    筒井 弘, Ying He, 大鐘 武雄 FOOMA JAPAN 2021 アカデミックプラザ研究発表要旨集 28 88 -91 2021年06月 [査読無し][通常論文]
  • ゴロム符号を用いたラインベース適応処理による映像軽圧縮手法に関する一検討
    大塚 祐大, 片岸 由奈子, 筒井 弘 電気・情報関係学会北海道支部連合大会 89 -90 2020年11月 [査読無し][通常論文]
  • Webカメラを用いた製造ライン状態報告ランプモニタリングシステムにおけるSVMによる色判定の評価
    髙杉 豪, 筒井 弘, 宮永 喜一 電子情報通信学会ソサイエティ大会 85 -85 2020年09月 [査読無し][通常論文]
  • Yunzhe Wang, Yu Tian, Yoshikazu Miyanaga, Hiroshi Tsutsui IEICE Technical Report 120 (51) 49 -54 2020年06月 [査読無し][通常論文]
  • 駐車場におけるWebカメラを用いた駐車判定の実験的評価
    福﨑 卓人, 筒井 弘, 宮永 喜一 電子情報通信学会総合大会 139 -139 2020年03月 [査読無し][通常論文]
  • 高スループットスケーラブルRadix-4 FFT回路の設計とその回路規模評価
    川幡 知孝, 筒井 弘, 宮永 喜一 電子情報通信学会総合大会 124 -124 2020年03月 [査読無し][通常論文]
  • 5G規格無線通信システムにおけるスクランブルのハードウェア実装
    平山 茉利子, 筒井 弘, 宮永 喜一 電子情報通信学会北海道支部学生会インターネットシンポジウム予稿集 2020年02月 [査読無し][通常論文]
  • 中越達也, 早坂昇, 筒井弘, 宮永喜一 電子情報通信学会大会講演論文集(CD-ROM) 2019 ROMBUNNO.A‐15‐2 2019年03月05日 [査読無し][通常論文]
  • 山田健太郎, 筒井弘, 須藤彰紘, 宮永喜一 電子情報通信学会大会講演論文集(CD-ROM) 2019 ROMBUNNO.A‐15‐10 2019年03月05日 [査読無し][通常論文]
  • Yoshikazu Miyanaga, Junji Yamano, Masaki Miura, Tohru Gotoh, Takashi Imagawa, Hiroshi Tsutsui 2018 Asia-Pacific Signal and Information Processing Association Annual Summit and Conference, APSIPA ASC 2018 - Proceedings 1087 -1090 2019年03月04日 [査読無し][通常論文]
     
    © 2018 APSIPA organization. This paper shows the total system of real-time FHD video communication over wireless system. The wireless system can realize the data rate of 3Gbps by use of an 80-MHz baseband bandwidth and a 8\times 8 MIMO-OFDM scheme. A low-latency and the optimum pipelined architecture are realized into all processing blocks. In addition, the video compression is based on loss-less coding/decoding. By using this mechanism, the original video can be transferred by a wireless system. In addition, the minimum latency can be realized by using a small size block based video coding. It provides the real-time operations of video communications. The proposed architecture realizes low power consumption.
  • 福元敦己, 今川隆司, 筒井弘, 宮永喜一, 越智裕之 電子情報通信学会技術研究報告 118 (473(SIS2018 37-52)) 5‐9 2019年02月27日 [査読無し][通常論文]
  • 浮橋慶太, 今川隆司, 筒井弘, 宮永喜一, 越智裕之 電子情報通信学会技術研究報告 118 (473(SIS2018 37-52)) 53‐58 2019年02月27日 [査読無し][通常論文]
  • 防犯カメラ映像解析のマルチコアプロセッサを用いたフレーム単位並列化による高速化の評価
    福﨑 卓人, 筒井 弘, 宮永 喜一 電子情報通信学会北海道支部学生会インターネットシンポジウム予稿集 2019年02月 [査読無し][通常論文]
  • Yu Tian, Jiayue Tang, Xiaonan Jiang, Hiroshi Tsutsui, Yoshikazu Miyanaga ISCIT 2018 - 18th International Symposium on Communication and Information Technology 101 -104 2018年12月24日 [査読無し][通常論文]
     
    © 2018 IEEE. This paper is mainly about the accuracy on the children speech recognition under noisy circumstances and methods to improve it. The power of the children's speech is lower than the adult. The accuracy of children speech recognition is unavoidably affected by the ambient noise. We executed a series of experiments to calculate the recognition accuracy for children speech under clean condition and different noisy conditions. It has been reported that running spectrum analysis (RSA) and running spectrum filtering (RSF) have the capability to enhance the robustness in the speech recognition system under noisy conditions. In subsequent experiments, we added RSA and RSF to the speech feature extraction and obtained a children recognition system with enhanced noise suppression capability and achieved higher recognition accuracy.
  • An Accuracy Evaluation of Fingerprint Database Constructed by Mean-Shift Clustering for WiFi Indoor Positioning Systems
    Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga Proceedings of 2018 Winter International Symposium on Big-Data, Cybersecurity and IoT 2018年12月 [査読無し][通常論文]
  • WiFi Indoor Positioning System Using Fingerprint Database Constructed by Mean-Shift Clustering with Estimated Reference Locations
    Myat Hsu Aung, Hiroshi Tsutsui, Yoshikazu Miyanaga Proceedings of the GSB Student Workshop, The 2nd GI-CoRE GSQ, GSB & IGM Joint Symposium 2018年08月 [査読無し][通常論文]
  • 渡辺大詩, 筒井弘, 今川隆司, 宮永喜一 映像情報メディア学会技術報告 42 (23(BCT2018 60-72)) 47‐50 2018年07月19日 [査読無し][通常論文]
  • Xiaonan Jiang, Tatsuya Nakagoshi, Jiayue Tang, Riku Takanashi, Yu Tian, Hiroshi Tsutsui, Yoshikazu Miyanaga IEICE Technical Report 118 (149) 53 -58 2018年07月 [査読無し][通常論文]
  • 池下貴大, 渡辺大詩, 筒井弘, 宮永喜一 映像情報メディア学会技術報告 42 (11(BCT2018 38-49)) 25‐28 2018年03月02日 [査読無し][通常論文]
  • 井原大文, 今川隆司, 上坂浩貴, 鴻上慎吾, 筒井弘, 宮永喜一, 越智裕之 電子情報通信学会技術研究報告 117 (455(VLD2017 89-128)) 55‐60 2018年02月21日 [査読無し][通常論文]
  • Yoshikazu Miyanaga, Hiroshi Tsutsui, Takashi Imagawa 2017 17th International Symposium on Communications and Information Technologies, ISCIT 2017 2018-January 1 -5 2018年01月16日 [査読無し][通常論文]
     
    © 2017 IEEE. The developed system has achieved the data rate of 3Gbps by use of an 80-MHz baseband bandwidth and a 8×8 MIMO-OFDM scheme. This paper describes the VLSI implementation of the 8×8 MIMO-OFDM system. A low-latency and the optimum pipelined architecture are realized into all processing blocks. It provides the real-time operations on OFDM modulation and MIMO detection. The proposed architecture also realizes low power consumption. This system has been applied for high-quality video communication. With some of results on field experiments, the system performance for video communications is described under real environments.
  • 渡辺大詩, 池下貴大, 筒井弘, 今川隆司, 宮永喜一 電気・情報関係学会北海道支部連合大会講演論文集(CD-ROM) 2017 ROMBUNNO.71 2017年10月28日 [査読無し][通常論文]
  • Hiroshi Tsutsui, Mitsuji Muneyasu IEICE Transactions on Fundamentals of Electronics, Communications and Computer Sciences 100-A (11) 2219 -2220 2017年
  • チップ試作による最小動作電圧予測手法の評価
    川島 潤也, 筒井 弘, 越智 裕之, 佐藤 高史 電子情報通信学会ICD研究会 ICD2012-87 3 -8 2012年12月 [査読無し][通常論文]
  • Zhi Li, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato 研究報告システムLSI設計技術（SLDM） 2012 (21) 1 -6 2012年11月19日 
    With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65nm CMOS technology, the proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.With the increased operating frequency and the reduction of feature size, achieving low error-rate data transmission between LSIs is an important field of research. In particular, input/output (I/O) impedance matching, as one of the necessary technologies for high-speed transmission, is strongly required. In this paper, we propose an architecture of output buffer whose impedance is self-adjustable against process variation and temperature characteristic of MOS transistors. The proposed architecture utilizes on-chip sensor circuits to capture threshold voltages and temperatures. Based on a commercial 65nm CMOS technology, the proposed method has been verified. Without the use of reference resistor, it successfully adjusts the I/O impedance within 2.36% and 1.4% around a target of 50Ω through simulation and measurement, respectively, regardless of the process parameters and temperature.
  • 粟野 皓光, 清水 裕史, 筒井 弘, 越智 裕之, 佐藤 高史 研究報告システムLSI設計技術（SLDM） 2011 (15) 1 -6 2011年11月21日 
    ランダムテレグラフノイズ (Random Telegraph Noise: RTN) は微細デバイスの信頼性や回路特性に関わる物理現象であり，様々なモデル化手法が提案されている．閾値電圧の変動'|届と変動時定数は，種々のモデルに共通する特に重要なパラメータであるが，測定データからこれらを求めることは困難な課題となっている．本研究では，キャリアの捕獲と放出の過程を統計的モデルとして表現し，マルコフ連鎖モンテカルロ法 (MCMC） を用いて各パラメータをベイズ推定する手法を提案する．人工的に生成した RTN 信号に提案手法を適用し，良好な結果が得られたが，実測信号については課題も見られた．Random Telegraph Noise (RTN) is a physical phenomenon that is considered to determine reliability and performance of circuits. Time constants of carrier capture and emission, and an associated change of threshold voltage are the important parameters commonly involved in various models, but their extraction from time-domain observations has been a difficult task. In this study, we propose a statistical method for estimating the time constants and the magnitude of threshold voltage shift. Our method is based on a graphical network representation and the parameters are estimated using Markov Chain Monte Carlo (MCMC) method. Experimental application of the proposed method on a synthetic time-domain RTN signal was very successful, while estimation examples on measured RTN signals suggest there is room for further improvement.
  • 宮川 哲朗, 筒井 弘, 越智 裕之, 佐藤 高史 研究報告システムLSI設計技術（SLDM） 2011 (13) 1 -6 2011年11月21日 
    ランダムウオークによる線形回路の過渡解析を高速化する手法を提案する．提案手法では，準ゼロ分散推定法に基づいて逐次的な確率更新を行う際に，一解析時刻前の節点電圧を利用して解析に必要なサンプル数を削減する．また解析中にサンプル数を自動的決定することにより，節点電位の変動による推定の不安定化を防止しつつ高速化を図る．提案手法により，従来のランダムウォーク法に基づく過渡解析に対して 10 倍以上の高速化を実現し，サンプル数自動決定により高速化と解析の安定化の両立を実現した．We propose a method to accelerate random walk based transient analysis of linear circuits. Our method uses quasi-zero-variance estimation with adaptive sample number determination, in which walk probabilities are adaptively updated to reduce estimation variance. The node voltages of previous time step are reused to give initial guesses for alternative probabilities at every time point, which reduces the total number of required samples. An adaptive determination of the number of samples makes estimation very stable and accelerate the analysis even further. The proposed analysis achieves more than 10x speedup against the conventional method.
  • 森下 拓海, 筒井 弘, 越智 裕之, 佐藤 高史 研究報告システムLSI設計技術（SLDM） 2011 (12) 1 -5 2011年11月21日 
    半導体プロセスの微細化が進み，電源回路網の解析が重要になっている．また，電源回路網それ自体の規模も大きく，今後のさらなる巨大化に対応するためにも，回路解析の高速化省メモリ化が大きな課題となっている．ブロック反復法は直接法と反復法を組み合わせた解析方法であり，大規模電源回路網解析への応用が期待されている．本稿ではブロック反復法の高速化を目的として，SOR 法およびブロック分割の観点から収束の加速方法を検討する．Because of its extremely large size, power grid analysis has been a computationally challenging problem both in terms of runtime and memory usage. LU factorization has been widely used to analyze voltage drop simulations due to its stability, but contiguous technology scaling demands even more efficient calculation methods. In this paper, application of block-iterative method, which combines LU factorization and iterative method, is proposed for efficient analysis of power grid analysis. Automatic adjustment of relaxation factor in successive over-relaxation method and block decomposition algorithm are proposed. Evaluation results are also presented.
  • 冨田 明彦, 杉本 成範, 筒井 弘, 境 和久, 檜田 和浩, 泉 知論, 尾上 孝雄, 中村 行宏 電子情報通信学会技術研究報告. VLD, VLSI設計技術 100 (473) 173 -178 2000年11月23日 
    近年, 論理の再構成が可能なデバイスとしてPLDが広く用いられている.本稿ではPLDの一種として, PLAのANDアレイの部分をLUTのアレイに置き換えたLUTアレイ型PLDを提案する.このPLDは, LUTの多段接続により項を生成するため高い項表現の能力を持ち, 少ない項数で回路を埋め込むことが可能である.また設計時に, LUTを複数組み合わせて, より入力数の多いLUTや, メモリとして利用するための機能を併せて実装した.これらの機能を付加するにあたり, 入力のデコード回路を各機能間で共有することで回路規模の増大を抑制している.ベンチマーク回路の埋め込み時に必要となる項数について, 入力デコーダ付きPLAとの比較を行った結果, LUTアレイ型PLDの方が14.9%少ない項数で回路を埋め込めることがわかった.

講演・口頭発表等

  • Design Techniques for Wireless Communication and Image Processing IP Cores  [招待講演]
    Hiroshi Tsutsui
    The 1st Hokkaido Young Professionals Workshop 2021年10月 公開講演，セミナー，チュートリアル，講習，講義等

担当経験のある科目（授業）

  • メディアシステム設計論北海道大学
  • メディアネットワーク演習Ⅰ北海道大学
  • メディアネットワーク実験ⅡＢ
  • メディアネットワーク実験ⅠＢ北海道大学
  • メディアネットワーク演習Ⅱ北海道大学
  • ネットワーク構成論北海道大学
  • ネットワークシステム特論北海道大学
  • 電気電子工学実験B京都大学

所属学協会

  • 映像情報メディア学会   情報処理学会   ACM   電子情報通信学会   IEEE   電気学会   パルテノン研究会   画像電子学会   

共同研究・競争的資金等の研究課題

  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2023年04月 -2027年03月 
    代表者 : 大鐘 武雄, 筒井 弘, 西村 寿彦
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2023年04月 -2026年03月 
    代表者 : 筒井 弘
  • 極低消費電力型マルチメディアIoTシステムの研究開発
    総務省：戦略的情報通信研究開発推進事業（SCOPE）先進的電波有効利用型
    研究期間 : 2020年04月 -2021年03月 
    代表者 : 筒井 弘
  • 日本学術振興会：科学研究費助成事業 基盤研究(B)
    研究期間 : 2016年04月 -2020年03月 
    代表者 : 坂本 雄児, 似内 映之, 筒井 弘, 山ノ井 高洋, 山口 一弘, 奥山 文雄
     
    本研究によって、世界最小、最軽量の電子ホログラフィ技術を用いたHead-mounted display (ホロHMD)の開発に成功した。また、高速計算法およびデータ圧縮法の研究により、現在のハードウェア技術レベルにおいても、リアルタイム計算、および通信可能な手法を提案した。これらの研究により、ホロHMDがシステムとして実用になりうることを示した。一方、スペックルによる画質劣化が大きいことが問題として残ったが、アルゴリズムによる抑圧法を検討し、その可能性を示した。生理的反応の測定に関しては、今後とも検討が必要である。
  • 極低消費電力型マルチメディアIoTシステムの研究開発
    総務省：戦略的情報通信研究開発推進事業（SCOPE）先進的電波有効利用型
    研究期間 : 2018年03月 -2020年03月 
    代表者 : 宮永 喜一, 筒井 弘
  • 日本学術振興会：科学研究費助成事業 若手研究(B)
    研究期間 : 2014年04月 -2017年03月 
    代表者 : 筒井 弘
     
    近年の撮像デバイスでは(1)高解像度・通常フレームレート(2)低解像度・高フレームレート，といった撮影モードをユーザが設定できるようになっている．このような2種類の動画像が利用可能である場合を想定し，それらから高品位映像(高解像度・高フレームレート)をフレーム補間により生成する手法を提案し，従来のフレーム補間より効率的に高品位映像を生成可能であることを示した．また，映像中の動きの有無に応じた適応処理を考え，縮小画像を用いた高速な動領域検出法を提案した．
  • 文部科学省：科学研究費補助金(基盤研究(B), 基盤研究(B))
    研究期間 : 2011年 -2013年 
    代表者 : 越智 裕之, 佐藤 高史, 筒井 弘, 中村 行宏
     
    人類がこれまでアナログメディアで蓄積してきた書物、音楽、映像等の文化遺産のデジタル化や、増えつつあるオンラインコンテンツの散逸防止が急務であるが、既存の光ディスクや磁気ディスク等の寿命は数10年と言われている。そこで研究代表者らは、長寿命なデジタル記憶メディアとしてマスクROMに注目し、その長期信頼性を更に高めるべく、マスクROMの実装されたシリコンチップ全体を完全に絶縁層で封止し、エネルギー供給やデータの取り出しを全て非接触で行うことを考え、更に、各記憶メディアに相互通信する機構を持たせ、拡張性の高い大規模アーカイブシステムを実現することを考えた。この実現に向け、平成24年度は、(a)オンチップ非接触電源供給および(b)データ通信技術の予備評価、ならびに、(c)低電圧動作可能なマスクROMの方式検討と評価を行った。(a)オンチップ非接触電源供給技術の予備評価に関しては、通常の0.18μmCMOSプロセス上に太陽電池を実装したチップの試作及び測定を行った。CMOSプロセスで太陽電池を実装した場合、基板電位より高い電圧を効率よく取り出すことは困難であることが知られているが、それを可能とする回路方式を新たに着想し、その基本的な動作を実測により確認することができた。この技術はセンサネットワークや能動無線タグ等にも適用可能性があり、現在、特許出願を検討している。(b)オンチップ非接触データ通信技術の予備評価に関しても、実測による評価を行った。この結果、周辺回路の発熱の影響で受信回路の動作が大きく影響を受けることを示唆する有益な結果が得られた。(c)低電圧動作可能なマスクROMの方式検討と評価に関しては、単位面積当たりのビット数で優れるNAND型マスクROMについて、設計およびシミュレーションによる評価を行った。この結果、65nmプロセスで最小サイズのトランジスタを使用して実現した32bit・32wordのNAND型マスクROMが電源電圧0.7V程度までは正常に動作し得ることを確認した。
  • 文部科学省：科学研究費補助金(基盤研究(B), 基盤研究(B))
    研究期間 : 2010年 -2012年 
    代表者 : 佐藤 高史, 越智 裕之, 筒井 弘
     
    今年度は昨年度に引き続き、モンテカルロ法による統計的タイミング解析を高速化するための並列計算アルゴリズムの検討、および、時間的にパラメータが変動するばらつきモデルについての基礎検討を実施した。1)タイミング解析アルゴリズムに関しては、昨年度検討した回路の最遅到着時間の伝搬をFPGA上にタイミンググラフの構造通りに実現する方法、を発展させ、汎用のタイミング計算専用演算器を定義し、これがメモリに数値を読み書きするプロセッサ型の実装方法を提案した。この実装では、モンテカルロ試行レベルでの並列化を実現できる。従来法に存在していた回路規模の制約を無くし、大規模回路にも効率よく適用できる見通しを得ている。また、回路が変わる度に実行する必要があったFPGAへのマッピング処理を不要とし、実質的な解析時間を低減した。同時に、良質な乱数を多数同時に出力可能な乱数生成器をFPGA上に実現することで、従来手法と遜色の無いスループットが得られることを確認した。2)トランジスタの特性ばらつきは、チップ内の信号伝搬遅延時間に多大な影響を与える。近年になって、特にトランジスタのしきい値が回路の動作中、経時的に変動するNBTIやRTN等の現象がタイミングに与える影響が大きくなってきている。これらの影響をタイミング解析にフィードバックするため、チップ試作により特に時間的な変動に関するデータを取得した。チャネル面積の小さいトランジスタでは、全トランジスタの経時変化量やその速度が同一でなく、これらもトランジスタごとに異なっていることを実験的に明らかとした。さらに今後、ばらつきの影響が特に大きいと考えられる低電圧での回路動作と関連したタイミング解析についてもチップ試作を通じて検討を実施する。
  • 日本学術振興会：科学研究費助成事業
    研究期間 : 2002年 -2004年 
    代表者 : 筒井 弘
     
    本研究の目的は,スケーラブル動画像符号化の組込み機器への効率的な実装手法の提案である.前年度までに於て,JPEG2000スケーラブル符号化/復号化を対象として,様々なシステム要求に対して最適な実装を容易かつ効率的に実現可能とするスケーラブルなデザインフレームワークの実現を目標とし,検討および実装/評価を行っている.本年度は,これまでに実装を行ったソフトウェアならびにハードウェア処理モジュールを組合せ,フレームワークの全体の構築を行い,「組込み向けJPEG2000符号化方式の実装法」と題した博士論文にまとめた.提案デザインフレームワークでは,アプリケーションの要求や設計時の制約条件に応じて,共通モジュールを選択的に利用することによって,最適なJPEG2000復号器/復号器/コーデックの実装を得ることができる. さらに,JPEG2000で各フレームを圧縮する動画像符号化方式であるMotion JPEG2000に関して,組込み機器での利用が見込まれる,低ビットレート符号化時における主観画質の向上手法を提案した.提案手法ではJPEG2000の持つ特長と人間の視覚特性を利用して,Motion JPEG2000の主観的画質を向上させる.JPEG2000は変換に離散ウェーブレット変換(DWT)を用いているために,符号化の過程で画像内の位置に応じて符号量の割り当てを制御することが容易となっている.人間の視覚特性は刺激の空間周波数,時間周波数に依存して特性が変化し,周波数が高いほど感度が低下する.提案する手法は,人間の視覚特性を利用して,時間周波数,空間周波数が高い領域に割り当てる符号量を減らし,それ以外の領域に割り当てる符号量を増やす.その結果,動画像全体の主観的画質を向上させることに成功した.

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