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Akazawa Masamichi

Research Center for Integrated Quantum ElectronicsAssociate Professor

Researcher basic information

■ Degree
  • 博士（工学）, 北海道大学
■ URL
researchmap URL■ Various IDs
Researcher number
  • 30212400
J-Global ID■ Research Keywords and Fields
Research Keyword
  • GaN
  • surface passivation
  • interface
  • surface
  • XPS
  • MOS
  • Al2O3
  • InAlN
  • nitride semiconductor
  • 界面準位
  • InGaAs
  • GaAs
  • MIS
  • テラヘルツ
  • InP
  • デバイス
  • ヘテロ界面
Research Field
  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering), Electric and electronic materials
  • Nanotechnology/Materials, Thin film/surface and interfacial physical properties
  • Manufacturing Technology (Mechanical Engineering, Electrical and Electronic Engineering, Chemical Engineering), Electron device and electronic equipment
  • Nanotechnology/Materials, Crystal engineering
  • Nanotechnology/Materials, Applied physical properties
■ Educational Organization

Career

■ Career
Career
  • Apr. 1995 - Present
    Hokkaido University, Associate Professor
  • Nov. 1988 - Mar. 1995
    Hokkaido University, Research Associate
Educational Background
  • Apr. 1988 - Oct. 1988, Hokkaido University, Graduate School of Enigineering, Division of Electrical Engineering
  • Apr. 1984 - Mar. 1988, Hokkaido University, Faculty of Enigineering, Department of Electrical Engineering
Committee Memberships
  • Aug. 2019 - Present
    The 14th International Conference on Nitride Semiconductors (ICNS-14), ICNS-14 Local Arrangement Comittee, Society
  • May 1995 - Present
    電子情報通信学会, ソサイエティ論文誌編集委員会査読委員, Society
  • Sep. 2020 - Nov. 2021
    International Conference on Solid-State Devices and Materials, Secretary of Steering Committee, Society
  • Nov. 2014 - Oct. 2015
    2015年固体素子・材料コンファレンス, 実行委員, Society
  • May 2002 - May 2003
    電子情報通信学会, シリコン材料・デバイス研究専門委員会幹事, Society
  • Apr. 2002 - Mar. 2003
    応用物理学会, シリコンテクノロジー研究分科会常任出版幹事, Society
  • Nov. 2000 - May 2002
    電子情報通信学会, シリコン材料・デバイス研究専門委員会幹事補佐, Society
  • May 1995 - Oct. 2000
    電子情報通信学会, シリコン材料・デバイス研究専門委員会専門員, Society

Research activity information

■ Awards
  • Sep. 2024, 第10回北大・部局横断シンポジウム実行委員会, ベストポスター賞
    窒化ガリウムのMOSトランジスタ応用のための界面制御の研究
    赤澤正道, Japan society, Japan
  • Mar. 2024, 16th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials / 17th International Conference on Plasma-Nano Technology & Science / 13th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (ISPlasma2024/IC-PLANTS2024/APSPT-13, Nagoya University, Nagoya, Japan, March 3–7, 2024), The Best Poster Presentation Award
    "Effects of SiO2-Cap Annealing Prior to Interface Formation on Properties of Al2O3/p-type GaN Interfaces"
    Yining Jiao;Takahide Nukariya;Umi Takatsu;Taketomo Sato;Masamichi Akazawa, International society, Japan
  • Mar. 2023, 15th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials/ 16th International Conference on Plasma-Nano Technology & Science (ISPlasam2023/IC-PLANTS2023, Gifu University, Gifu, Japan, March 5–9, 2023), The Best Poster Presentation Awards
    "Impact of ultra-high-pressure annealing on interface state density distribution near conduction band at Al2O3/Mg-ion-implanted GaN interface"
    Y. Hatakeyama;M. Akazawa;T. Narita;M. Bockowski;T. Kachi, International society, Japan, 33660220;13864903
  • Sep. 2016, JSAP, JSAP Paper Award
    "Characterization of electronic states at insulator/(Al)GaN interfaces for improved insulated gate and surface passivation structures of GaN-based transistors"
    Zenji Yatabe;Yujin Hori;Wan-Cheng Ma;Joel T. Asubar;Masamichi Akazawa;Taketomo Sato;Tamotsu Hashizume
  • May 2013, CSManTech, 2013 Paper Awards (He Bong Kim Award)
    "Characterization and Control of Insulated Gate Interfaces"
    Tamotsu Hashizume;Masamichi Akazawa
  • Oct. 1998, the 5th International Conference on Soft Computing and Information/ Intelligent Systems (IIZUKA '98), Best Paper Award
    "A Functional Neuro-MOS Circuit for Implementing Cellular-Automaton Picture-Processing Devices"
    M. Ikebe;M. Akazawa;Y. Amemiya
  • Aug. 1990, International Conference on Solid State Devices and Materials, SSDM Young Researcher Award
    "In0.53Ga0.47As MISFETs Having an Ultrathin MBE Si Interface Control Layer and Photo-CVD SiO2 Insulator"
    M. Akazawa
■ Papers
■ Other Activities and Achievements
  • Impact of interface formation process on properties of photoelectrochemically etched p-GaN MOS interfaces
    JIAO Yining; 忽滑谷崇秀; 高津海; 佐藤威友; 赤澤正道, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 71st, 2024
  • Investigation of Charge Generated at Surface of p-type GaN
    JIAO Y.; 高橋尚伸; 島崎喬大; 佐藤威友; 赤澤正道, 応用物理学会秋季学術講演会講演予稿集(CD-ROM), 85th, 2024
  • 窒化物半導体異種接合の評価と制御
    佐藤威友; 赤澤正道; 橋詰保, 応用物理学会春季学術講演会講演予稿集(CD-ROM), 61st, 2014
  • Effects of Fabrication Process on Electrical Properties of InAlN MOS Structures with ALD-Al_2O_3
    Chiba Masahito; Nakano Takuma; Akazawa Masamichi, IEICE technical report. Electron devices, 113, 329, 101, 105, 28 Nov. 2013
    We investigated the dependence of the electrical properties on the fabrication procedure for InAlN MOS structure having an Al_2O_3 layer formed by atomic layer deposition (ALD). When the ALD Al_2O_3/InAlN interface was formed after ohmic-contact annealing in nitrogen without the use of a cap layer, the electrical properties were poor, resulting in a small capacitance change in the capacitance-voltage (C-V) curve. X-ray photoelectron spectroscopy (XPS) study indicated that the bare InAlN surface was oxidized during capless annealing presumably owing to the trace contamination in the furnace. High-temperature ohmic-contact annealing after Al_2O_3/InAlN interface formation did not improve the interface properties, resulting in interface state density D_ in the range of 10^<13>cm^<-2>eV^<-1>, despite the use of the Al_2O_3 layer for surface protection. This was highly likely related to the crystallization of Al_2O_3. When a SiN_x layer was used as the cap layer during ohmic-contact annealing prior to ALD, greatly improved characteristics of the MOS diode were achieved, indicating that D_ was suppressed to be in the range of 10^<12>cm^<-2>eV^<-1> near the conduction band. Furthermore, as a result of low-temperature post-deposition annealing at 400℃ for this sample, reduction of the interface states was achieved. The obtained results indicate that an appropriate fabrication procedure leads to an improvement of the Al_2O_3/InAlN interface properties., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Evaluation of Sub-terahertz Periodic Structure in a Coplanar Stripline
    YAMAZAKI Yusuke; INAFUNE Koji; AKAZAWA Masamichi; SANO Eiichi, IEICE technical report. Electron devices, 104, 693, 41, 46, 24 Feb. 2005
    A periodic structure in a subterahertz coplanar stripline (CPS) was fabricated on a low-temperature-grown GaAs (LT-GaAs) layer in order to achieve an electromagnetic bandgap (EBG). To optimize dimension of structures, we used the finite-difference-time-domain (FDTD) method for the full-wave analysis. In consequence, we found that the thickness of the metal layer affects the characteristic of EBGs. Take into account this result, the sample structure was designed, fabricated, and characterized by the photoconductive sampling (PCS). Two bandgaps and an intermediate passband were observed in the range up to 0.5THz, which coincided with the results of simulation based on the FDTD method., The Institute of Electronics, Information and Communication Engineers, Japanese
  • A Low-Loss Coplanar Waveguide for the THz Region and Its Application to Electromagnetic-Bandgap Filters
    INAFUNE Koji; AKAZAWA Masamichi; SANO Eiichi, IEICE technical report. Microwaves, 104, 296, 45, 49, 07 Sep. 2004
    A numerical study of a method to reduce the radiation loss of a coplanar waveguide (CPW) is reported, and the application of the low-loss CPW to electromagnetic-bandgap (EBG) filters for the THz region is described. The finite-difference time-domain (FDTD) method was used for the full-wave analysis of CPWs and filters. It is expected that the radiation loss could be greatly reduced by constructing a CPW on a substrate consisting of a thin GaAs film reinforced with a thick backside insulator with a low dielectric constant. The application of the same substrate structure to a newly devised EBG-based filter built in a CPW was investigated, and the structure was found effective for preserving a high transmission rate in a high-frequency passband., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Application of UHV Contactless C-V Measurement to the Surface of SOI
    Akazawa Masamichi; Hasegawa Hideki, Proceedings of the Society Conference of IEICE, 2002, 2, 59, 59, 20 Aug. 2002
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Evaluation of carbon thin films deposited by oxygen plasma assisted PLD method
    ONO Tomoyuki; SUDA Yoshiyuki; AKAZAWA Masamichi; SUGAWARA Hirotake; SAKAI Yosuke; SUZUKI Kaoru, 電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan, 2001, 381, 386, 21 Sep. 2001
    Japanese
  • Deposition and Characterization of C:F Films Using C_7F_<16> : Effect of Material Gas Pressure and Gas Additions
    HOKOI K.; AKAZAWA M.; SUGAWARA H.; SUDA Y.; SAKAI Y., 電気学会研究会資料. ED, 放電研究会, 2001, 111, 13, 18, 07 Aug. 2001
    Japanese
  • Characterization of ultrathin insulator/Si interfaces formed on n-Si(001) by UHV contactless capacitance-voltage method
    SHOUJI Ryouhei; HASHIZUME Tamotsu; YOSHIDA Toshiyuki; AKAZAWA Masamichi; HASEGAWA Hideki, IEICE technical report. Electron devices, 100, 641, 45, 52, 21 Feb. 2001
    Ultrathin insulator/Si interfaces formed by various low temperature processes were characterized by UHV contactless C-V and XPS methods. For the SiO_2/Si interfaces prepared by thermal oxidation process using dry O_2, the interface state density was increased with decreasing the oxidation temperature. In addition, lower temperature process was found to produce a discrete defect level near midgap. The ECR-excited N_2O plasma process at 400℃ realized the interface with relatively low interface state density and wide distribution. Furthermore improvement of interface properties were achieved by the UHV annealing process at 900℃., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Proposal and Fabrication of a QMESFET
    AKAZAWA M.; KASAI S.; HASHIZUME T.; HASEGAWA H., IEICE technical report. Electron devices, 100, 641, 89, 96, 21 Feb. 2001
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the proposed device as a ULSI device by reducing its size., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Programmable Three-Dimensional Cellular-Neural-Network LSI
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the Society Conference of IEICE, 2000, 2, 83, 83, 07 Sep. 2000
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Fabrication of an Insulated Gate MESFET Using an SOI Layer
    AKAZAWA Masamichi, Proceedings of the Society Conference of IEICE, 2000, 2, 76, 76, 07 Sep. 2000
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Parameter Design of a Single-Electron Inverter With Multiple-Valued Characteristics
    KANAAMI K.; AKAZAWA M.; AMEMIYA Y., IEICE technical report. Circuits and systems, 99, 550, 1, 8, 19 Jan. 2000
    Functional LSIs using extremely small amounts of power can be made by using single-electron circuits, but designing the parameters of such circuits is a complicated and troublesome task. This paper therefore propose, taking the single-electron inverter circuit as an example, a simple policy for the circuit-parameter design. Following this policy, we can easily design a single-electron inverter with a desired transfer characteristic. We have, for example, designed a special inverter circuit that can be used for constructing multiple-valued logic systems. A multiple-valued transfer characteristic(or a staircase transfer curve), which is difficult to obtain with CMOS circuits, can be obtained easily., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Programmable Three-Dimensional Cellular-Neural-Network Circuits
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the IEICE General Conference, 128, 128, 2000
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Pulsed Laser Deposition of Carbon Films in Ar plasmas
    NISHIMURA Takuma; MIZUNO Manabu; SUDA Yoshiyuki; SAKAI Yosuke; AKAZAWA Masamichi, 電気学会研究会資料. ED, 放電研究会, 1999, 148, 79, 84, 19 Oct. 1999
    Japanese
  • Observation of Laser Ablated Carbon Plume
    SUDA Yoshiyuki; MIZUNO Manabu; NISHIMURA Takuma; BRATESCU M. A.; SAKAI Yosuke; AKAZAWA Masamichi, 電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan, 1999, 324, 329, 08 Sep. 1999
    Japanese
  • Pulsed Laser Deposition of Carbon Films
    NISHIMURA Takuma; MIZUNO Manabu; SUDA Yoshiyuki; SAKAI Yosuke; AKAZAWA Masamichi, 電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan, 1999, 317, 317, 08 Sep. 1999
    Japanese
  • A Single-Flux-Quantum Logic Circuit Based on the Modified BDD Structure
    Akazawa M.; Amemiya Y., Proceedings of the Society Conference of IEICE, 1999, 2, 25, 25, 16 Aug. 1999
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • A Three Dimensional νMOS Cellular-Neural-Network Circuit
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the Society Conference of IEICE, 1999, 2, 103, 103, 16 Aug. 1999
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Circuit Design of A Three Dimensional Cellular Neural Network Using vMOS
    FUJIWARA T.; AKAZAWA M.; AMEMIYA Y., Technical report of IEICE. VLD, 99, 107, 109, 116, 10 Jun. 1999
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem, is designed., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Solving Combinational Optimization Problems with the Quantum Hopfield Network
    TOKUDA E.; ASAHI N.; AKAZAWA M.; AMEMIYA Y., IEICE technical report. Neurocomputing, 98, 674, 77, 82, 19 Mar. 1999
    The quantum Hopfield network is a kind of recurrent neural network that can always converge to the global minimum state without being stuck in local minima. This property is obtained by utilizing the co-tunneling phenomenon in quantum systems. This paper proposes a method of constructing the quantum Hopfield network by using single-electron circuits. The operation of the single-electron quantum Hopfield network is analized by computer simulation, assuming an instance of combinatrial optimization problems. It is demonstrated that, starting with a given initial state, the network can converge to the minimum energy state that represents the correct solution to the problem., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Boltzmann Machine Device Using Signle-Electron Circuits
    YAMADA Takashi; AKAZAWA Masamichi; AMEMIYA Yoshihito, IEICE technical report. Neurocomputing, 98, 673, 115, 120, 18 Mar. 1999
    This paper proposes to create Boltzmann Machine device by using single-electron circuits. The Boltzmann machine is a kind of recurrent neural network that can solve various problems in subject such as combinational optimization. It is difficult for presently available electronic circuits to implement the generation of randomness for the stochastic neuron operation. We can construct the stochastic neuron device concisely by using single-electron circuits and, thereby, can implement the Boltzmann machine on an LSIs., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Color Petri-net Circuits Using Multiple-Valued Signals
    Koutani M.; Akazawa M.; Amemiya Y., Proceedings of the IEICE General Conference, 1999, 2, 143, 143, 08 Mar. 1999
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • A Three-Dimensional Cellular Neural Network Circuit
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the IEICE General Conference, 144, 144, 1999
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Single-Flux-Quantum Logic Circuits Based on the Binary Decision Diagram : Circuit design for a 32-bit adder
    ASAHI Noboru; YAMADA Takashi; AKAZAWA Masamichi; AMEMIYA Yoshihito, Technical report of IEICE. SCE, 98, 399, 43, 50, 16 Nov. 1998
    A 32-bit adder circuit is designed using single-flux-quantum (SFQ) circuits, on the basis of the binary decision diagram (BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. We here construct a high-speed SFQ adder circuit based on a BDD representation simplified by the method of isomorphic-subgraph substitution. To construct the adder circuit compactly, we propose the BDD device that can be driven by SFQ signal. It is shown by computer simulation that the operation speed of the designed 32-bit adder is 350ps., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Single-Flux-Quantum Logic circuits based on the Binary Decision Diagram
    ASAHI Noboru; AKAZAWA Masamichi; AMEMIYA Yoshihito, Proceedings of the Society Conference of IEICE, 1998, 2, 28, 28, 07 Sep. 1998
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Multiple-Valued-Logic Processing Based on the Pulse Width Modulation
    FUKASAWA Yoshiyuki; AKAZAWA Masamichi; AMEMIYA Yoshihito, Proceedings of the Society Conference of IEICE, 1998, 2, 127, 127, 07 Sep. 1998
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Network Operation of the Single-Electron Boltzmann Machine
    YAMADA Takashi; AKAZAWA Masamichi; AMEMIYA Yoshihito, Proceedings of the Society Conference of IEICE, 1998, 7, 7, 07 Sep. 1998
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Solving Combinatorial Optimization Problems with the Quantum Hopfield Network
    TOKUDA E.; ASAHI N.; AKAZAWA M.; AMEMIYA Y., Proceedings of the Society Conference of IEICE, 1998, 8, 8, 07 Sep. 1998
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Single-Flux-Quantum Logic Circuits Based on the Binary Decision Diagram
    ASAHI Noboru; AKAZAWA Masamichi; AMEMIYA Yoshihito, Technical report of IEICE. SCE, 98, 222, 49, 56, 28 Jul. 1998
    This paper proposes the single-flux-quantum logic circuit based on the binary decision diagram(BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. By implementing BDDs with single-flux-quantum circuits, we can create various logic systems that are capable of high speed operation.Construction and operation of an 8-bit adder is presented as an example., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Quantum Hopfield Network Using Single-Electron Circuits : Hopfield Network Without the Local-Minimum Problem
    AKAZAWA M.; AMEMIYA Y., IEICE technical report. Neurocomputing, 97, 624, 265, 271, 20 Mar. 1998
    The Hopfield network is a computation model for solving combinatorial optimization problems through the use of the specific feedback network. The feedback network changes its internal state to minimize the energy function. Thus we can obtain the solution to the given problem by relating the cost function of the problem to the energy function of the network and by observing how the network settles down to the minimum energy state. Owing to the existence of local minima in the energy function, however, we cannot always be certain of obtaining the correct solution to the problem. To overcome this difficulty, the author proposes the idea that a novel Hopfield network, free from the local-minimum problem, can be attained by constructing the feedback network using single-electron circuits. In the single-election circuit, a phenomenon exists called "cotunneling", in which two or more tunnelings occur simultaneously as a coherent coupling. Using this phenomenon, we can construct a "quantum Hopfield network" in which the transition of a Hamming distance of more than two is possible., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Multiple-valued Logic Based on Pulse-Width Modulation
    Fukasawa Yoshiyuki; Akasawa Masamichi; Amemiya Yoshihito, Proceedings of the IEICE General Conference, 1998, 2, 201, 201, 06 Mar. 1998
    The Institute of Electronics, Information and Communication Engineers, Japanese
  • Single-Electron Majority Logic Circuits
    IWAMURA Hiroki; AKAZAWA Masamichi; AMEMIYA Yoshihito, Technical report of IEICE. SDM, 97, 273, 39, 44, 26 Sep. 1997
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation error induced by thermal agitation is also estimated., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Single-electron step inverter
    Asahi Noboru; Akazawa Masamichi, Proceedings of the Society Conference of IEICE, 1997, 2, 77, 77, 13 Aug. 1997
    単電子回路では、輸送電荷の離散性とクーロンブロッケード現象とが相まって、通常の電子回路には見られない様々な特性が現れる。そのためCMOS回路では得られない種々の機能が実現可能となる。たとえば、インバータ回路を例にとってパラメータ探索を行ったところ、入出力の伝達特性がステップ的に変化する「ステップインバータ」の機能が得られることが判明した。これは、しきい論理回路や多値論理回路を低電力設計するときに不可欠のものである。以下に結果を報告する。, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Programmable logic device using single-electron quasi-CMOS circuits
    Nitta Hidehiko; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the Society Conference of IEICE, 1997, 2, 131, 131, 13 Aug. 1997
    単電子回路を用いてCMOS型の論理回路が構成されており, 擬似CMOS型単電子回路と呼ばれている. ところで, 単電子回路の性質を上手に利用すれば, 本来のCMOSにはない新しい機能を付加することができる. ここでは, 入力の組合わせにより論理を切り換えられる可変論理デバイスを提案する., The Institute of Electronics, Information and Communication Engineers, Japanese
  • νMOS multiple-valued logic circuit based on the decision diagram
    Yamada Takashi; Iwamura Hiroki; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the Society Conference of IEICE, 1997, 2, 135, 135, 13 Aug. 1997
    決定グラフとはディジタル論理を有向グラフで表す手法であり、論理設計や論理検証などのCADで使われている。本研究では、多値論理の決定グラフ(MDD:Multiple-valued Decision Diagram)を実際のデバイスで構成することを提案する。具体例として、4値論理MDDをシリコン機能デバイスのνMOSで構成してみた。加算器を例にとってシミュレーション解析を行い、正しい論理動作を確認した。以下に結果を述べる, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Low-power Construction of νMOS Cellular Automata
    IKEBE Masayuki; Honma Kunihiko; Akazawa Masamichi; AMEMIYA Yoshihito, Proceedings of the Society Conference of IEICE, 1997, 2, 134, 134, 13 Aug. 1997
    νMOSインバータは、多入力しきい論理に適したデバイスである。これを用いると画像処理用セルオートマトン回路をコンパクトに構成できる。しかし、しきい論理回路ではνMOSをオンとオフの中間状態で使うことが多く、そのため貫通電流を生じて消費電力が大きくなりやすい。 ここではνMOS回路の低電力設計を考える。雑音除去・輪郭抽出セルオートマトン回路を例にとり、ダイナミック形と高しきい値MOS形の2つの構成法によって低電力設計行った。以下にその詳細を示す。, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Construction of Logic Circuits Using Single-Electron BDD Devices
    AKAZAWA M.; ASAHI N.; AMEMIYA Y., IEICE technical report. Electron devices, 96, 573, 9, 16, 14 Mar. 1997
    This paper proposes an idea of constructing single-electron logic circuits based on the binary-decision diagram (BDD). The proposed unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting the identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for elemental logic circuits (NAND, NOR, XOR) and combinational logic circuits (a four-variable logic circuit and a 4-bit adder). Computer simulation shows that the designed circuits perform the logic operations correctly., The Institute of Electronics, Information and Communication Engineers, Japanese
  • Analog Logic Circuits Using BDD devices
    Fukasawa Yoshiyuki; Akazawa Masamichi; Amemiya Yoshihito, Proceedings of the IEICE General Conference, 1997, 2, 192, 192, 06 Mar. 1997
    二分決定グラフ(BDD)は, ブール代数式や真理値表とは異なる方法, 有向グラフによってディジタル論理を表す手法である。もともと論理設計や論理検証に使われていたが, 最近になって実際のデバイスでBDD論理を組むという研究が報告されるようになった。ここでは, BDDの適用範囲をアナログに拡大することを提案する。これによって新しい応用が生まれる可能性がある。, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Analog Signal Processing Using Single-Electron Circuits
    Akasawa Masamichi; Amemiya Yoshihito, Proceedings of the IEICE General Conference, 1997, 2, 196, 196, 06 Mar. 1997
    単電子現象は本質的に離散現象なので, それを利用した単電子回路も本来はデジタル論理に適したものである。しかしアナログ回路の開発も将来に向けて必要とされる。ここでは電子密度変調によるアナログ表現法を提案し, そのための回路構成を考えてみた。, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Possibility of Operation of Logic Circuit Using Quantum Cellular Automata
    Akazawa Masamichi; Amamiya Yoshihito, Proceedings of the Society Conference of IEICE, 1996, 2, 253, 254, 18 Sep. 1996
    量子セルの近接相互作用を利用したセルオートマトン(QCA)が提案されている。しかしこれまでのところセル配列の静的な安定状態を考察するに留まり、システム全体として動作するかどうかは理論的にも実験的にも検証されていない。そこで著者は種々の観点からその動作可能性を検討し、アニーリングによる駆動を行えばシステム動作が可能であろう、との予測を行った。, The Institute of Electronics, Information and Communication Engineers, Japanese
  • A Phosphorus Pile-Up Model for SiO2-Si interface of p-Channel MOSFETs
    Aoki Takahiro; Akazawa Masamichi; Tazawa Satoshi, Proceedings of the Society Conference of IEICE, 1996, 2, 127, 127, 18 Sep. 1996
    計算機上でプロセス・デバイス・回路をシミュレートし、デバイスの特性を予測するTechnology CAD技術は短TATな製造技術の開発に必要である。特性予測をより正確に行うには地道な実験データの蓄積とモデリングが必須である。一般にpチャネルMOSFETにおいて、nウェル形成用の燐ドーパントにはパイルアップ現象があることが知られており、この現象を取り扱っていない従来のシミュレータでは、デバイス特性予測を大きく狂わすことが知られている。また、SiO2-Si界面において酸化工程、アニール工程後の燐ドーパントの再分布(偏析)があることも一般的に知られている。本報告では、燐ドーパントのパイルアップ現象をモデル化し、種々のプロセス水準に対するpチャネルMOSFETのしきい値電圧の実測結果と比較した結果を述べる。, The Institute of Electronics, Information and Communication Engineers, Japanese
  • Strategy in developing LSIs using quantum devices-How to implement information processing using quantum effects-
    AMEMIYA Yoshihito; AKAZAWA Masamichi, 應用物理, 64, 8, 765, 768, 10 Aug. 1995
    応用物理学会, Japanese
  • Electrical Conduction Near Surface of Semi-Insulating Substrate and Its Surface Passivation
    佐々木 恵二; 赤沢 正道; 塩原 俊助; 長谷川 英機, Bulletin of the Faculty of Engineering,Hokkaido University, 170, p35, 43, Jul. 1994
    北海道大学 = Hokkaido University, Japanese
  • A New Surface Passivation Method of InGaAs Using a Si Ultrathin Layer and Its Application
    大植 英司; 赤沢 正道; 児玉 聡; 長谷川 英機, Bulletin of the Faculty of Engineering,Hokkaido University, 156, p51, 58, Jul. 1991
    北海道大学 = Hokkaido University, Japanese
  • Characterization of InGaAs MIS Structure by DLTS Method
    Uraie Atsuhiro; Akazawa Masamichi; Hasegawa Hideki, Research reports, Kushiro Technical College, 24, 53, 58, 20 Dec. 1990
    Kushiro National College of Technology, Japanese
■ Books and other publications
  • 第２版 応用物理ハンドブック 応用物理学会編
    Masamichi Akazawa, 第9章 半導体デバイス 9.12半導体センサとトランスデューサ 9.12.1 磁電効果デバイス, p.643; 9.12.2 熱電効果デバイス, p.644; 9.12.4 放射線検出デバイス, p.645.
    Maruzen, Apr. 2002, [Contributor]
  • 電子情報通信ハンドブック 6-13編 新概念集積回路
    雨宮好仁; 宮永喜一; 赤澤正道, pp. 808 - 814
    オーム社, Jun. 1998, [Contributor]
■ Lectures, oral presentations, etc.
  • Effects of 850℃ pre-annealing prior to activation RTA of Mg-ion-implanted GaN on properties of MOS structures formed afterwards
    Hinata Karasawa; Masanobu Takahashi; Masamichi Akazawa; Shota Kaneki; Masafumi Yokoyama; Hajime Fujikura
    2026 JSAP Spring Meeting, 16 Mar. 2026, JSAP, Japanese, Oral presentation
    15 Mar. 2026 - 18 Mar. 2026, Tokyo, Japan, 47958768;44494238;33660220;47958870, [Domestic Conference]
  • Origin of Near-interface Donor-type Defects in p-GaN MOS Structures
    M. Takahashi; T. Shimazaki; T. Sato; M. Akazawa
    2026 JSAP Spring Meeting, 16 Mar. 2026, JSAP, Japanese, Oral presentation
    15 Mar. 2026 - 18 Mar. 2026, Tokyo, Japan, 47958768;44494238;33660220, [Domestic Conference]
  • Fabrication of inversion-type GaN MOSFET by applying simultaneous low-temperature annealing to MOS interface and ohmic contacts
    Hiroto Akabane; Hinata Karasawa; Masanobu Takahashi; Masamichi Akazawa
    2026 JSAP Spring Meeting, 15 Mar. 2026, JSAP, Japanese, Poster presentation
    15 Mar. 2026 - 18 Mar. 2026, Tokyo, Japan, 47958768;44494238;33660220, [Domestic Conference]
  • Effects of long-term 850℃ pre-annealing prior to rapid activation annealing at 1250℃ on Mg-ion implanted GaN studied by using MOS structures
    H. Karasawa; M. Takahashi; M. Akazawa
    18th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials/ 19th International Conference on Plasma-Nano Technology & Science (ISPlasma2026/IC-PLANTS2026, Meijo University, Nagoya, Aichi, Japan, March 2–6, 2026)., 05 Mar. 2026, English, Oral presentation
    02 Mar. 2026 - 06 Mar. 2026, Nagoya, Japan, 47958870;33660220, [International presentation]
  • p型GaNを用いたMOS構造における界面近傍欠陥の低損傷エッチングと熱処理による制御
    高橋尚伸; 嶋崎喬大; 佐藤威友; 赤澤正道
    電子情報通信学会ED/CMP/LQE 合同研究会, 21 Nov. 2025, Japanese, Oral presentation
    20 Nov. 2025 - 21 Nov. 2025, 47958768;44494238;33660220, [Domestic Conference]
  • Attempt to control p-GaN MOS interfaces by combining photoelectrochemical etching and 850℃ annealing
    M. Takahashi; T. Shimazaki; T. Sato; M. Akazawa
    2025 JSAP Fall Meeting, 10 Sep. 2025, JSAP, Japanese, Poster presentation
    07 Sep. 2025 - 10 Sep. 2025, Nagoya, Japan, 47958768;44494238;33660220, [Domestic Conference]
  • Investigation of effects of 850℃ annealing prior to activation annealing on Mg-ion-implanted GaN using MOS structures
    H. Karasawa; M. Takahashi; M. Akazawa
    2025 JSAP Fall Meeting, 10 Sep. 2025, JSAP, Japanese, Poster presentation
    07 Sep. 2025 - 10 Sep. 2025, Nagoya, Japan, 47958768;44494238;47958870, [Domestic Conference]
  • [招待講演] GaN MOS界面制御の重要性
    赤澤正道; 佐藤威友
    IEICE-SDM IEICE-ICD ITE-IST 合同研究会, 08 Aug. 2025, 電子情報通信学会、映像情報メディア学会, Japanese, Oral presentation
    06 Aug. 2025 - 08 Aug. 2025, 札幌, Japan, 47958768;44494238;33660220, [Invited], [Domestic Conference]
  • Suppression of hole injection into near-interface traps by inserting AlN interfacial layer between AlSiO and GaN
    M. Akazawa; M. Takahashi; K. Itoh; T. Narita
    15th International Conference on Nitride Semiconductors (ICNS-15, Clarion Hotel Malmö Live, Malmö, Sweden, July 6–11, 2025), 09 Jul. 2025, English, Oral presentation
    06 Jul. 2025 - 11 Jul. 2025, Malmö, Sweden, 47958768;44494238;33660220, [International presentation]
  • Investigation of GaN MOS structures with SiO2 formed by atomic layer deposition using bis (ethyl-methyl-amino) silane and ozone
    M. Takahashi; Y. Jiao; M. Akazawa
    15th International Conference on Nitride Semiconductors (ICNS-15, Clarion Hotel Malmö Live, Malmö, Sweden, July 6–11, 2025), 07 Jul. 2025, English, Poster presentation
    06 Jul. 2025 - 11 Jul. 2025, Malmö, Sweden, 47958768;44494238;33660220, [International presentation]
  • Effects of Pre-Annealing at 850 ℃ Using AlON Cap Layer on Properties of GaN MOS Interfaces
    M. Akazawa; G. Shindo; M. Takahashi
    Compound Semiconductor Week 2025 (CSW2025, Banff Centre for Arts and Creativity, Banff, Alberta, Canada, May 27–30, 2025), 29 May 2025, English, Oral presentation
    27 May 2025 - 30 May 2025, 47958768;44494238;47958870, [International presentation]
  • Effects of Dehydrogenation Annealing Using AlON Surface-Protection Layer on p-GaN MOS interface
    M. Tkahashi; Y. Jiao; M. Akazawa
    2025 JSAP Spring Meeting, 14 Mar. 2025, Japanese, Poster presentation
    14 Mar. 2025 - 17 Mar. 2025, 47958768;33660220;44494238, [Domestic Conference]
  • Reduction of positive fixed charges at Al2O3/p-GaN interface by pre-annnealing using AlON cap layer
    Masanobu Takahashi; Yining Jiao; Masamichi Akazawa
    17th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials/ 18th International Conference on Plasma-Nano Technology & Science (ISPlasma2025/IC-PLANTS2025, Chubu University, Kasugai, Aichi, Japan, March 3–7, 2025)., 05 Mar. 2025, English, Poster presentation
    03 Mar. 2025 - 07 Mar. 2025, 47958768;44494238;33660220, [International presentation]
  • Effects of Long-Term Low-Temperature Annealing Prior to Activation Annealing on Near-Conduction-Band-Edge Gap States in Vicinity of Mg-Ion-Implanted GaN Surface
    Y. Luo; Y. Hatakeyama; M. Akazawa
    32nd International Colloquium on Scanning Probe Microscopy (ICSPM32, Hotel Monterey Edelhof Sapporo, Sapporo, Japan, Nov. 18–20, 2024), 18 Nov. 2024, English, Poster presentation
    18 Nov. 2024 - 20 Nov. 2024, Japan, 33660220;13864903, [International presentation]
  • X-Ray Photoelectron Spectroscopy Monitoring of Fermi Level Position at Mg-Doped p-Type GaN Surface During MOS Interface Formation
    Y. Jiao; M. Takahashi; M. Akazawa
    32nd International Colloquium on Scanning Probe Microscopy (ICSPM32, Hotel Monterey Edelhof Sapporo, Sapporo, Japan, Nov. 18–20, 2024), 18 Nov. 2024, English, Poster presentation
    18 Nov. 2024 - 20 Nov. 2024, Japan, 47958768;33660220, [International presentation]
  • Investigation of Charges Originated from Near-Surface Defects I p-type GaN Using X-ray Photoelectron Spectroscopy and MOS Diodes
    M. Akazawa; Y. Jiao; M. Takahashi; T. Shimazaki; T. Sato
    International Workshop on Nitride Semiconductors 2024 (IWN2024, Hilton Hawaiian Village, O’ahu, Hawai’i, USA, Nov. 3–8, 2024), 05 Nov. 2024, English, Oral presentation
    03 Nov. 2024 - 08 Nov. 2024, Honolulu, United States, 47958768;44494238;33660220, [International presentation]
  • Mgイオン打ち込みしたGaNに対する850℃アニールの表面およびバルク欠陥への影響についてのMOS構造を用いた評価(3)
    新藤 源大; 畠山 優希; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 18 Sep. 2024, 応用物理学会, Japanese, Poster presentation
    16 Sep. 2024 - 20 Sep. 2024, 新潟, Japan, 47958768;44494238;40296562, [Domestic Conference]
  • Mgイオン注入後2段階アニールを行ったGaN中の伝導帯付近禁制帯内準位のMOS構造を用いた評価 (2)
    羅 宇瀏; 畠山 優希; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 18 Sep. 2024, Japanese, Poster presentation
    16 Sep. 2024 - 20 Sep. 2024, 33660220;47958768;44494238
  • GaNに対するSiO2キャップアニールの効果についてのXPS評価
    高橋 尚伸; 焦 一寧; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 18 Sep. 2024, 応用物理学会, Japanese, Poster presentation
    16 Sep. 2024 - 20 Sep. 2024, 新潟, Japan, 33660220;47958768;44494238, [Domestic Conference]
  • p型GaN表面に発生する電荷についての検討
    焦 一寧; 高橋 尚伸; 島崎 喬大; 佐藤 威友; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 16 Sep. 2024, 応用物理学会, Japanese, Invited oral presentation
    16 Sep. 2024 - 20 Sep. 2024, 新潟, Japan, 33660220;47958768;44494238, [Domestic Conference]
  • Effects of Moderate-Temperature Annealing on Near-Surface Defects in Mg-Implanted GaN Studied Using MOS Structures
    G. Shindo; Y. Hatakeyama; M. Akazawa
    2024 International Conference on Solid State Devices and Materials (SSDM2024, Arcrea Himeji, Himeji, Hyogo, Japan, Sept. 1 – 4, 2024)., 03 Sep. 2024, English, Poster presentation
    01 Sep. 2024 - 04 Sep. 2024, 47958870
  • Investigation of Charges Originated from Near-Surface Defects in p-type GaN Using X-ray Photoelectron Spectroscopy and MOS Diodes
    M. Akazawa; Y. Jiao; M. Takahashi; T. Shimazaki; T. Sato
    Compound Semiconductor Week 2024 (CSW2024, Lund University, Lund, Sweden, June 3–6, 2024)., 03 Jun. 2024, English, Poster presentation
    03 Jun. 2024 - 06 Jun. 2024, Lund, Sweden, 47958768;33660220;13864903;44494238, [International presentation]
  • Mgイオン注入後2段階アニールを行ったGaN中の伝導帯付近禁制帯内準位のMOS構造を用いた評価
    羅 宇瀏; 畠山 優希; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 22 Mar. 2024, 応用物理学会, Japanese, Poster presentation
    22 Mar. 2024 - 25 Mar. 2024, 東京, Japan, 44494238;33660220, [Domestic Conference]
  • MgとNのイオン共注入後超高圧アニールを行ったGaNのMOS界面近傍伝導帯付近禁制帯準位の評価
    畠山 優希; 加地徹; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 22 Mar. 2024, 応用物理学会, Japanese, Poster presentation
    22 Mar. 2024 - 25 Mar. 2024, 東京, 33660220;44494238, [Domestic Conference]
  • Mgイオン打ち込みしたGaNに対する850℃アニールの表面およびバルク欠陥への影響についてのMOS構造を用いた評価(2)
    新藤 源大; 畠山 優希; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 22 Mar. 2024, Japanese, Poster presentation
    22 Mar. 2024 - 25 Mar. 2024, 44494238;47958870
  • 光電気化学エッチングを施したp-GaN MOS界面の特性に対する界面形成プロセスの影響
    焦 一寧; 忽滑谷 崇秀; 高津 海; 佐藤 威友; 赤澤 正道
    2024年応用物理学会秋季学術講演会, 22 Mar. 2024, 応用物理学会, Japanese, Poster presentation
    22 Mar. 2024 - 25 Mar. 2024, 東京, Japan, 33660220, [Domestic Conference]
  • Effects of SiO2-Cap Annealing Prior to Interface Formation on Properties of Al2O3/p-type GaN Interfaces
    Yining Jiao; Takahide Nukariya; Umi Takatsu; Taketomo Sato; Masamichi Akazawa
    16th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials / 17th International Conference on Plasma-Nano Technology & Science / 13th Asia-Pacific International Symposium on the Basics and Applications of Plasma Technology (ISPlasma2024/IC-PLANTS2024/APSPT-13, Nagoya University, Nagoya, Japan, March 3–7, 2024), 04 Mar. 2024, English, Poster presentation
    03 Mar. 2024 - 07 Mar. 2024, Japan, 33660220, [International presentation]
  • MOS-structure based study of defects in Mg-ion-implanted GaN
    Y. Hatakeyama; Y. Luo; G. Shindo; M. Akazawa
    International Conference on Materials and Systems for Sustainability (ICMaSS2023, Nagoya University, Nagoya, Japan, December 1-3, 2023), 02 Dec. 2023, English, Oral presentation
    01 Dec. 2023 - 03 Dec. 2023, 33660220, [International presentation]
  • MOS interface technologies for high-power and high-frequency GaN transistors (invited)
    T. Hashizume; M. Akazawa
    14th International Conference on Nitride Semiconductors (ICNS-14, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, November 12-17, 2023), 14 Nov. 2023, English, Invited oral presentation
    12 Nov. 2023 - 17 Nov. 2023, [Invited], [International presentation]
  • Interface Properties of p-type GaN MOS Structures Examined by Sub-Bandgap-Light-Assisted Capacitance–Voltage Measurement
    T. Nukariya; J. Yining; U. Takatsu; T. Sato; M. Akazawa
    14th International Conference on Nitride Semiconductors (ICNS-14, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, November 12-17, 2023)., 14 Nov. 2023, English, Poster presentation
    12 Nov. 2023 - 17 Nov. 2023, 33660220, [International presentation]
  • Detection of Gap States Originated from Ga-Interstitial and Divacancy Defects in Mg-Implanted GaN Using MOS Structures
    Y. Hatakeyama; G. Shindo; Y. Luo; M. Akazawa
    14th International Conference on Nitride Semiconductors (ICNS-14, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, November 12-17, 2023)., 14 Nov. 2023, English, Oral presentation
    12 Nov. 2023 - 17 Nov. 2023, 33660220, [International presentation]
  • Photoelectrochemical etching of AlGaN/GaN heterostructures and control of reaction rates
    T. Togashi; Y. Oki; Y. Osawa; R. Ochi; M. Akazawa; T. Sato
    2023 JSAP Fall Meeting, 22 Sep. 2023, Japanese, Oral presentation
    20 Sep. 2023 - 23 Sep. 2023
  • Sub-bandgap-light-assisted C–V measurement of MOS structure with photoelectrochemically etched p-GaN
    Takahide Nukariya; Jiao Yining; Umi Takatsu; Taketomo Sato; Masamichi Akazawa
    2023 JSAP Fall Meeting, 22 Sep. 2023, Japanese, Oral presentation
    20 Sep. 2023 - 23 Sep. 2023, 33660220
  • Evaluation of gap-states near conduction band in the vicinity of MOS interface for Mg- and N-ion-co-implanted GaN
    Yuki Hatakeyama; Masamichi Akazawa
    2023 JSAP Fall Meeting, 22 Sep. 2023, Japanese, Oral presentation
    20 Sep. 2023 - 23 Sep. 2023, 33660220
  • Influence of solution pH on Contactless-Photoelectrochemical (CL-PEC) etching of GaN
    Y. Osawa; M. Akazawa; T. Sato
    2023 JSAP Fall Meeting, 21 Sep. 2023, Japanese, Poster presentation
    20 Sep. 2023 - 23 Sep. 2023
  • Assessment of effects of 850℃ annealing on surface and bulk defects of Mg-ion implanted GaN using MOS structure
    Genta Shindo; Yuki Hatakeyama; Masamichi Akazawa
    2023 JSAP Fall Meeting, 21 Sep. 2023, Japanese, Poster presentation
    20 Sep. 2023 - 23 Sep. 2023
  • Characterization of Mg-ion-implanted GaN after low-temperature annealing
    Yuliu Luo; Yuki Hatakeyama; Masamichi Akazawa
    2023 JSAP Fall Meeting, 21 Sep. 2023, Japanese, Poster presentation
    20 Sep. 2023 - 23 Sep. 2023, 33660220
  • Insulator-dependence of interface properties of p-GaN MOS structures
    Jiao Yining, Takahide Nukariya, Masamichi Akazawa
    2023 JSAP Fall Meeting, 21 Sep. 2023, Japanese, Poster presentation
    20 Sep. 2023 - 23 Sep. 2023, 33660220
  • Effects of Long-Term Low-Temperature Annealing on Lightly Mg-Implanted GaN
    M. Akazawa; Y. Luo; Y. Hatakeyama
    21st International Workshop on Junction Technology (IWJT2023, Kyoto University, Kyoto, Japan, June 8-9, 2023), 08 Jun. 2023, JSAP, English, Oral presentation
    08 Jun. 2023 - 09 Jun. 2023, Kyoto University, Kyoto, Japan, Japan, 33660220, [International presentation]
  • Effects of PEC etching for Fermi-level pinning in AlGaN/GaN HEMTs
    Ryota Ochi; Takuya Togashi; Yoshito Osawa; Fumimasa Horikiri; Noboru Fukuhara; Masamichi Akazawa; Taketomo Sato
    2023 JSAP Spring Meeting, 17 Mar. 2023, Japanese, Oral presentation
    15 Mar. 2023 - 18 Mar. 2023
  • Sub-bandgap-light-assisted C-V characteristics of MOS structure with Mg-doped p-GaN
    akahide Nukariya; Yuya Tamamura; Kouta Kubo; Umi Takatsu; Taketomo Sato; Masamichi Akazawa
    2023 JSAP Spring Meeting, 16 Mar. 2023, Japanese, Poster presentation
    15 Mar. 2023 - 18 Mar. 2023, 33660220
  • Evaluation of gap-states near conduction band in the vicinity of MOS interface for Mg-ion-implanted GaN after ultra-high-pressure annealing
    Yuki Hatakeyama; Masamichi Akazawa; Tetsuo Narita; Michal Bockowski; Tetsu Kachi
    2023 JSAP Spring Meeting, 16 Mar. 2023, Japanese, Poster presentation
    15 Mar. 2023 - 18 Mar. 2023, 33660220, [Domestic Conference], ［Internationally co-authored］
  • Impact of ultra-high-pressure annealing on interface state density distribution near conduction band at Al2O3/Mg-ion-implanted GaN interface
    Y. Hatakeyama; M. Akazawa; T. Narita; M. Bockowski; T. Kachi
    15th International Symposium on Advanced Plasma Science and its Applications for Nitrides and Nanomaterials/ 16th International Conference on Plasma-Nano Technology & Science (ISPlasam2023/IC-PLANTS2023, Gifu University, Gifu, Japan, March 5–9, 2023), 07 Mar. 2023, English, Poster presentation
    05 Mar. 2023 - 09 Mar. 2023, Gifu, Japan, 33660220;13864903, [International presentation], ［Internationally co-authored］
  • Impact of photoelectrochemical etching on Al2O3/p-GaN interface
    M. Akazawa; T. Nukariya; Y. Tamamura; K. Kubo; T. Sato
    2022 Internationa Workshop on Nitride Semiconductors (IWN2022), 10 Oct. 2022, English, Poster presentation
    09 Oct. 2022 - 14 Oct. 2022, Berlin, Germany, 33660220, [International presentation]
  • Interface control of GaN MOS structures for power transistors
    T. Hashizume; M. Akazawa
    2022 JSAP Fall Meeting Symposium, 21 Sep. 2022, Japanese, Invited oral presentation
    20 Sep. 2022 - 23 Sep. 2022, 仙台市, [Invited], [Domestic Conference]
  • Characterization of interface states near conduction band in lightly Mg-implanted GaN after high-temperature cap annealing using n-GaN MOS structure
    Yuki Hatakeyama; Masamichi Akazawa
    2022 JSAP Fall Meeting, 20 Sep. 2022, Japanese, Poster presentation
    20 Sep. 2022 - 23 Sep. 2022, 仙台市, 33660220, [Domestic Conference]
  • Effects of photo-electrochemical etching on C-V characteristics of MOS structure with Mg-doped p-GaN
    Takahide Nukariya; Yuya Tamamura; Kouta Kubo; Taketomo Sato; Masamichi Akazawa
    2022 JSAP Fall Meeting, 20 Sep. 2022, Japanese, Poster presentation
    20 Sep. 2022 - 23 Sep. 2022, 33660220, [Domestic Conference]
  • Effects of defect levels in vicinity of GaN surface on C-V characteristics of MOS structure with Mg-doped p-GaN (2)
    Yuya Tamamura; Takahide Nukariya; Masamichi Akazawa
    2022 JSAP Fall Meeting, 20 Sep. 2022, Japanese, Poster presentation
    20 Sep. 2022 - 23 Sep. 2022, 仙台市, 33660220, [Domestic Conference]
  • Effects of defect levels in vicinity of GaN surface on C-V characteristics of MOS structure with Mg-doped p-GaN
    Yuya Tamamura; Takahide Nukariya; Masamichi Akazawa
    2022 JSAP Spring Meeting, 24 Mar. 2022, Japanese, Poster presentation
    22 Mar. 2022 - 26 Mar. 2022, 相模原市, 33660220, [Domestic Conference]
  • Photo-assisted C–V measurement of p-GaN MOS diodes
    Y. Tamamura; T. Nukariya; M. Akazawa
    14th International Symposium on Advanced Science and its Application for Nitrides and Nanomaterials/15th International Conference on Plasma Nanotechnology and Science (ISPlasam2022/IC-PLANTS2022), 09 Mar. 2022, English, Poster presentation
    06 Mar. 2022 - 10 Mar. 2022, 33660220, [International presentation]
  • Detection of Interstitial-Defect Levels in Mg-Ion-Implanted GaN Using MOS Diodes
    M. Akazawa; Shunta Murai; Yuya Tamamura
    31th International Conference on Defects in Semiconductors (ICDS 2017), 29 Jul. 2021, English, Poster presentation
    26 Jul. 2021 - 30 Jul. 2021, 33660220, [International presentation]
  • A Defect Level Generated in GaN by High-Temperature Annealing with AlN Encapsulation
    M. Akazawa; Yuya Tamamura; S. Murai
    13th International Symposium on Advanced Science and its Application for Nitrides and Nanomaterials/14th International Conference on Plasma Nanotechnology and Science (ISPlasam2021/IC-PLANTS2021), 09 Mar. 2021, English, Poster presentation
    07 Mar. 2021 - 11 Mar. 2021, 13864903, [International presentation]
  • Encapsulant Dependent Effect of Low-Temperature Annealing on Mg-Ion-Implanted GaN
    Shunta Murai; Encheng Wu; Masamichi Akazawa; Tetsu Kachi
    2020 JSAP Meeting, 10 Sep. 2020, Japanese, Oral presentation
    08 Sep. 2020 - 11 Sep. 2020, online, 33660220
  • Impact of Cap-Layer Materials Used in Long-Term Low-Temperature Annealing on Electrical Properties of Mg-Ion Implanted GaN
    M. Akazawa; S. Murai; R. Kamoshida; E. Wu; T. Kachi
    62nd Electronic Materials Conference (EMC2020, Virtual Holding, June 24-26, 2020), 25 Jun. 2020, English, Poster presentation
    24 Jun. 2020 - 26 Jun. 2020, 13864903
  • Effects of Long-Term Low-Temperature Annealing on Mg-Ion Implanted GaN
    Shunta Murai; Ryo Kamoshida; M. Akazawa
    The 9th Asia-Pacific Workshop on Widegap Semiconductors (APWS2019, Okinawa Institute of Science and Technology Graduate University, Okinawa, Japan, Nov. 10 – 15, 2019)., 14 Nov. 2019, English, Poster presentation
    [International presentation]
  • Effects of Surface Oxide Reduction Prior to Metallization on Electrical Properties of GaN-on-GaN Schottky Diodes
    K. Isobe; M. Akazawa
    The 9th Asia-Pacific Workshop on Widegap Semiconductors (APWS2019, Okinawa Institute of Science and Technology Graduate University, Okinawa, Japan, Nov. 10 – 15, 2019)., 12 Nov. 2019, English, Poster presentation
    [International presentation]
  • XPS Study on Plasma Oxide Layer of InAlN
    Yuya Kitawaki; Masamichi Akazawa
    The 80th JSAP Autumn Meeting 2019, 18 Sep. 2019, Japanese, Poster presentation
    [Domestic Conference]
  • Effects of Long-Term Low-Temperature annealing on Mg-Ion Implanted GaN
    Shunta Murai; Ryo Kamoshida; Masamichi Akazawa
    The 80th JSAP Autumn Meeting 2019, 18 Sep. 2019, Japanese, Poster presentation
    [Domestic Conference]
  • Analysis of Interface-State Admittance of MOS Diodes Constructed of Mg-Ion-Implanted GaN
    Ryo Kamoshida; Shunta Murai; Masamichi Akazawa
    The 80th JSAP Autumn Meeting 201809, 18 Sep. 2019, Japanese, Oral presentation
    [Domestic Conference]
  • Impact of Photolithography Development Process on GaN Schottky Barrier Diode
    Kazuki Isobe; Masamichi Akazawa
    The 80th JSAP Autumn Meeting 2019, 18 Sep. 2019, Japanese, Poster presentation
    [Domestic Conference]
  • Effects of Deep Level States Generated by Mg-Ion Implantation on Electrical Properties of GaN MOS Diodes before Activation Annealing
    R. Kamoshida; S. Murai; M. Akazawa
    2019 International Conference on Solid State Devices and Materials (SSDM2019, Nagoya University, Nagoya, Japan, Sept. 2 – 5, 2019), 04 Sep. 2019, English, Poster presentation
    [International presentation]
  • Detection of Deep Level States Generated in GaN by Mg-Ion Implantation Using Conductance Method for MOS Diodes
    M. Akazawa; R. Kamoshida
    13th International Conference on Nitride Semiconductors (ICNS-13, Hyatt Regency Bellevue, Bellevue, Washington, USA, July 7-12, 2019), 09 Jul. 2019, English, Poster presentation
    [International presentation]
  • Investigation of Impact of Dosage on Electrical Properties of Mg-Ion-Implanted GaN before Activation Annealing Using MOS Structures
    Ryo Kamoshida; Kei Uetake; Shunta Murai; Masamichi Akazawa
    Compound Semiconductor Week 2019 (CSW219, Kasugano International Forum, Nara, Japan, May 19 – 23, 2019), 21 May 2019, English, Poster presentation
    [International presentation]
  • Control of SiO2/InAlN Interface by Plasma Surface Oxidation
    Shouhei Kitajima; Masamichi Akazawa
    11th International Symposium on Advanced Science and its Appliaction for Nitrides and Nanomaterials/12th International Conference on Plasma-Nano Technology & Science (ISPlasam2019/IC-PLANTS2019, Nagoya Institute of Technology, Nagoya, Japan, March 17-20), 18 Mar. 2019, English, Poster presentation
    [International presentation]
  • Impact of Dosage on Electrical Properties of Mg-Ion-Implanted GaN before High-Temperature Annealing (2)
    Ryo Kamoshida; Kei Uetake; Shunta Murai; Masamichi Akazawa
    The 66th JSAP Spring Meting 2019, 09 Mar. 2019, Japanese, Poster presentation
    [Domestic Conference]
  • Impact of Surface Treatment on GaN-on-GaN Schottky Barrier Diode
    Kazuki Isobe; Masamichi Akazawa
    The 66th JSAP Spring Meeting 2019, 09 Mar. 2019, Japanese, Poster presentation
    [Domestic Conference]
  • Investigation of Effect of Low-Temperature Annealing and Dosage on Mg-Ion-Implanted GaN Using MOS Structure
    Kei Uetake; Ryo Kamoshida; Masamichi Akazawa
    International Workshop on Nitride Semiconductors 2018 (IWN2018, Kanazawa, Ishikawa, Japan, November 11 - 16, 2018), 11 Nov. 2018, English, Poster presentation
    [International presentation]
  • Investigation of Surface Pretreatment for Schottky Contacts on n-GaN on GaN Substrate
    Kazuki Isobe; Masamichi Akazawa
    14th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures (ACSIN-14) in conjunction with 26th International Colloquium on Scanning Probe Microscopy (ICSPM26), 23 Oct. 2018, English, Poster presentation
    [International presentation]
  • Control of SiO2/InAlN Interface Using Sub-nm-Thick Al2O3 Interlayer
    Shouhei Kitajima; Masamichi Akazawa
    14th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures (ACSIN-14) in conjunction with 26th International Colloquium on Scanning Probe Microscopy (ICSPM26), 22 Oct. 2018, English, Poster presentation
    [International presentation]
  • Investigation of Lightly Mg-Ion-Implanted GaN Using MOS Structure
    Masamichi Akazawa; Kei Uetake; Ryo Kamoshida
    The 79th JSAP Autumn Meeting, 2018, 19 Sep. 2018, English, Invited oral presentation
    [Invited], [Domestic Conference]
  • Properties of SiO2/InAlN interface having ultrathin Al2O3 interlayer (2)
    Shouhei Kitajima; Masamichi Akazawa
    The 79th JSAP Autumn Meeting, 2018, 18 Sep. 2018, Japanese, Poster presentation
    [Domestic Conference]
  • Impact of Dosage on Electrical Properties of Mg-Ion-Implanted GaN before High-Temperature Annealing
    Ryo Kamoshida; Kei Uetake; Masamichi Akazawa
    The 79th JSAP Autumn Meeting, 2018, 18 Sep. 2018, Japanese, Poster presentation
    [Domestic Conference]
  • Impact of Surface Treatment for GaN on Surface Fermi Level Position and Metal-Work-Function Dependence of Schottky Barrier Height
    Kazuki Isobe; Masamichi Akazawa
    The 79th JSAP Autumn Meeting, 2018, 18 Sep. 2018, Japanese, Poster presentation
    [Domestic Conference]
  • Thermal behavior of defects generated in GaN by low-dose Mg-ion implantation
    Masamichi Akazawa; Naoshige Yokota; Kei Uetake
    Compound Semiconductor Week 2018, 28 May 2018, English, Poster presentation
    [International presentation]
  • Change in electrical properties of Mg-ion implanted GaN by annealing (2)
    Kei uetake; Naoshige Yokota; Masamichi Akazawa
    The 65th JSAP Spring Meeting, 2018, 19 Mar. 2018, Japanese, Oral presentation
    [Domestic Conference]
  • Properties of SiO2/InAlN interface having plasma oxide interlayer
    Shouhei Kitajima; Masamichi Akazawa
    The 65th JSAP Spring Meeting, 2018, 17 Mar. 2018, Japanese, Poster presentation
    [Domestic Conference]
  • Properties of SiO2/InAlN interface having Al2O3 and plasma oxide ultra thin interlayer
    Shouhei Kitajima; Masamichi Akazawa
    The 53th JSAP Hokkaido Branch Annual Meeting, 06 Jan. 2018, Japanese, Oral presentation
    [Domestic Conference]
  • Properties of SiO2/InAlN interface having ultrathin Al2O3 interlayer
    S. Kitajima; M. Akazawa
    The 78th JSAP Autum Meeting, 2017, 07 Sep. 2017, Japanese, Poster presentation
    [Domestic Conference]
  • Change in electrical properties of Mg-ion implanted GaN by annealing
    N. Yokota; K. Uetake; M. Akazawa
    The 78th JSAP Autum Meeting, 2017, 07 Sep. 2017, Japanese, Oral presentation
    [Domestic Conference]
  • Change in properties of GaN Schottky barrier diodes by insertion of ultrathin insulator layers
    T. Hasezaki; M. Akazawa
    The 78th JSAP Autum Meeting, 2017, 07 Sep. 2017, Japanese, Poster presentation
    [Domestic Conference]
  • Measurement of Electronic States Generated in GaN by Mg Ion Implantation
    N. Yokota; K. Uetake; M. Akazawa
    29th International Conference on Defects in Semiconductors (ICDS 2017, Matsue, Shimane, Japan, July 31 – Aug. 4, 2017), 31 Jul. 2017, English, Poster presentation
    [International presentation]
  • Modification of Fermi-level pinning at metal/GaN interface by inserting ultrathin Al2O3 interlayers
    M. Akazawa; T. Hasezaki
    12th International Conference on Nitride Semiconductors (ICNS-12, Strasbourg, France, July 24-28, 2017), 24 Jul. 2017, English, Poster presentation
    [International presentation]
  • Properties of SiO2/InAlN interface with Al2O3 ultrathin interlayers
    A. Seino; M. Akazawa
    The 64th JSAP Spring Meeting, 2017, 16 Mar. 2017, Japanese, Poster presentation
    [Domestic Conference]
  • Electrical characterization of electron levels generated in GaN by Mg ion implantation
    N. Yokota; M. Akazawa
    The 64th JSAP Spring Meeting, 2017, 16 Mar. 2017, Japanese, Oral presentation
    [Domestic Conference]
  • Change of GaN Schottky barrier height by insertion of ultrathin Al2O3 layers
    T. Hasezaki; M. Akazawa
    The 64th JSAP Spring Meeting, 2017, 16 Mar. 2017, Japanese, Poster presentation
    [Domestic Conference]
  • Reduction of Interface State Density at SiO2/InAlN Interface by Inserting Ultrathin Interlayers
    M. Akazawa; A. Seino; N. Yokota; T. Hasezaki
    International Workshop on Nitride Semiconductors 2016 (IWN2016, Hilton Orlando Lake Buena Vista, Orlando, Florida, USA, October 2 - 7, 2016), 05 Oct. 2016, English, Poster presentation
    [International presentation]
  • Properties of SiO2/InAlN Interface with Plasma Oxide Interlayer
    Atsushi Seino; Naoshige Yokota; Masamichi Akazawa
    The 77th JSAP Autumn Meeting, 2016, 14 Sep. 2016, Japanese, Poster presentation
    [Domestic Conference]
  • Effect of Insertion of Al2O3 Ultrathin Layer into PECVD SiO2/InAlN Interface
    A. Seino; T. Hasezaki; N. Yokota; M. Akazawa
    The 63rd JSAP Spring Meeting, 2016, 20 Mar. 2016, Japanese, Poster presentation
    [Domestic Conference]
  • Characterization of Surfaces and Interfaces of InAlN
    Masamichi Akazawa
    2016 RCIQE International Seminar, 08 Mar. 2016, English, Invited oral presentation
    [International presentation]
  • Nature and Origin of Interface States at Dielectric/III-N Heterojunction Interfaces
    Maciej Matys; Boguslawa Adamowicz; Roman Stoklas; Masamichi Akazawa; Zenji Yatabe; Tamotsu Hashizume
    2015 MRS Fall Meeting & Exhibit, 29 Nov. 2015, English, Poster presentation
    [International presentation]
  • Characterization of SiO2/InAlN Interface Formed by Plasma Enhanced CVD
    A. Seino; M. Akazawa
    The 76th JSAP Fall Meeting, 13 Sep. 2015, Japanese, Poster presentation
    [Domestic Conference]
  • [Invited] Characterization of Surfaces and Interfaces of InAlN/GaN Heterostructures
    M. Akazawa; T. Hashizume
    11th International Conference on Nitride Semiconductors (ICNS-11, Beijing, China, Aug. 30 - Sept. 4, 2015), 30 Aug. 2015, English, Invited oral presentation
    [International presentation]
  • Process Dependence of Al2O3/InAlN Interface Properties
    M. Chiba; M. Akazawa
    The 62nd JSAP Spring Meeting, 11 Mar. 2015, Japanese, Poster presentation
    [Domestic Conference]
  • Application of Al2O3/InAlN interface formed by 2-step ALD to MOSHEMT
    Y. Odanagi; M. Akazawa; J. T. Asubar; Z. Yatabe; T. Hashizume
    The 75th JSAP Fall Meeting, 17 Sep. 2014, Japanese, Poster presentation
    [Domestic Conference]
  • Impact of Annealing on Properties of ALD Al2O3/InAlN Interfaces
    M. Akazawa; T. Nakano; M. Chiba
    56th Electronic Materials Conference (EMC56, UCSB, Santa Barbara, California, USA, June 25-27, 2014), 25 Jun. 2014, English, Oral presentation
    [International presentation]
  • Process-dependent properties of InAlN surface and ALD-Al2O3/InAlN interface
    M. Akazawa; M. Chiba; T. Nakano
    2014 International Conference on Compound Semiconductor Manufacturing Technology (CSMANTECH 2014, Sheraton Downtown Denver, Denver, Colorado, USA, May 19-22, 2014), 19 May 2014, Japanese, Oral presentation
    [International presentation]
  • Properties of Al2O3/InAlN interface formed by 2-step ALD
    T. Nakano; M. Chiba; Y. Odanagi; M. Akazawa
    The 61st JSAP Spring Meeting, 17 Mar. 2014, Japanese, Oral presentation
    [Domestic Conference]
  • Effect of annealing on properties of InAlN MOS diodes with ALD-Al2O3 insulator layer
    M. Chiba; T. Nakano; M. Akazawa
    The 61st JSAP Spring Meeting, 17 Mar. 2014, Japanese, Oral presentation
    [Domestic Conference]
  • [Invited] Characterization and control of GaN-based heterointerfaces
    T. Sato; M. Akazawa; T. Hashizume
    The 61st JSAP Spring Meeting, 17 Mar. 2014, Japanese, Invited oral presentation
    [Invited], [Domestic Conference]
  • Investigation of High-Temperature Annealed ALD-Al2O3/InAlN Interface
    M. Akazawa; T. Nakano; M. Chiba
    12th International Conference on Atomically Controlled Surfaces, Interfaces and Nanostructures in conjunction with 21st International Conference on Scanning Probe Microscopy (ACSIN-12 & ICSPM21, Tsukuba, Japan, November 4 - 8, 2013), 07 Nov. 2013, English, Poster presentation
    [International presentation]
  • Effects of Fabrication Process on Electrical Properties of InAlN MOS Structures with ALD-Al2O3
    M. Chiba; T. Nakano; M. Akazawa
    The Technical Committee on Electron Devices, IEICE, JAPAN, 13 Oct. 2013, Japanese, Oral presentation
    [Domestic Conference]
  • Effects of High-Temperature Annealing on Properties of Al2O3/InAlN Interface Formed by Atomic Layer Deposition
    T. Nakano; M. Chiba; M. Akazawa
    2013 International Conference on Solid State Devices and Materials (SSDM2013, Hilton Fukuoka Sea Hawk, Fukuoka, Japan, Sept. 25-27, 2013), 26 Sep. 2013, English, Poster presentation
    [International presentation]
  • Study on Fabrication Sequence of InAlN MOS Diodes with ALD-Al2O3 Insulator Layer
    M. Chiba; T. Nakano; M. Akazawa
    The 74th JSAP Fall Meeting, 16 Sep. 2013, Japanese, Oral presentation
    [Domestic Conference]
  • Improvement of Al2O3/InAlN interface properties through two-step ALD process interrupted by high-temperature annealing
    T. Nakano; M. Chiba; M. Akazawa
    The 74th JSAP Fall Meeting, 16 Sep. 2013, Japanese, Oral presentation
    [Domestic Conference]
  • Dependence of ALD-Al2O3/InAlN interface properties on fabrication process
    T. Nakano; M. Chiba; M. Akazawa
    10th International Conference on Nitride Semiconductors (ICNS-10, Washington, DC, Aug. 25-30, 2013), 26 Aug. 2013, English, Poster presentation
    [International presentation]
  • Characterization and Control of insulated Gate Interface on GaN-Based heterostructures (invited)
    T. Hashizume; M. Akazawa
    2013 International Conference on Compound Semiconductor Manufacturing Technology, p.329-332 (CS MANTEC2013, Hilton New Orleans Riverside, New Orleans, Louisiana, USA, May 13-16, 2013), 13 May 2013, English, Invited oral presentation
    [Invited], [International presentation]
  • Effect of annealing on ALD-Al2O3/InAlN interface
    T. Nakano; M. Akazawa
    JSAP Srping Meeting, 2013, 28 Mar. 2013, Japanese, Oral presentation
    [Domestic Conference]
  • Characterization and control of surfaces and interfaces of InAlN/GaN heterostructures
    M. Akazawa; T. Hashizume
    The 60th JSAP Spring Meeting, 2013, 27 Mar. 2013, Japanese, Oral presentation
    [Invited], [Domestic Conference]
  • Insulated gate technologies for high-performance GaN transistors (invited)
    T. Hashizume; Y. Hori; S. Kim; Z. Yatabe; M. Akazawa
    International Workshop on Nitride Semiconductors 2012 (IWN2012, Sapporo, Japan, October 14 - 19, 2012), 18 Oct. 2012, English, Invited oral presentation
    [Invited], [International presentation]
  • Effects of surface treatment on InAlN investigated by X-ray photoelectron spectroscopy
    M. Akazawa; T. Nakano
    International Workshop on Nitride Semiconductors 2012 (IWN2012, Sapporo, Japan, October 14 - 19, 2012), 16 Oct. 2012, English, Poster presentation
    [International presentation]
  • InAlN表面に対する弗化水素酸処理の効果
    中野拓真; 赤澤正道
    応用物理学会学術講演会講演予稿集(CD−ROM), 27 Aug. 2012, Japanese
  • Interface characterization of AlInN/GaN heterostructures
    HASHIZUME TAMOTSU; HORI YUJIN; AKAZAWA MASAMICHI
    電子情報通信学会技術研究報告, 19 Jul. 2012, Japanese
  • 溶液処理によるInAlN表面自然酸化膜の除去
    中野拓真; 赤澤正道
    応用物理学関係連合講演会講演予稿集(CD−ROM), 29 Feb. 2012, Japanese
  • Effect of hydrofluoric acid treatment on InAlN surfaces
    T. Nakano; M. Akazawa
    2012 Asia-Pacific Workshop on Fundamental and Applications of Advanced Semiconductor Devices (AWAD2012, Naha, Okinawa, Japan, June 27-29, 2012), 28 Jan. 2012, English, Poster presentation
    [International presentation]
  • InドープしたMOVPE成長AlGaN膜の内部電界
    赤澤正道; 赤澤正道; GAO B; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM), 16 Aug. 2011, Japanese
  • Al2O3/InAlN/AlGaN/GaN構造におけるAlGaNスペーサ層の検討
    GAO B; 赤澤正道; 赤澤正道; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM), 16 Aug. 2011, Japanese
  • Optimum AlGaN Spacer Layer in Al2O3/InAlN/AlGaN/GaN Structures
    M. Akazawa; B. Gao; T. Hashizume; M. Hiroki; S. Yamahata; N. Shigekawa
    9th International Conference on Nitride Semiconductors (ICNS-9, Glasgow, UK, July 10-15, 2011), 12 Jul. 2011, English, Poster presentation
    [International presentation]
  • Al2O3/InAlN/AlGaN/AlN/GaN構造のC‐V特性
    GAO B; 赤澤正道; 赤澤正道; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学関係連合講演会講演予稿集(CD−ROM), 09 Mar. 2011, Japanese
  • InドープしたMOVPE成長AlGaN超薄膜内電界のXPSによる評価
    赤澤正道; 赤澤正道; GAO B; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学関係連合講演会講演予稿集(CD−ROM), 09 Mar. 2011, Japanese
  • Investigation of polarization-induced electric field in ultrathin InAlN films on GaN by X-ray photoelectron spectroscopy
    M. Akazawa; B. Gao; T. Hashizume; M. Hiroki; S. Yamahata; N. Shigekawa
    International Workshop on Nitride Semiconductors 2010 (IWN2010, Tampa, Florida, USA, September 19 - 24, 2010), 23 Sep. 2010, English, Poster presentation
    [International presentation]
  • XPSによるGaN上極薄InAlN内分極誘起電界の検出
    GAO MB; 赤澤正道; 赤澤正道; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM), 30 Aug. 2010, Japanese
  • XPSによるInxAl1−xN/GaN界面の価電子帯不連続量の評価
    赤澤正道; 赤澤正道; GAO MB; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学会学術講演会講演予稿集(CD−ROM), 30 Aug. 2010, Japanese
  • In0.17Al0.83N/GaNヘテロ界面のXPS観察
    赤澤正道; 赤澤正道; 橋詰保; 橋詰保; 廣木正伸; 山幡章司; 重川直輝
    応用物理学関係連合講演会講演予稿集(CD−ROM), 03 Mar. 2010, Japanese
  • MOS Interface Control on III-V High Mobility Channel Materials (invited)
    H. Hasegawa; M. Akazawa
    37th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-35, Santa Fe, New Mexico, USA, January 10-14, 2010), 11 Jan. 2010, English, Invited oral presentation
    [Invited], [International presentation]
  • Fermi level Pinning and Its Removal at III-V MOS Interfaces (invited)
    H. Hasegawa; M. Akazawa
    40th IEEE Semiconductor Interface Specialists Conference (Key Bridge Marriott Hotel, Arlington, VA, USA, December 3-5, 2009), 03 Dec. 2009, English, Invited oral presentation
    [Invited], [International presentation]
  • Surface Passivation of III-V Semiconductors for More Moore and Beyond CMOS Devices - present status and key issues – (invited)
    H. Hasegawa; M. Akazawa
    6th International Workshop on Semiconductor Surface Passivation (Zakopane, Poland, September 13-18, 2009), 17 Sep. 2009, English, Invited oral presentation
    [Invited], [International presentation]
  • Formation of High-k MOS Structures with Si Interface Control Layer on Air-Exposed GaAs and InGaAs Wafers
    M. Akazawa; H. Hasegawa
    6th International Workshop on Semiconductor Surface Passivation (Zakopane, Poland, September 13-18, 2009), 16 Sep. 2009, English, Poster presentation
    [International presentation]
  • Slow Dispersive Hopping Transport of Electrons on Surfaces of AlGaN/GaN HEMTs and Planar Schottky Diodes
    H. Hasegawa; M. Akazawa
    12th International Conference on the Formation of Semiconductor Interfaces (ICFSI-12, Weimar, Germany, July 5-10, 2009), 09 Jul. 2009, English, Oral presentation
    [International presentation]
  • Control of Interface between HfO2 and Air-Eexposed InGaAs by Ultrathin Si Interface Control Layer
    M. Akazawa; H. Hasegawa
    12th International Conference on the Formation of Semiconductor Interfaces (ICFSI-12, Weimar, Germany, July 5-10, 2009), 08 Jul. 2009, English, Poster presentation
    [International presentation]
  • On the Frequency Dispersion of III-V MOS C-V Curves
    H. Hasegawa; M. Akazawa
    33rd Workshop on Compound Semiconductor Device and Integrated Circuits held in Europe (WOCSDICE2009, Málaga, Spain, May 17-20, 2009), 19 May 2009, English, Oral presentation
    [International presentation]
  • Anomalous Admittance Behavior of III-V Insulator-Semiconductor Interfaces and Its Mechanism
    H. Hasegawa; M. Akazawa
    Symposium on Surface and Nano Science 2009 (SSNS’09, Shizukuishi Prince Hotel, Shizukuishi, Iwate, Japan, January 27-30, 2009), 28 Jan. 2009, English, Oral presentation
    [International presentation]
  • Current Collapse Transient Behavior and Its Mechanism in Submicron-Gate AlGaN /GaN Heterostructure Transistors
    H. Hasegawa; M. Akazawa
    36th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-36, Santa Barbara, California, USA, January 11-15, 2009), 13 Jan. 2009, English, Oral presentation
    [International presentation]
  • Capacitance-Voltage and Photoluminescence Study of High-k /III-V Semiconductor Interfaces Controlled by Si Interface Control Layer
    M. Akazawa; M. Miczek; B. Adamowicz; H. Hasegawa
    36th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-36, Santa Barbara, California, USA, January 11-15, 2009), 13 Jan. 2009, English, Oral presentation
    [International presentation]
  • Distributed Pinning Spot Model for High-k Insulator - III-V Semiconductor Interface
    M. Akazawa; H. Hasegawa
    International Symposium on Surface Science and Technology (ISSS-5, Waseda University, Tokyo, Japan, November 9-13, 2008), 11 Nov. 2008, English, Poster presentation
    [International presentation]
  • Characterization and Control of Group-III Nitride Surfaces for Power Electronics and Sensor Electronics [invited]
    H. Hasegawa; M. Akazawa
    14th International Symposium on the Physics of Semiconductors and Applications (ISPSA2008, Jeju, Korea, August 26-29, 2008), 27 Aug. 2008, English, Invited oral presentation
    [Invited], [International presentation]
  • Anomalous Behavior of Capacitance and Conductance of III-V Metal- Insulator- Semiconductor Capacitors
    M. Akazawa; H. Hasegawa
    2008 Electronic Material Conference (EMC2008, University of California Santa Barbara, California, USA, June 25-27, 2008), 27 Jun. 2008, English, Oral presentation
    [International presentation]
  • Slow Response Instability in the Planar Pd Schottky Diode Hydrogen Sensor Formed on AlGaN/GaN Wafer
    H. Hasegawa; M. Akazawa
    2008 Electronic Material Conference (EMC2008, University of California Santa Barbara, California, USA, June 25-27, 2008), 25 Jun. 2008, English, Oral presentation
    [International presentation]
  • Optimization of Si Interface Control Layer Thickness for High-k GaAs Metal-Insulator-Semiconductor Structures
    M. Akazawa; H. Hasegawa
    9th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC2008, Lodz, Poland, June 1- 4, 2008), 03 Jun. 2008, English, Oral presentation
    [International presentation]
  • Control of Surfaces and Interfaces for III-V Semiconductor Nanoelectronics [invited]
    H. Hasegawa; M. Akazawa
    9th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC2008, Lodz, Poland, June 1- 4, 2008), 02 Jun. 2008, English, Invited oral presentation
    [Invited], [International presentation]
  • SURFACE STATE EFFECTS AND SURFACE PASSIVATION WITH A SILICON INTERFACE CONTROL LAYER FOR III-V NANOWIRE TRANSISTORS
    H. Hasegawa; M. Akazawa
    32nd Workshop on Compound Semiconductor Device and Integrated Circuits held in Europe (WOCSDICE2008, Leuven, Belgium, May 18-21, 2008), 19 May 2008, English, Oral presentation
    [International presentation]
  • AlGaN/GaNプレーナ・ショットキダイオードの低速分散性過渡応答‐電流コラプスの新モデル‐
    長谷川英機; 赤澤正道
    応用物理学関係連合講演会講演予稿集, 27 Mar. 2008, Japanese
  • シリコン界面制御層を有するGaAs高誘電体MISキャパシタのアドミッタンス
    赤澤正道; 長谷川英機
    応用物理学関係連合講演会講演予稿集, 27 Mar. 2008, Japanese
  • Interface Control of High-k MOS Gate Stack for GaAs nanowire Transistors
    H. Hasegawa; M. Akazawa
    Symposium on Surface and Nano Science 2008 (SSNS’08, Appi-Kougen, Iwate, Japan, January 22-25, 2008), 23 Jan. 2008, English, Oral presentation
    [International presentation]
  • Steady State and Transient Behavior of Currents in Low-Leakage Planar Schottky Diodes Formed on AlGaN /GaN Heterostructures
    H. Hasegawa; M. Akazawa
    35th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-35, Santa Fe, New Mexico, USA, January 13-17, 2008),, 15 Jan. 2008, English, Oral presentation
    [International presentation]
  • Frequency Dispersion of GaAs High-k MIS Capacitors with Si Interface Control Layer
    M. Akazawa; H. Hasegawa
    35th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-35, Santa Fe, New Mexico, USA, January 13-17, 2008), 15 Jan. 2008, English, Oral presentation
    [International presentation]
  • Silicon Interface Control Layer Based Surface Passivation Method and Related High-k MIS Gate Stack for GaAs Nanowire MISFETs
    M. Akazawa; H. Hasegawa
    International Symposium on Advanced nanodevices and Nanotechnology (ISANN2007, Waikoloa, Hawaii, USA, December 2-7, 2007), 06 Dec. 2007, English, Oral presentation
    [International presentation]
  • GaAs High-k Dielectric MOS Structure Having Silicon Interface Control Layer
    M. Akazawa; H. Hasegawa
    34th International Symposium on Compound Semiconductor (iscs2007, Kyoto, Japan, October 15-18, 2007), 16 Oct. 2007, English, Poster presentation
    [International presentation]
  • Dynamic behavior of metal contacts formed on AlGaN/GaN heterostructure
    H. Hasegawa; M. Akazawa
    7th International Conference on Nitride Semiconductor (ICNS-7, Las Vegas, Nevada, USA, September 16-21, 2007), 20 Sep. 2007, English, Poster presentation
    [International presentation]
  • Sensing and current transport mechanisms of a high performance Pd/AlGaN/GaN Schottky diode hydrogen sensor
    M. Akazawa; H. Hasegawa
    7th International Conference on Nitride Semiconductor (ICNS-7, Las Vegas, Nevada, USA, September 16-21, 2007), 18 Sep. 2007, English, Poster presentation
    [International presentation]
  • Interface Control Technology for Surface Passivation of III-V Semiconductor Nanostructures (invited)
    H. Hasegawa; M. Akazawa
    5th International Workshop on Semiconductor Surface Passivation (Zakopane, CRC Geovita, Poland, September 16-19, 2007), 17 Sep. 2007, English, Invited oral presentation
    [Invited], [International presentation]
  • Pd/AlGaN/GaNショットキーダイオード形水素センサの大気中動作特性
    赤澤正道; 長谷川英機
    応用物理学会学術講演会講演予稿集, 04 Sep. 2007, Japanese
  • Si界面制御層によるHfO2/GaAs界面の制御
    赤澤正道; 長谷川英機
    応用物理学会学術講演会講演予稿集, 04 Sep. 2007, Japanese
  • Surface passivation technology for III-V semiconductor nanoelectronics (invited)
    H. Hasegawa; M. Akazawa
    11th International Conference on the Formation of Semiconductor Interfaces (ICFSI-11, Manaus-Amazonas, Brazil, August 19-24, 2007), 20 Aug. 2007, English, Invited oral presentation
    [Invited], [International presentation]
  • Complete Removal of Fermi Level Pinning at High-k Dielectric/GaAs (001) and (111)B Interfaces by a Silicon Interface Control Layer
    M. Akazawa; H. Hasegawa
    2007 Electronic Material Conference (EMC2007, University of Notre Dame, South Bend, Indiana, USA, June 20-22, 2007), 21 Jun. 2007, English, Oral presentation
    [International presentation]
  • Performance Enhancement and Sensing Mechanism of Pd/AlGaN/GaN Hydrogen Sensors Subjected to Oxygen Gettering
    H. Hasegawa; M. Akazawa
    2007 Electronic Material Conference (EMC2007, University of Notre Dame, South Bend, Indiana, USA, June 20-22, 2007), 21 Jun. 2007, English, Oral presentation
    [International presentation]
  • Passivation of III-V Surface by Si Interface Control Layer and Its Application of high-k MIS Gate Stack (invited)
    H. Hasegawa; M. Akazawa
    Interntional Workshop on High-k Dielectrics on High Speed Channel Materials, Hinsiu, Taiwan, May 24-25, 2007, 24 May 2007, English, Invited oral presentation
    [Invited], [International presentation]
  • MBE growth and in-situ XPS characterization of silicon interlayers for surfaces passivation of GaAs quantum devices
    M. Akazawa; H. Hasegawa
    2007 RCIQE International Seminar on "Advanced Semiconductor Materials and Devices," (Sapporo, Japan, February 8-9, 2007), 09 Feb. 2007, English, Invited oral presentation
    [Invited], [International presentation]
  • Control of Schottky Interfaces of AlGaN/GaN system for hydrogen sensor applications (invited)
    H. Hasegawa; M. Akazawa
    Symposium on Surface and Nano Science 2007 (SSNS’07, Appi-Kougen, Iwate, Japan, January 23-26, 2007), 24 Jan. 2007, English, Invited oral presentation
    [Invited], [International presentation]
  • Hydrogen Response Characteristics and Mechanism of Pd/ AlGaN/ GaN Schottky Diodes Subjected to Oxygen Gettering
    H. Hasegawa; M. Akazawa
    34th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-34, Salt Lake City, Utah, USA, January 14-18, 2007), 17 Jan. 2007, English, Oral presentation
    [International presentation]
  • Growth Mechanism and Fermi Level Unpinning in Silicon Interface Control Layers for Surface Passivation of (001) and (111) GaAs and AlGaAs Surfaces
    M. Akazawa; H. Hasegawa
    34th Conference on the Physics & Chemistry of Semiconductor Interfaces (PCSI-34, Salt Lake City, Utah, USA, January 14-18, 2007), 16 Jan. 2007, English, Oral presentation
    [International presentation]
  • Understanding and Control of Group-III Nitride Surfaces for Power Electronics and Sensor Electronics (invited)
    H. Hasegawa; M. Akazawa
    5th Solid State Surfaces and Interfaces (SSSI2006, Smolenice Castle, Slovak Republic, November 19-24, 2006), 20 Nov. 2006, English, Invited oral presentation
    [Invited], [International presentation]
  • Sensing Dynamics and Mechanism of a Pd/AlGaN /GaN Schottky Diode Type Hydrogen Sensor
    H. Hasegawa; M. Akazawa
    2006 International Workshop on Nitride Semiconductors (IWN2006, Kyoto, Japan, October 22-27, 2006), 24 Oct. 2006, English, Poster presentation
    [International presentation]
  • MBE Growth and In-Situ XPS Characterization of Silicon Interlayers on (111)B Surfaces for Passivation of GaAs Quantum Wire Devices
    M. Akazawa; H. Hasegawa
    14th International Conference on Molecular Beam Epitaxy (MBE2006, Tokyo, Japan, September 3-8, 2006), 07 Sep. 2006, English, Poster presentation
    [International presentation]
  • Characterization and Control of AlGaN Schottky Diodes for Performance Enchancement of Hydrogen Sensors
    H. Hasegawa; K. Matsuo; T. Kimura; J. Kotani; M. Akazawa; T. Hashizume
    8th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC'06, Cádiz, Spain, May 14- 17, 2006), 16 May 2006, English, Poster presentation
    [International presentation]
  • In-situ X-ray photoelectron spectroscopy characterization of Si interlayer based surface passivation process for AlGaAs/GaAs quantum wire transistors
    M. Akazawa; H. Hasegawa; R. Jia
    8th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC'06, Cádiz, Spain, May 14- 17, 2006), 15 May 2006, English, Oral presentation
    [International presentation]
  • THz Transmission Properties of Metal Hole-Array Filters
    Y. Yamazaki; M. Akazawa; E. Sano
    2006 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (IV)" (Sapporo, February 9-10, 2006), 10 Feb. 2006, English, Poster presentation
    [International presentation]
  • X-ray Photoelectron Spectroscopy Study of Silicon Interlayer Based Passivation for GaAs and AlGaAs (111) B Surfaces
    M. Akazawa; N. Shiozaki; H. Hasegawa
    2006 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (IV)" (Sapporo, February 9-10, 2006), 09 Feb. 2006, English, Poster presentation
    [International presentation]
  • X-ray Photoelectron Spectroscopy Study of Silicon Interlayer Based Surface Passivation for AlGaAs/GaAs Quantum Structures on (111) B Surfaces
    M. Akazawa; N. Shiozaki; H. Hasegawa
    10th International Conference on the Formation of Semiconductor Interfaces (ICFSI-10, Aix-en-Provence, France, July 3-8, 2005), 07 Jul. 2005, English, Oral presentation
    [International presentation]
  • Precisely Controlled Anodic Etching for Processing of GaAs-based Quantum Nanostructures and Devices
    N. Shiozaki; T. Sato; M. Akazawa; H. Hasegawa
    10th International Conference on the Formation of Semiconductor Interfaces (ICFSI-10, Aix-en-Provence, France, July 3-8, 2005), 06 Jul. 2005, English, Poster presentation
    [International presentation]
  • Surface Passivation Using a Si Interface Control Layer for AlGaAs/GaAs Quantum Structures Fabricated on GaAs(111)B Substrates
    AKAZAWA Masamichi; SHIOZAKI Nanako; SATO Taketomo; HASEGAWA Hideki
    IEICE technical report. Electron devices, 03 Jun. 2005, Japanese
    We attempted to apply a Si-interface-control-layer (Si ICL)-based surface passivation method to the surfaces of quantum structures fabricated on GaAs(111)B substrates. The sample surfaces were investigated by an XPS study at each step of the fabrication process, and fabricated quantum structures were characterized by PL measurements. Shifts of surface Fermi level positions toward the conduction band edges at GaAs and AlGaAs(111)B surfaces were observed after the Si ICL formation. PL intensities reduced with reduction of distances between quantum structures and their surfaces. The surface pa...
  • MBE Growth and Si-interlayer Based Surface Passivation of GaAs Quantum Wires
    N. Shiozaki; T. Sato; M. Akazawa; H. Hasegawa
    29th Workshop on Compound Semiconductor Device and Integrated Circuits held in Europe (WOCSDICE2005, May 16-18, 2005, Cardiff), 17 May 2005, English, Oral presentation
    [International presentation]
  • Evaluation of Sub-terahertz Periodic Structure in a Coplanar Stripline
    YAMAZAKI Yusuke; INAFUNE Koji; AKAZAWA Masamichi; SANO Eiichi
    IEICE technical report. Electron devices, 24 Feb. 2005, Japanese
    A periodic structure in a subterahertz coplanar stripline (CPS) was fabricated on a low-temperature-grown GaAs (LT-GaAs) layer in order to achieve an electromagnetic bandgap (EBG). To optimize dimension of structures, we used the finite-difference-time-domain (FDTD) method for the full-wave analysis. In consequence, we found that the thickness of the metal layer affects the characteristic of EBGs. Take into account this result, the sample structure was designed, fabricated, and characterized by the photoconductive sampling (PCS). Two bandgaps and an intermediate passband were observed in th...
  • Transmission Characteristics of THz Perfect-Conductor PerforatedPlate Filters with Two-Dimensional Periodic Holes
    T. Tanaka; M. Akazawa; E. Sano
    2005 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III)" (Sapporo, February 8-10, 2005), 09 Feb. 2005, English, Poster presentation
    [International presentation]
  • Photoconductive Sampling of Electromagnetic Periodic Structures in Subterahertz Coplanar Striplines
    Y. Yamazaki; K. Inafune; M. Akazawa; J. Motohisa; E. Sano
    2005 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III)" (Sapporo, February 8-10, 2005), 09 Feb. 2005, English, Poster presentation
    [International presentation]
  • Using FDTD Method to Design Millimeter-Wave Active Integrated Antena
    K. Inafune; M. Akazawa; E. Sano
    2005 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies (III)" (Sapporo, February 8-10, 2005), 09 Feb. 2005, English, Poster presentation
    [International presentation]
  • THz-Wave Filters Using Surface Periodic Structures Composed of the Metal Films
    TANAKA Takeshi; AKAZAWA Masamichi; SANO Eiichi
    IEICE technical report. Microwaves, 07 Sep. 2004, Japanese
    THz waves are expected to be applied to new technologies in several fields, and the developments of the devices in THz region are needed for the use. In this paper, we study on the structures of THz wave filters for microelectronics and the methods of designing filters by FDTD simulations. The transmission characteristics of meal-thin-film meshes are clearly based on surface plasmon-polaritons. However, other transmission characteristics mechanisms appear in the filters composed of metal-thin-film meshes cascaded at the both sides of a dielectric layer. We investigate the methods of control...
  • A Low-Loss Coplanar Waveguide for the THz Region and Its Application to Electromagnetic-Bandgap Filters
    INAFUNE Koji; AKAZAWA Masamichi; SANO Eiichi
    IEICE technical report. Microwaves, 07 Sep. 2004, Japanese
    A numerical study of a method to reduce the radiation loss of a coplanar waveguide (CPW) is reported, and the application of the low-loss CPW to electromagnetic-bandgap (EBG) filters for the THz region is described. The finite-difference time-domain (FDTD) method was used for the full-wave analysis of CPWs and filters. It is expected that the radiation loss could be greatly reduced by constructing a CPW on a substrate consisting of a thin GaAs film reinforced with a thick backside insulator with a low dielectric constant. The application of the same substrate structure to a newly devised EB...
  • Adiabatic Switching by Quasistatic Operation of Single-Electron-Tunneling Devices
    AKAZAWA Masamichi
    The transactions of the Institute of Electronics, Information and Communication Engineers. C, 01 Jul. 2003, Japanese
    単電子デバイスの準静的動作の極限において,消費電力がかからない無損失の,断熱的なスイッチング動作となることがあり得るかどうかについて考察した.通常,トランジスタに代表されるスイッチング素子においてはしきい値が存在し,そのしきい値において急激なエネルギー変化を伴うことから準静的動作による消費電力の低減には限界がある.しかし,単電子デバイスでは,デバイスの設計次第で,準静的な電圧変化に対して急激なエネルギー変化を伴わないスイッチングが可能である.本論文では,単電子デバイスの準静的動作について,その消費電力特性を数値計算により予測した結果を示す.
  • Possibility of Adiabatic Switching of Single-Electron-Devices
    M. Akazawa
    2003 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies" (Sapporo, February 12-14, 2003), 13 Feb. 2003, English, Poster presentation
    [International presentation]
  • Electromagnetic Field Simulation of 2-Dimensional Polygon-Array Photonic Crystals
    M. Akazawa; T. Tanaka; K. Inafune; E. Sano
    2003 RCIQE International Seminar for 21st Century COE Program: "Quantum Nanoelectronics for Meme-Media-Based Information Technologies" (Sapporo, February 12-14, 2003), 13 Feb. 2003, English, Poster presentation
    [International presentation]
  • Properties of Electronic States at Free Surfaces and Schottky Barrier Interfaces of AlGaN/ GaN Heterostructure
    H. Hasegawa; T. Inagaki; S. Ootomo; M. Akazawa; T. Hashizume
    29th International Symposium on Compound Semiconductor (Lausanne, Switzerland, October 7-10, 2002), 08 Oct. 2002, English, Oral presentation
    [International presentation]
  • Application of UHV Contactless C-V Measurement to the Surface of SOI
    Akazawa Masamichi; Hasegawa Hideki
    Proceedings of the Society Conference of IEICE, 20 Aug. 2002, Japanese
  • A UHV Contactless Capacitance-Voltage Characterization Method Applicable to Semiconductor Layers Grown on Insulating Substrates
    M. Akazawa; H. Hasegawa
    6th International Workshop on Expert Evaluation & Control of Compound Semiconductor Materials & Technologies (EXMATEC 2002, Budapest, Hungary, May 26-29, 2002), 28 May 2002, English, Poster presentation
    [International presentation]
  • Evaluation of carbon thin films deposited by oxygen plasma assisted PLD method
    ONO Tomoyuki; SUDA Yoshiyuki; AKAZAWA Masamichi; SUGAWARA Hirotake; SAKAI Yosuke; SUZUKI Kaoru
    電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan, 21 Sep. 2001, Japanese
  • ナノデバイスによる断熱論理回路
    赤澤正道
    応用物理学会学術講演会講演予稿集, 11 Sep. 2001, Japanese
  • Deposition and Characterization of C:F Films Using C_7F_<16> : Effect of Material Gas Pressure and Gas Additions
    HOKOI K; AKAZAWA M; SUGAWARA H; SUDA Y; SAKAI Y
    電気学会研究会資料. ED, 放電研究会, 07 Aug. 2001, Japanese
  • C7F16を用いたa‐C:F膜のRFプラズマCVD
    鉾井耕司; 赤澤正道; 菅原広剛; 須田善行; 酒井洋輔
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2001, Japanese
  • QMESFETの作製と評価
    赤澤正道; 葛西誠也; 橋詰保; 長谷川英機
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2001, Japanese
  • プラズマ制御PLD法による炭素薄膜堆積—酸素プラズマのエッチング効果について—
    小野智之; 須田善行; 赤澤正道; 菅原広剛; 酒井洋輔
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2001, Japanese
  • プラズマ制御PLD法による炭素微粒子生成—プラズマ電力による微粒子形状変化—
    須田善行; 小野智之; 赤澤正道; 酒井洋輔
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2001, Japanese
  • 低温プロセスによるSi(001)上に形成した極薄絶縁膜/Si界面の非接触非破壊評価
    庄子亮平; 吉田俊幸; 橋詰保; 赤澤正道; 長谷川英機
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2001, Japanese
  • Proposal and Fabrication of a QMESFET
    Akazawa M; Kasai S; Hashizume T; Hasegawa H
    Technical report of IEICE. SDM, 21 Feb. 2001, Japanese
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is a quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the ...
  • Characterization of ultrathin insulator/Si interfaces formed on n-Si(001)by UHV contactless capacitance-voltage method
    SHOUJI Ryouhei; HASHIZUME Tamotsu; YOSHIDA Toshiyuki; AKAZAWA Masamichi; HASEGAWA Hideki
    Technical report of IEICE. SDM, 21 Feb. 2001, Japanese
    Ultrathin insulator/Si interfaces formed by various low temperature processes were characterized by UHV contactless C-V and XPS methods. For the SiO_2/Si interfaces prepared by a thermal oxidation process using dry O_2, the interface state density was increased with decreasing the oxidation temperature. In addition, lower temperature process was found to produce a discrete defect level near midgap. The ECR-excited N_2O plasma process at 400°C realized the interface with relatively low interface state density and wide destribution. Furthermore improvement of interface properties were achieve...
  • Proposal and Fabrication of a QMESFET
    Akazawa M; Kasai S; Hashizume T; Hasegawa H
    IEICE technical report. Electron devices, 21 Feb. 2001, Japanese
    We propose a novel ultra-small MOSFET structure in which we can reduce the tunneling current through the ultrathin gate oxide without using a high-K dielectric. The results of device fabrication are also reported. The proposed device is quasi-MESFET, referred as a QMESFET, having an ultrathin SiO_2 inserted between the gate metal and a highly doped ultrathin SOI channel. In the proposed device, the depletion layer at the semiconductor surface works as a barrier for electron tunneling and reduces the tunneling current through the gate oxide. We can obtain a satisfactory performance of the pr...
  • Characterization of ultrathin insulator / Si interfaces formed on n-Si(001) by UHV contactless capacitance-voltage method
    SHOUJI Ryouhei; HASHIZUME Tamotsu; YOSHIDA Toshiyuki; AKAZAWA Masamichi; HASEGAWA Hideki
    IEICE technical report. Electron devices, 21 Feb. 2001, Japanese
    Ultrathin insulator/Si interfaces formed by various low temperature processes were characterized by UHV contactless C-V and XPS methods. For the SiO_2/Si interfaces prepared by thermal oxidation process using dry O_2, the interface state density was increased with decreasing the oxidation temperature. In addition, lower temperature process was found to produce a discrete defect level near midgap. The ECR-excited N_2O plasma process at 400℃ realized the interface with relatively low interface state density and wide distribution. Furthermore improvement of interface properties were achieved b...
  • Programmable Three-Dimensional Cellular-Neural-Network LSI
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE, 07 Sep. 2000, Japanese
  • Fabrication of an Insulated Gate MESFET Using an SOI Layer
    AKAZAWA Masamichi
    Proceedings of the Society Conference of IEICE, 07 Sep. 2000, Japanese
  • 低温プロセスによる形成した極薄絶縁膜/Si(001)界面の超高真空対応非接触C‐V法による評価
    庄子亮平; 吉田俊幸; 橋詰保; 赤澤正道; 長谷川英機
    応用物理学会学術講演会講演予稿集, 03 Sep. 2000, Japanese
  • プラズマ制御PLD法による炭素微粒子生成—プラズマによるC(1s)スペクトル変化—
    須田善行; 小野智之; 赤澤正道; 酒井洋輔
    応用物理学会学術講演会講演予稿集, 03 Sep. 2000, Japanese
  • C7F16/Heを用いたa‐C:F膜のRFプラズマCVD
    鉾井耕司; 赤澤正道; 菅原広剛; 須田善行; 酒井洋輔
    応用物理学会学術講演会講演予稿集, 03 Sep. 2000, Japanese
  • プラズマ制御PLD法による炭素微粒子生成
    西村卓真; 須田善行; 小野智之; 赤澤正道; 酒井洋輔
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2000, Japanese
  • C7F16,(C3F7)3N/(C4F9)3NおよびC8F18/C8F16Oを用いたa‐C:F膜のプラズマCVD
    赤澤正道; LUNGU C. P; LUNGU A; 田畑昌祥; 鉾井耕司; 菅原広剛; 酒井洋輔
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2000, Japanese
  • 高誘電体を有するMOS構造の容量—電圧特性における周波数分散
    赤澤正道; 谷井隆; 橋詰保
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2000, Japanese
  • ショットキーラップゲート構造を用いた単電子インバータの作製と評価
    赤澤正道; 金編健太郎; 葛西誠也; 雨宮好仁; 長谷川英機
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2000, Japanese
  • 低温プロセスによりn‐Si(100)上に形成した極薄絶縁膜/Si界面の非接触C‐V法による評価
    庄子亮平; 塩沢竜生; 吉田俊幸; 赤澤正道; 橋詰保; 長谷川英機
    応用物理学関係連合講演会講演予稿集, 28 Mar. 2000, Japanese
  • Programmable Three-Dimensional Cellular-Neural-Network Circuits
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the IEICE General Conference, 07 Mar. 2000, Japanese
  • Pulsed Laser Deposition of Carbon Particles Controlled by ICP Plasma
    Y. Suda; T. Nishimura; T. Ono; M. Akazawa; Y. Sakai
    International Workshop on Basic Aspects of Non-equilibrium Plasmas Interacting with Surfaces (BANPIS-2000, Nagasaki, Japan, January 28 - 30, 2000), 29 Jan. 2000, English, Oral presentation
    [International presentation]
  • Parameter Design of a Single-Electron Inverter With Multiple-Valued Characteristics
    Kanaami K; Akazawa M; Amemiya Y
    IEICE technical report. Circuits and systems, 19 Jan. 2000, Japanese
    Functional LSIs using extremely small amounts of power can be made by using single-electron circuits, but designing the parameters of such circuits is a complicated and troublesome task. This paper therefore propose, taking the single-electron inverter circuit as an example, a simple policy for the circuit-parameter design. Following this policy, we can easily design a single-electron inverter with a desired transfer characteristic. We have, for example, designed a special inverter circuit that can be used for constructing multiple-valued logic systems. A multiple-valued transfer characteri...
  • Pulsed Laser Deposition of Carbon Films in Ar plasmas
    NISHIMURA Takuma; MIZUNO Manabu; SUDA Yoshiyuki; SAKAI Yosuke; AKAZAWA Masamichi
    電気学会研究会資料. ED, 放電研究会, 19 Oct. 1999, Japanese
  • CFx Polymer Film Deposition in DC and RF Fluorinert Vapor Plasmas
    C. P. Lungu; A. M. Lungu; Y. Sakai; H. Sugawara; M. Tabata; M. Akazawa; M. Miyamoto
    Second International Symposium on Applied Plasma Science (ISPAS'99, Osaka, Japan, September 20 -24, 1999), 23 Sep. 1999, English, Oral presentation
    [International presentation]
  • Observation of Laser Ablated Carbon Plume
    SUDA Yoshiyuki; MIZUNO Manabu; NISHIMURA Takuma; BRATESCU M. A; SAKAI Yosuke; AKAZAWA Masamichi
    電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan, 08 Sep. 1999, Japanese
  • Pulsed Laser Deposition of Carbon Films
    NISHIMURA Takuma; MIZUNO Manabu; SUDA Yoshiyuki; SAKAI Yosuke; AKAZAWA Masamichi
    電気学会基礎・材料・共通部門大会講演論文集 = Proceeding of Annual Conference of Fundamentals and Materials Society, IEE Japan, 08 Sep. 1999, Japanese
  • A Three Dimensional νMOS Cellular-Neural-Network Circuit
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE, 16 Aug. 1999, Japanese
  • A Single-Flux-Quantum Logic Circuit Based on the Modified BDD Structure
    Akazawa M; Amemiya Y
    Proceedings of the Society Conference of IEICE, 16 Aug. 1999, Japanese
  • Circuit Design of A Three Dimensional Cellular Neural Network Using υMOS
    Fujiwara T; Akazawa M; Amemiya Y
    Technical report of IEICE. VLD, 10 Jun. 1999, Japanese
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem,...
  • Circuit Design of A Three Dimensional Cellular Neural Network Using υMOS
    Fujiwara T; Akazawa M; Amemiya Y
    Technical report of IEICE. DSP, 10 Jun. 1999, Japanese
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem,...
  • Circuit Design of A Three Dimensional Cellular Neural Network Using υMOS
    Fujiwara T; Akazawa M; Amemiya Y
    IEICE technical report. Circuits and systems, 10 Jun. 1999, Japanese
    A design method assuming a CMOS LSI process is proposed for building a three-dimensional (3D) cellular neural network (CNN) circuit. A υMOS circuit is used so that neuron cells, which interact with the nearest-neighbor cells, can be compactly constructed. By arranging the neuron-cell circuits, the whole 3D CNN circuit can be constructed on a two-dimensional plane. And because of the characteristic that the cells only interact with nearest-neighbor cells, orderly interconnection is achieved. As an example, a circuit, which functions as a 3D CNN and can solve a reinforcement learning problem,...
  • 28a-ZM-4 A Full Adder Circuit Using Single-Electron Multiple-Valued Threshold Devices
    Kanaami K; Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1999, Japanese
  • Solving Combinational Optimization Problems with the Quantum Hopfield Network
    TOKUDA E; ASAHI N; AKAZAWA M; AMEMIYA Y
    IEICE technical report. Neurocomputing, 19 Mar. 1999, Japanese
    The quantum Hopfield network is a kind of recurrent neural network that can always converge to the global minimum state without being stuck in local minima. This property is obtained by utilizing the co-tunneling phenomenon in quantum systems. This paper proposes a method of constructing the quantum Hopfield network by using single-electron circuits. The operation of the single-electron quantum Hopfield network is analized by computer simulation, assuming an instance of combinatrial optimization problems. It is demonstrated that, starting with a given initial state, the network can converge...
  • Boltzmann Machine Device Using Signle-Electron Circuits
    YAMADA Takashi; AKAZAWA Masamichi; AMEMIYA Yoshihito
    IEICE technical report. Neurocomputing, 18 Mar. 1999, Japanese
    This paper proposes to create Boltzmann Machine device by using single-electron circuits. The Boltzmann machine is a kind of recurrent neural network that can solve various problems in subject such as combinational optimization. It is difficult for presently available electronic circuits to implement the generation of randomness for the stochastic neuron operation. We can construct the stochastic neuron device concisely by using single-electron circuits and, thereby, can implement the Boltzmann machine on an LSIs.
  • A Three-Dimensional Cellular Neural Network Circuit
    Fujiwara Takanobu; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the IEICE General Conference, 08 Mar. 1999, Japanese
  • Color Petri-net Circuits Using Multiple-Valued Signals
    Koutani M; Akazawa M; Amemiya Y
    Proceedings of the IEICE General Conference, 08 Mar. 1999, Japanese
  • Single-Flux-Quantum Logic Devices Based on the Binary Decision Diagram
    N. Asahi; T. Yamada; M. Akazawa; Y. Amemiya
    11th International Symposium on Superconductivity (ISS'98, Fukuoka, Japan, November 16-19, 1998), 17 Nov. 1998, English, Oral presentation
    [International presentation]
  • Single-Flux-Quantum Logic Circuits Based on the Binary Decision Diagram : Circuit design for a 32-bit adder
    ASAHI Noboru; YAMADA Takashi; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Technical report of IEICE. SCE, 16 Nov. 1998, Japanese
    A 32-bit adder circuit is designed using single-flux-quantum (SFQ) circuits, on the basis of the binary decision diagram (BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. We here construct a high-speed SFQ adder circuit based on a BDD representation simplified by the method of isomorphic-subgraph substitution. To construct the adder circuit compactly, we propose the BDD device that can be driven by SFQ signal. It is shown by computer simulation that the operation speed...
  • ν-MOS Cellular-Automaton Devices for Intelligent Image Sensors
    M. Ikebe; M. Akazawa; Y. Amemiya
    5th International Conference on Soft Computing and Information/ Intelligent Systems (IIZUKA'98, Iizuka, Fukuoka, Japan, October 16 - 20, 1998), 19 Oct. 1998, English, Oral presentation
    [International presentation]
  • Network Operation of the Single-Electron Boltzmann Machine
    YAMADA Takashi; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE, 07 Sep. 1998, Japanese
  • Multiple-Valued-Logic Processing Based on the Pulse Width Modulation
    FUKASAWA Yoshiyuki; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE, 07 Sep. 1998, Japanese
  • Single-Flux-Quantum Logic circuits based on the Binary Decision Diagram
    ASAHI Noboru; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE, 07 Sep. 1998, Japanese
  • Solving Combinatorial Optimization Problems with the Quantum Hopfield Network
    TOKUDA E; ASAHI N; AKAZAWA M; AMEMIYA Y
    Proceedings of the Society Conference of IEICE, 07 Sep. 1998, Japanese
  • Single-Flux-Quantum Logic Circuits Based of the Binary Decision Diagram
    ASAHI Noboru; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Technical report of IEICE. SCE, 28 Jul. 1998, Japanese
    This paper proposes the single-flux-quantum logic circuit based on the binary decision diagram(BDD). The BDD is a graphical method for representing digital functions and can provide a concise expression for most logic functions encountered in LSI design applications. By implementing BDDs with single-flux-quantum circuits, we can create various logic systems that are capable of high speed operation.Construction and operation of an 8-bit adder is presented as an example.
  • [Invited] Binary-Decision-Diagram Logic Systems Using Single-Electron Circuits and Single-Flux-Quantum Circuits－Circuit Design and Simulation
    M. Akazawa
    Seventh Hitachi Cambridge Seminar (McCrum Lecture Theatre, Corpus Christi College, Cambridge, U.K., July 6, 1998), 06 Jul. 1998, English, Invited oral presentation
    [Invited], [International presentation]
  • ν-MOS Cellular-Automaton Devices for Intelligent Image Sensors
    M. Ikebe; M. Akazawa; Y. Amemiya
    Second International Conference on Knowledge-Based Intelligent Electronic Systems (Adelaide, Australia, April 21 -23, 1998), 22 Apr. 1998, English, Oral presentation
    [International presentation]
  • Network Operation of a Single-Electron Boltzmann Machine
    YAMADA T; AKAZAWA M; AMEMIYA Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1998, Japanese
  • Construction of Sequencial Circuits Using Single-Electron Majority Logic Devices
    IWAMURA H; AKAZAWA M; AMEMIYA Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1998, Japanese
  • Solution to the Independent Set Problem Using Single Electron Analog Computation
    TOKUDA E; ASAHI N; AKAZAWA M; AMEMIYA Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1998, Japanese
  • Current Circulation in a Loop Circuit of Directioncal Single-Electron-Tunnelling Junctions
    KANAAMI K; AKAZAWA M; AMEMIYA Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1998, Japanese
  • Electron-Wave Quantum Circuits for solving the Deutsch-Jozsa problem
    AKAZAWA M; AMEMIYA Y; TABE M
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1998, Japanese
  • Quantum Hopfield Network Using Single-Electron Circuits : Hopfield Network Without the Local-Minimum Problem
    Kazawa M; Amemiya Y
    IEICE technical report. Neurocomputing, 20 Mar. 1998, Japanese
    The Hopfield network is a computation model for solving combinatorial optimization problems through the use of the specific feedback network. The feedback network changes its internal state to minimize the energy function. Thus we can obtain the solution to the given problem by relating the cost function of the problem to the energy function of the network and by observing how the network settles down to the minimum energy state. Owing to the existence of local minima in the energy function, however, we cannot always be certain of obtaining the correct solution to the problem. To overcome t...
  • Multiple-valued Logic Based on Pulse-Width Modulation
    Fukasawa Yoshiyuki; Akasawa Masamichi; Amemiya Yoshihito
    Proceedings of the IEICE General Conference, 06 Mar. 1998, Japanese
  • Single-Electron Logic Circuits Based on the Binary Decision Diagram
    N. Asahi; M. Akazawa; Y. Amemiya
    3rd International Workshop on Quantum Functional Devices (QFD'97, Gaithersberg, Maryland, U.S.A., November 5-7, 1997), 06 Nov. 1997, English, Oral presentation
    [International presentation]
  • Single-Electron Majority Logic Circuits
    IWAMURA Hiroki; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Technical report of IEICE. ICD, 26 Sep. 1997, Japanese
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • Single-Electron Majority Logic Circuits
    IWAMURA Hiroki; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Technical report of IEICE. SDM, 26 Sep. 1997, Japanese
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • Single-Electron Majority Logic Circuits
    IWAMURA Hiroki; AKAZAWA Masamichi; AMEMIYA Yoshihito
    Technical report of IEICE. VLD, 26 Sep. 1997, Japanese
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • Single-Electron Majority Logic Circuits
    IWAMURA Hiroki; AKAZAWA Masamichi; AMEMIYA Yoshihito
    IEICE technical report. Electron devices, 26 Sep. 1997, Japanese
    This paper proposes circuit construction for constructing single-electron integated circuits based on majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. By ombining identical majority gate circuits, various subsystems can be constructed with a smaller number of devices than that of Boolean-based construction. An adder and a parity generator are designed as examples. It is shown by computer simulation that the designed subsystems produce the correct logic operations. The operation ...
  • [Invited] Quantum Hopfield Network Using Single-Electron Circuits
    M. Akazawa
    1997 International Conference on Solid State Devices and Materials (SSDM'97, Hamamatsu, Shizuoka, Japan, September 16-19, 1997), 18 Sep. 1997, English, Invited oral presentation
    [Invited], [International presentation]
  • Computer-Aided Design of Single-Electron Boltzmann Machine Neuron Circuit
    M. Akazawa; T. Yamada; Y. Amemiya
    1997 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'97, Boston, U.S.A., September 2-4,1997), 03 Sep. 1997, English, Oral presentation
    [International presentation]
  • Computer-Aided Design of Single-Electron Boltzmann Machine Neuron Circuit
    M. Akazawa; T. Yamada; Y. Amemiya
    Second International research Workshop on Future Information Processing Technologies (Sapporo Kita-Hiroshima Prince Hotel, Kita-Hiroshima, August 25-28,1997), 26 Aug. 1997, English, Oral presentation
    [International presentation]
  • νMOS multiple-valued logic circuit based on the decision diagram
    Yamada Takashi; Iwamura Hiroki; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE, 13 Aug. 1997, Japanese
    決定グラフとはディジタル論理を有向グラフで表す手法であり、論理設計や論理検証などのCADで使われている。本研究では、多値論理の決定グラフ(MDD:Multiple-valued Decision Diagram)を実際のデバイスで構成することを提案する。具体例として、4値論理MDDをシリコン機能デバイスのνMOSで構成してみた。加算器を例にとってシミュレーション解析を行い、正しい論理動作を確認した。以下に結果を述べる
  • Low-power Construction of νMOS Cellular Automata
    IKEBE Masayuki; Honma Kunihiko; Akazawa Masamichi; AMEMIYA Yoshihito
    Proceedings of the Society Conference of IEICE, 13 Aug. 1997, Japanese
    νMOSインバータは、多入力しきい論理に適したデバイスである。これを用いると画像処理用セルオートマトン回路をコンパクトに構成できる。しかし、しきい論理回路ではνMOSをオンとオフの中間状態で使うことが多く、そのため貫通電流を生じて消費電力が大きくなりやすい。 ここではνMOS回路の低電力設計を考える。雑音除去・輪郭抽出セルオートマトン回路を例にとり、ダイナミック形と高しきい値MOS形の2つの構成法によって低電力設計行った。以下にその詳細を示す。
  • Programmable logic device using single-electron quasi-CMOS circuits
    Nitta Hidehiko; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the Society Conference of IEICE, 13 Aug. 1997, Japanese
    単電子回路を用いてCMOS型の論理回路が構成されており, 擬似CMOS型単電子回路と呼ばれている. ところで, 単電子回路の性質を上手に利用すれば, 本来のCMOSにはない新しい機能を付加することができる. ここでは, 入力の組合わせにより論理を切り換えられる可変論理デバイスを提案する.
  • Single-electron step inverter
    Asahi Noboru; Akazawa Masamichi
    Proceedings of the Society Conference of IEICE, 13 Aug. 1997, Japanese
    単電子回路では、輸送電荷の離散性とクーロンブロッケード現象とが相まって、通常の電子回路には見られない様々な特性が現れる。そのためCMOS回路では得られない種々の機能が実現可能となる。たとえば、インバータ回路を例にとってパラメータ探索を行ったところ、入出力の伝達特性がステップ的に変化する「ステップインバータ」の機能が得られることが判明した。これは、しきい論理回路や多値論理回路を低電力設計するときに不可欠のものである。以下に結果を報告する。
  • 29p-B-15 Temperature valiable single-electron Boltzmann-machine neuron circuit
    Yamada T; Akazawa M
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1997, Japanese
  • 29p-B-14 Analysis of Combinatorial Problems Using A Single-electron Hopfield Network
    Akazawa M
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1997, Japanese
  • 29p-B-13 Single-Electron Hopfield Neural Network
    Tokuda E; Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1997, Japanese
  • 29p-B-12 Single-Electron Logic Circuit using quasi-CMOS logic gates
    Nitta H; Akazawa M
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1997, Japanese
  • 29a-B-3 Thermal Noise in single-Electron Binary-Decision-Diagram Circuits
    Asahi N; Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1997, Japanese
  • 29a-B-1 Arrangement of back-ground charge in quantum cellular automata
    Lee G; Akazawa M; Wu Nan Jian; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1997, Japanese
  • Construction of Logic Circuits Using Single-Electron BDD Devices
    Akazawa M; Asahi N; Amemiya Y
    IEICE technical report. Electron devices, 14 Mar. 1997, Japanese
    This paper proposes an idea of constructing single-electron logic circuits based on the binary-decision diagram (BDD). The proposed unit device consists of four tunnel junctions and operates as a two-way switch for single-electron transport. Any combinational logic can be implemented by connecting the identical unit devices into a cascade to build the tree of a BDD graph. Several sample designs are presented for elemental logic circuits (NAND, NOR, XOR) and combinational logic circuits (a four-variable logic circuit and a 4-bit adder). Computer simulation shows that the designed circuits pe...
  • Analog Logic Circuits Using BDD devices
    Fukasawa Yoshiyuki; Akazawa Masamichi; Amemiya Yoshihito
    Proceedings of the IEICE General Conference, 06 Mar. 1997, Japanese
    二分決定グラフ(BDD)は, ブール代数式や真理値表とは異なる方法, 有向グラフによってディジタル論理を表す手法である。もともと論理設計や論理検証に使われていたが, 最近になって実際のデバイスでBDD論理を組むという研究が報告されるようになった。ここでは, BDDの適用範囲をアナログに拡大することを提案する。これによって新しい応用が生まれる可能性がある。
  • Analog Signal Processing Using Single-Electron Circuits
    Akasawa Masamichi; Amemiya Yoshihito
    Proceedings of the IEICE General Conference, 06 Mar. 1997, Japanese
    単電子現象は本質的に離散現象なので, それを利用した単電子回路も本来はデジタル論理に適したものである。しかしアナログ回路の開発も将来に向けて必要とされる。ここでは電子密度変調によるアナログ表現法を提案し, そのための回路構成を考えてみた。
  • A Phosphorus Pile-Up Model for SiO2-Si interface of p-Channel MOSFETs
    Aoki Takahiro; Akazawa Masamichi; Tazawa Satoshi
    Proceedings of the Society Conference of IEICE, 18 Sep. 1996, Japanese
    計算機上でプロセス・デバイス・回路をシミュレートし、デバイスの特性を予測するTechnology CAD技術は短TATな製造技術の開発に必要である。特性予測をより正確に行うには地道な実験データの蓄積とモデリングが必須である。一般にpチャネルMOSFETにおいて、nウェル形成用の燐ドーパントにはパイルアップ現象があることが知られており、この現象を取り扱っていない従来のシミュレータでは、デバイス特性予測を大きく狂わすことが知られている。また、SiO2-Si界面において酸化工程、アニール工程後の燐ドーパントの再分布(偏析)があることも一般的に知られている。本報告では、燐ドーパントのパイルアップ現象をモデル化し、種々のプロセス水準に対するpチャネルMOSFETのしきい値電圧の実測結果と比較した結果を述べる。
  • Possibility of Operation of Logic Circuit Using Quantum Cellular Automata
    Akazawa Masamichi; Amamiya Yoshihito
    Proceedings of the Society Conference of IEICE, 18 Sep. 1996, Japanese
    量子セルの近接相互作用を利用したセルオートマトン(QCA)が提案されている。しかしこれまでのところセル配列の静的な安定状態を考察するに留まり、システム全体として動作するかどうかは理論的にも実験的にも検証されていない。そこで著者は種々の観点からその動作可能性を検討し、アニーリングによる駆動を行えばシステム動作が可能であろう、との予測を行った。
  • Phosphorus Pile-Up Model for SiO2-Si Interface of p-Channel MOSFETs
    M. Akazawa; T. Aoki; S. Tazawa; Y. Sato
    1996 International Conference on Simulation of Semiconductor Processes and Devices (SISPAD'96, Tokyo, Japan, September 2-4, 1996), 03 Sep. 1996, English, Oral presentation
    [International presentation]
  • 27a-ZA-12 Analysis of Quantum Cellular Automata using Feedback Neural Network
    Shibata N; Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 26 Mar. 1996, Japanese
  • 27a-ZA-11 Study on Operation of Quantum Cellular Automata
    Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 26 Mar. 1996, Japanese
  • 27a-ZA-9 Single-Electron Lgic Circuits based on Binary Decision Diagram
    Asahi N; Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 26 Mar. 1996, Japanese
  • 27a-ZA-7 A Boltzmann-machine neural circuit using single-electron tunneling
    Akazawa M; Amemiya Y
    応用物理学関係連合講演会講演予稿集, 26 Mar. 1996, Japanese
  • Contactless and Nondestructive Characterization of Silicon Surfaces by Capacitance-Voltage and Photoluminescence Method
    S. Koyanagi; M. Akazawa; H. Hasegawa
    1995 Int. Conf. on Solid State Devices and Materials (SSDM'95, Osaka, Japan, August 21-24, 1995), 23 Aug. 1995, English, Oral presentation
    [International presentation]
  • Strategy in developing LSIs using quantum devices-How to implement information processing using quantum effects-
    AMEMIYA Yoshihito; AKAZAWA Masamichi
    應用物理, 10 Aug. 1995, Japanese
  • 29p-ZN-5 Surface Electrical Conduction Characteristics of GaAs grown by MBE at Low Temperature
    Shiobara S; Suzuki S; Akazawa M; Hashizume T; Hasegawa H
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1995, Japanese
  • 29p-ZN-1 Characterization of electronic properties at semiconductor surface by contactless C-V and PL measurements(1)
    Akazawa M; Koyanagi S; Hasegawa H; Sakai T
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1995, Japanese
  • 29a-PA-25 Characterization of electronic properties of mono-and multi-crystalline Si surfaces by contactless C-V and P-L measurements (1)
    Koyanagi S; Akazawa M; Hasegawa H; Sakai T
    応用物理学関係連合講演会講演予稿集, 28 Mar. 1995, Japanese
  • Control of Compound Semiconductor Interfaces by Si Interface Control Layer and Its Applications
    H. Hasegawa; S. Kodama; K. Koyanagi; M. Akazawa
    State-of-the-Art Program on Compound Semiconductors XVIII (SOTAPOCS XVIII, Honolulu, Hawaii, U.S.A., May 18, 1993), 18 May 1993, English, Oral presentation
    [International presentation]
  • [Invited] Control of Structure and Properties of Compound Semiconductor Interfaces by Si Interface Control Layer
    H. Hasegawa; S. Kodama; K. Koyanagi; M. Akazawa
    5th International Conference on Indium Phosphide and Related Materials (IPRM'93, Paris, France, April 18-22, 1993), 19 Apr. 1993, English, Invited oral presentation
    [Invited], [International presentation]
  • Control of Compound Semiconductor Interfaces by Si Interface Control Layer and Its Applications
    H. Hasegawa; M. Akazawa; S. Kodama; K. Koyanagi; S. Suzuki; Y. G. Xie; T. Sawada
    Conference on Advanced Heterostructure Transistors (Keauhou, Kona, Hawaii, U.S.A., November 29- December 4, 1992), 30 Nov. 1992, English, Oral presentation
    [International presentation]
  • In-Situ Characterization and Control of GaAs and InGaAs Surfaces and Interfaces for Completely UHV-Based Nanostructure Fabrication
    H. Hasegawa; T. Sawada; T. Saitoh; S. Kodama; M. Akazawa; H. Fujikura
    International Conference on Scienece and Technology of Electron Devices (Kruger National Park, Republic of South Africa, November 16-18, 1992), 17 Nov. 1992, English, Oral presentation
    [International presentation]
  • In-Situ Characterization and Control of Compound Semiconductor Surfaces and Interfaces for Completely UHV-Based Nanostructure Fabrication
    H. Hasegawa; T. Saitoh; M. Akazawa; H. Fujikura; T. Sawada
    3rd International Conference on Solid State and Integrated Circuit Technology (ICSIT'92, Bejin, China, Oct. 18 - 24, 1992), 20 Oct. 1992, English, Oral presentation
    [International presentation]
  • Investigation of Valence Band Offset Modification at GaAs-AlAs and InGaAs-InAlAs Heterointerfaces Induced by Si Interlayer
    M. Akazawa; H. Hasegawa; H. Tomozawa; H. Fujikura
    19th International Symposium on GaAs and Related Compounds (Karuisawa, Japan, September 28- October 2, 1992), 30 Sep. 1992, English, Oral presentation
    [International presentation]
  • Removal of Fermi Level Pinning in InGaAs Nanostructures by Ultrathin MBE Si Interface Control Layer
    M. Akazawa; S. Kodama; H. Fujikura; H. Hasegawa
    Electronic Materials Conference (Cambridge, U.S.A., June 24-26, 1992), 25 Jun. 1992, English, Oral presentation
    [International presentation]
  • Control of Compound Semiconductor Interfaces by an Ultrathin Pseudomorphic Si Layer
    H. Hasegawa; M. Akazawa; S. Kodama; K. Koyanagi
    1st International Workshop on Quantum Functional Devices (QFD'92, Nasu Heights, Japan, May 12-15, 1992), 13 May 1992, English, Oral presentation
    [International presentation]
  • Control of Surface and Interface Fermi Level Pinning for Compound Semiconductor Nanometer Scale Structures
    H. Hasegawa; M. Fujikura; M. Akazawa; H. Tomozawa
    International Workshop on Quantum-Effect Physics, Electronics and Applications (Luxor, Egypt, January 5-9, 1992), 06 Jan. 1992, English, Oral presentation
    [International presentation]
  • Fabrication Process and Properties of InGaAs Wires Having Si Interface Control Layers for Removal of Fermi Level Pinning
    H. Fujikura; H. Tomozawa; M. Akazawa; H. Hasegawa
    1st International Symposium on Atomically Controlled Surfaces and Interfaces (ACSI-1, Tokyo, Japan, November 19-22, 1991), 20 Nov. 1991, English, Oral presentation
    [International presentation]
  • Control of GaAs and InGaAs Insulator- Semiconductor and Metal-Semiconductor Interfaces by Ultrathin Molecular Beam Epitaxy Si Layers
    M. Akazawa; H. Ishii; H. Hasegawa
    1991 Int. Conf. on Solid State Devices and Materials (SSDM'91, Yokohama, Japan, August 27-29, 1991), 28 Aug. 1991, English, Oral presentation
    [International presentation]
  • Formation Mechanism of Schottky Barriers on MBE Grown GaAs Surface Subjected to Various Treatment
    H. Ishii; H. Hasegawa; M. Akazawa
    3rd International Conference on Formation of Surface and Interface (ICFSI-3, Rome, Italy, May, 1991), May 1991, English, Oral presentation
    [International presentation]
  • Surface Passivation Technology of InGaAs Using an MBE Si Layer Compatible with Standard Device Processing
    H. Hasegawa; M. Akazawa; E. Ohue
    3rd International Conference on InP and Related Materials (IPRM'91, Cardiff, Wales, U.K., April 8-11, 1991), 09 Apr. 1991, English, Oral presentation
    [International presentation]
  • Surface Passivation of InGaAs Using Thin Si Layers by Novel In-situ Interface Control Process
    M. Akazawa; E. Ohue; H. Ishii; H. Iwadate; H. Hasegawa
    2nd International Conference on InP and Related Materials (IPRM'90, Denver, U.S.A., April23-25, 1990), 24 Apr. 1990, English, Oral presentation
    [International presentation]
  • Control of GaAs and InGaAs Insulator-Semiconductor Interfaces by an Ultrathin MBE Si Layer
    H. Hasegawa; M. Akazawa; H. Iwadate; E. Ohue
    7th International Workshop on Future Electron Devices (Toba, Japan, October 2-4, 1989), 03 Oct. 1989, English, Oral presentation
    [International presentation]
  • Surface Passivation of In0.53Ga0.47As by Ultra-thin Pseudomorphic MBE Si Layer Combined with Photo-CVD Insulator
    M. Akazawa; E. Ohue; H. Ishii; H. Iwadate; H. Hasegawa
    6th International Conference on Passivity (Passivity-6, Sapporo, Japan, Sept. 24-28, 1989), 27 Sep. 1989, English, Oral presentation
    [International presentation]
  • In0.53Ga0.47As MISFETs Having an Ultrathin MBE Si Interface Control Layer and Photo-CVD SiO2 Insulator
    M. Akazawa; H. Hasegawa; H. Ohno
    the 21st Conference on Solid State Devices and Materials (SSDM'89, Tokyo, Japan, August 28-30, 1989), 29 Aug. 1989, English, Oral presentation
    [International presentation]
  • Control of Compound Semiconductor-Insulator Interfaces by an Ultra-thin MBE-Si Layer
    H. Hasegawa; M. Akazawa; H. Ishii; K. Matsuzaki
    The 16th Conference on Physics and Chemistry of Semiconductor Interfaces (PCSI-16, Boseman, Montana, U.S.A., February 7-9, 1989), 08 Feb. 1989, English, Oral presentation
    [International presentation]
  • Characterization and Control of Group-III Nitride Surfaces for Power Electronics and Sensor Electronics [invited]
    H. Hasegawa; M. Akazawa
  • X-ray Photoelectron Spectroscopy Study of Silicon Interlayer Based Surface Passivation for AlGaAs/GaAs Quantum Structures on (111) B Surfaces
    M. Akazawa; N. Shiozaki; H. Hasegawa
  • Characterization of Surfaces and Interfaces of InAlN/GaN Heterostructures
    Masamichi Akazawa
■ Syllabus
  • 応用デバイス回路学特論, 2024年, 修士課程, 情報科学院
  • 先端デバイス学特論, 2024年, 博士後期課程, 情報科学研究科
  • 応用デバイス回路学特論, 2024年, 博士後期課程, 情報科学院
  • ディジタル回路, 2024年, 学士課程, 工学部
  • 科学・技術の世界（1単位）, 2024年, 学士課程, 全学教育
  • 科学・技術の世界（1単位）, 2024年, 学士課程, 全学教育
  • 電気電子工学実験Ⅳ, 2024年, 学士課程, 工学部
  • 電気電子工学実験Ⅴ, 2024年, 学士課程, 工学部
■ Affiliated academic society
  • THE INSTITUTE OF ELECTRICAL ENGINEERS OF JAPAN
  • THE INSTITUTE OF ELECTRONICS, INFORMATION AND COMMUNICATION ENGINEERS.
  • THE JAPAN SOCIETY OF APPLIED PHYSICS
■ Research Themes
  • Improvement of effective electron mobility in inversion-type n-channel gallium nitride MOSFET by interface control
    Grants-in-Aid for Scientific Research
    Apr. 2024 - Mar. 2027
    M. Akazawa; T. Sato
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (B), Hokkaido University, Principal investigator, Competitive research funding, 24K00934
  • 窒化物半導体異種界面パラレル伝導制御とマルチチャネル高周波トランジスタの開発
    科学研究費助成事業
    01 Apr. 2023 - 31 Mar. 2026
    佐藤 威友; 赤澤 正道; 三好 実人
    (1) AlGaN/GaNヘテロ構造に対して界面準位の発生を抑制する絶縁体界面形成法を確立するために、AlGaN/GaNヘテロ構造に対して表面の電子状態を評価した。X線光電子分光（XPS）法によりAlGaN表面状態を分析した結果、結晶成長条件の違い（基板材料の違いによる成長条件の最適化状況の違い）により、フェルミレベルのピンニング位置が異なることを明らかにした。また、そのピンニング位置の違いに対応し、AlGaN表面に形成したオーミック電極の接触抵抗が増減し、さらに異常なピンニング位置を示したAlGaN表面に対して光電気化学エッチングを5 nm実施すると、接触抵抗は正常値に戻るように低減することを明らかにした。これは、結晶成長直後の表面状態が電極の電気的特性に影響を与え、その特性改善には光電気化学エッチングが有効であることを示す結果であり、ゲート絶縁膜界面形成条件の最適化に関する有用な知見を得た。
    (2) GaNおよびAlGaN表面に対して光電気化学酸化を利用した低損傷エッチングに取り組み、1 nm/min程度の低速エッチングを実現した。またエッチング溶液のpH値によって加工後の表面状態は大きく異なり、酸性溶液を利用した時に平坦性が最も良いことを明らかにした。中性溶液では、母体材料であるAlOxおよびGaOxが表面に形成されることをXPS分析により明らかにした。
    (3) AlGaN/GaNヘテロ構造上に作製したMISキャパシタの容量-電圧（C-V）評価により、2つの界面（絶縁膜/AlGaNとAlGaN/GaN）の電子密度分布を算出した。計算機シミュレーションによる理論解析の結果、AlGaN/GaN界面の２DEGチャネルが空乏し始める順方向ゲート電圧領域で絶縁膜/AlGaN界面に電子チャネルが形成される様子が確認され、実験結果をよく説明できることを明らかにした。
    日本学術振興会, 基盤研究(B), 北海道大学, 23K26131
  • 窒化物半導体異種界面パラレル伝導制御とマルチチャネル高周波トランジスタの開発
    科学研究費助成事業
    01 Apr. 2023 - 31 Mar. 2026
    佐藤 威友; 三好 実人; 赤澤 正道
    日本学術振興会, 基盤研究(B), 北海道大学, 23H01437
  • イオン注入したGaN結晶の表面近傍点欠陥評価
    共同研究
    Apr. 2023 - Mar. 2025
    藤倉序章; 横山正史; 金木将太; 堀切文正
    住友化学株式会社, 北海道大学, Principal investigator
  • Creation of innovative core technology for power electronics
    委託事業（再委託）
    Apr. 2021 - Mar. 2025
    Jun Suda
    MEXT, Hokkaido University, Principal investigator
  • GaN結晶の表面近傍点欠陥の評価・低減に関する研究
    共同研究
    Apr. 2022 - Mar. 2023
    赤澤正道; 藤倉序章、堀切文正、金木将太
    株式会社サイオクス, 北海道大学, Principal investigator
  • パワーデバイス向け窒化物半導体上シリコン熱酸化膜形成技術の確立
    研究開発・調査助成
    Apr. 2020 - Mar. 2021
    公益財団法人 八洲環境技術振興財団, 北海道大学, Principal investigator
  • Program for research and development of next-generation semiconductor to realize energysaving society
    科学技術試験研究委託事業
    Apr. 2016 - Mar. 2021
    Tetsu Kachi
    MEXT, Hokkaido University, Competitive research funding
  • 特異構造を含む異種接合の界面制御と電子デバイス展開
    科学研究費補助金（新学術領域研究）
    Apr. 2016 - Mar. 2021
    橋詰 保
    文部科学省, Competitive research funding
  • 高温熱処理アルミナ超薄膜による絶縁体／窒化インジウムアルミニウム界面の制御と応用
    科学研究費補助金(基盤研究(C))
    Apr. 2015 - Mar. 2018
    赤澤 正道
    文部科学省, Principal investigator, Competitive research funding
  • Control of Fermi level pinning at surfaces and interfaces of InAlN
    Grants-in-Aid for Scientific Research
    Apr. 2012 - Mar. 2015
    AKAZAWA Masamichi
    Fermi level pinning at the surface, insulator/semiconductor interface, and metal/semiconductor interface has been investigated for InAlN lattice matched to GaN. Pinning at the InAlN surface was found to be removed by an appropriate insulator deposition. The interface state density at the insulator/InAlN interface was found to be dependent on the interface formation process and post deposition annealing. An original method to form an Al2O3/InAlN interface with a low interface state density was developed. For the metal/InAlN interface, strong dependence of the Schottky barrier height on the metal work function was seen.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (C), Hokkaido University, Principal investigator, Competitive research funding, 24560022
  • Reliability improvement of GaN transistors based on the control of electronic states and a nobel gate structure
    Grants-in-Aid for Scientific Research
    2009 - 2012
    HASHIZUME Tamotsu; SATO Taketomo; KOGA Hiroaki; KUBO Toshiharu; AKAZAWA Masamichi
    To improve the operation stability of GaN-heterostructure transistors, we have carried out characterization and control of electronic states at insulator-semiconductor interfaces, fabrication and characterization of the multi-mesa-channel (MMC) transistors, and the related experiments. By applying the novel simulation and photo-assisted capacitance-voltage methods to Al_2O_3/ AlGaN/GaN structures, we determined the density distribution of electronic states at the Al_2O_3/AlGaN for the first time. It was also found that the MMC structure is very effective in improving the current stability of the GaN-based transistors.
    Japan Society for the Promotion of Science, Grant-in-Aid for Scientific Research (A), Hokkaido University, Coinvestigator not use grants, Competitive research funding, 21246007
  • 化合物半導体MIS界面準位に関するピンニング・スポット面内分布モデル
    科学研究費補助金(萌芽研究)
    2008 - 2008
    長谷川 英機; 赤澤 正道
    本研究の目的は、III-V化合物半導体metal-insulator-semiconductor(MIS)構造の界面準位分布に関する「ピンニング・スポット面内分布(Dps)モデル」を、理論解析とSi超薄膜界面層(Si ICL)構造を用いた実験により定量的に検証することにあり、次の成果を得た。(重)従来界面準位は、面内で均一分布すると仮定されてきた。DSPモデルでは、界面準位分布は面内でナノスケール尺度の不均一性をもち、強いフェルミ準位ピンニングを引き起こすスポット状の領域「ピンニング・スポット」と、ピンニングが弱くバイアスにより電子蓄積層や反転電子層が形成され得るピンニング・フリー領域が共存すると考える。このモデルから期待されるMISアドミタンスのバイアス・周波数・温度依存性を定式化し、コンピュータを用い数値計算を行った。(2)化合物半導体およびsi ICLをMBE成長し、そのsi ICL一部をラジカル窒化したGaAsおよびInGaAsのSi ICL制御MIS試料を作製し、そのアドミタンスのバイアス・周波数・温度依存性を測定した。(3)Si ICLMIs試料について、バンド端フォトルミネセンス(PL)量子効率の励起光強度依存性を非接触測定し、その結果をポーランド・シレジアン工科大学物理学科のアダモヴィッチ教授の協力を得てコンピュータ解析し、マクロな界面準位密度(D_)...
    文部科学省, 萌芽研究, 北海道大学, Coinvestigator not use grants, Competitive research funding, 20656006
  • GaN-based Chemical Sensors and Their On-chip Integration Using Nanowire Networks
    Grants-in-Aid for Scientific Research(基盤研究(B))
    2006 - 2007
    Hideki HASEGAWA; 赤澤 正道; 池辺 将之
    This project investigates key technologies for realization of GaN-based high-sensitivity chemical sensors and their on-chip integration using nanowires. The main conclusions are as follows: (1) Interface models on Schottky barrier formation are surveyed, and key issues related to AlGaN/GaN Schottky barriers including Fermi level pinning, Schottky barrier height (SBH) and reverse leakage currents are discussed. The current transport is explained by the thin surface barrier (TSB) model. Leakage currents can be reduced by the oxygen gettering process. (2) Pd Schottky barrier hydrogen sensors f...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 18360002
  • 電界移動型量子ドットを用いた室温動作高速・超低消費電力単電子スイッチ素子の研究
    科学研究費補助金(萌芽研究)
    2006 - 2006
    長谷川 英機; 赤澤 正道
    量子デバイスの消費電力は極低温では小さいが、室温では電子エネルギーの熱的広がりによるスイッチ特性のだれにより増大する。本研究では、「量子ドットの空間的位置を電界で制御しトンネル確率を制御する」という原理にもとづく「電界移動型量子ドット単電子分岐スイッチ」について、その原理を確認することと、その効果を妨げる表面準位を低減することを目的として研究を推進し、次の成果を得た(1)3つのショットキ・ラップゲートにより、AlGaAs/GaAs量子細線T型分岐上に、量子ドットと3つのトンネル障壁を形成した「単電子分岐スイッチ」を試作し、その動作を測定した。その結果、低温で通常の単電子トンネル理論よりも急峻なスイッチ特性が得られた。しかしその急峻さは温度の上昇と共に急激に消失した。(2)デバイスの特性を量子ドットを円形近似した単純な解析モデルにもとづき解析して実験特性と比較した結果、ドットの電界移動によるトンネル確率の指数関数的変調が急峻なスイッチ特性を実現することが、確認された。また温度上昇による特性の劣化の主な理由は、低温では凍結している分岐スイッチの表面準位が、室温に近づくほど活性化し、ドットの電界移動を妨げることにあることが判明した。(3)その後の研究の大半は、「シリコン界面制御層(Si ICL)」を用いた代表者らの表面不活性化技術を、種々のファセット面をもつAlGaAs/GaAs量...
    文部科学省, 萌芽研究, 北海道大学, Coinvestigator not use grants, Competitive research funding, 18656089
  • Research on inter-ubiquitous-chip communication circuits using terahertz electromagnetic wave
    Grants-in-Aid for Scientific Research(基盤研究(B))
    2004 - 2006
    Eiichi SANO; 赤澤 正道; 山本 眞史; 尾辻 泰一
    The purpose of this research is to establish fundamental device, circuit, and measurement technologies for realizing compact, low-power communication circuits with carrier frequencies raging from a few hundreds GHz to one THz. The following results have been obtained. (1)A finite-difference time-domain (FDTD) electromagnetic simulator analyzing simultaneously active devices like resonant-tunneling diodes (RTDs) and high-electron-mobility transistors (HEMTs) has been developed. (2)An active integrated antenna (AIA) oscillator consisting of InP-based HEMTs and a slot antenna was designed usin...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 16360161
  • Research on a highly efficient semiconductor THz emitting source using a metal thin-film mesh
    Grants-in-Aid for Scientific Research(基盤研究(C))
    2004 - 2005
    Masamichi AKAZAWA; 佐野 栄一
    It was confirmed that a metal mesh having an appropriate structure exhibits a high transmittance as a filter in the THz region. Especially a filter with the thickness much smaller than the transmitted wavelength does not have the cutoff property resulting in a high transmittance even for the tilted incidence. According to the results of simulation and experiment, it was found that the surface plasmon-polariton (SPP) contributes the transmission property. Then there is possibility that the boundary condition at the semiconductor surface for the THz emission is modified by attaching a metal m...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(C), 北海道大学, Principal investigator, Competitive research funding, 16560288
  • カオス多重による超大容量光通信の研究
    科学研究費補助金(萌芽研究)
    2004 - 2005
    佐野 栄一; 赤澤 正道
    本研究は、複数の半導体レーザ(LD)で発現する互いに直交したカオス信号に情報を乗せ、それらを多重化することにより、通信容量を飛躍的に増大させる光通信方式の創出を目的とする。具体的には、複数のLDから構成される結合写像格子(CML:Coupled-Map Lattice)を送信部と受信部に配置し、送信CMLからの複数の「カオスチャネル」を一本の光ファイバ内に多重化し、送信CMLとカオス同期する受信CMLにおいて多重カオス信号を分離する光通信方式である。昨年度は、光電場レート方程式とキャリアレート方程式を数値計算することにより、CMLの振る舞いを詳細に検討し、LDの注入電流と光結合度を選ぶことにより、CMLの各LD出力を直交できること、送信CMLと受信CML問の相関はほぼδ_となると(ただし、iは送信CMLのi番目のLD、jは受信CMLのj番目のLDを示す)を明らかにした。さらに、2チャネル伝送システムをシミュレートし、1Gbit/sの伝送レートでの2チャネル伝送が可能であることを示した。しかしながら、これらの理論解析は伝送距離ゼロのいわゆるback-to-backの条件で行われていた。実際のシステムにおいては光ファイバの波長分散とカー効果により受信波形は送信波形と異なるため、送信CML.と受信CML間のカオス同期は保証されない。これまでの研究では、分散シフトファイバが仮...
    文部科学省, 萌芽研究, 北海道大学, Coinvestigator not use grants, Competitive research funding, 16656113
  • Surface/interface control of high-frequency and high-power transistors based on GaN materials
    Grants-in-Aid for Scientific Research(基盤研究(B))
    2002 - 2004
    Tamotsu HASHIZUME; 赤澤 正道; 葛西 誠也; 本久 順一
    The purpose of this research was to characterize and control surface/interface properties of GaN-based material systems such as AlGaN/GaN hetrostrcutures for the stability improvement of high-frequency and high-power transistors. The main results obtained are listed below :(1)Serious deterioration such as stoichiometry disorder and nitrogen deficiency (N deficiency) was found at the processed AlGaN surfaces. This resulted in formation of a localized deep donor level related to N vacancy (V_N), causing excess leakage currents at the AlGaN Schottky interface and serious drain current collapse...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 14350155
  • Single Electron Integrated Circuits Based on A BDD Architecture Utilizing Quantum Dots Controlled by Nano-Schottky Gates
    Grants-in-Aid for Scientific Research(基盤研究(A))
    2001 - 2003
    Hideki HASEGAWA; 赤澤 正道; 橋詰 保; 雨宮 好仁; 葛西 誠也
    The purpose of this research was to investigate a novel single electron integrated circuit based on a binary-decision diagram (BDD) architecture utilizing quantum dots controlled by nano-Schottky gates. Main results are listed below :(1)A novel "hexagonal BDD quantum circuit approach" for realization of quantum LSIs, in which the BDD architecture is implemented on hexagonal nanowire network in high dense, was proposed. Various logic subsystems and arithmetic logic units (ALUs) were successfully designed utilizing the novel circuit approach.(2)Elemental BDD devices (node devices) were realiz...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(A), 北海道大学, Coinvestigator not use grants, Competitive research funding, 13305020
  • Development of insulating system with low dielectric constant, high dielectric strength a-C:F film coated conductor prepared by plasma CVD as alternatives to SF_6
    Grants-in-Aid for Scientific Research(基盤研究(B))
    2001 - 2003
    Yosuke SAKAI; Bratescu A; 赤澤 正道; 菅原 広剛; 中島 昌俊; 須田 善行
    In order to reduce the usage of SFs insulation gas, which has high GWP (global warming potential), the present project proposed to use a-C:F film coated conductor prepared by RF plasma CVD method for insulation of electric power systems as alternatives of SF_6. This project was motivated because we had experienced very high deposition rates in RF plasma if per-fluorocarbon vapors were used. The main results are listed as follows.l. The deposition rate on Si and A1 substrates was > 100-200nm/min, which is a few tens times higher than those obtained by conventional CF_4 and C_2F_6 gases.2. Th...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 13555077
  • 可逆計算デバイスの実現に関する基礎的研究
    科学研究費補助金(奨励研究(A), 若手研究(B))
    2001 - 2002
    赤澤 正道
    「可逆計算デバイス」には、熱的な可逆性と論理的な可逆性が要求される。本研究では、単電子デバイスの準静的動作の極限(低周波極限)が、可逆動作となる可能性があることを示した。電子デバイスにおいても、完全な熱的可逆動作は熱力学の第2法則によって否定されるが、準静的動作により極めて可逆に近い動作を実現することは物理的に否定されるものではない。しかし、電子デバイスを準静的に駆動しても、個々のデバイスが閾値をもち、その閾値において急峻なエネルギー変化を伴う限り、消費電力の低減は制限を受ける。これは、たとえ、理想的な特性を持つ量子細線トランジスタを用いたとしても同じことである。ところが、適切に設計された単電子デバイスは、励起準位を介することなく基底状態のみで動作することが可能であり、量子極限近傍で急激なエネルギーの損失が起こらないように動作することができるので、準静的動作により消費電力を任意に小さくできる。したがって、適切に設計された単電子回路の準静的動作の低周波極限は、電源から供給されたエネルギーが電荷の回収とともに完全に電源に戻されるような充放電動作、すなわち可逆動作となる。集積回路用の極微細加工はすでに、寸法的にはメゾスコピック領域に入っており、単電子現象の利用さえも、不可能ではなくなってきている。このような動向の中で、本発見は大きな意義を持つ。すなわち、Fredkin-Toffol...
    文部科学省, 奨励研究(A), 若手研究(B), 北海道大学, Principal investigator, Competitive research funding, 13750294
  • ボルテックスを利用した機能回路の開拓
    科学研究費補助金(特定領域研究(A))
    1999 - 1999
    赤澤 正道
    ボルテックス輸送の性質を巧みに利用した、新たな回路アーキテクチャを見つけ出すことは、超伝導エレクトロニクスの発展を促進する鍵となる。研究代表者は、新規なデバイスである「ボルテックスBDDデバイス」を用いて高速な理論回路を構成する方法を見出した。BDDは二分決定グラフの略であり、ブール代数によらず、有向グラフを用いてディジタル関数を表現するための1方法であり、論理設計において多くのディジタル関数を完全かつ簡便に表現することができる。本研究では、BDDをそのまま回路化し、BDD回路システムとすることを考えた。BDD回路システム中において、論理出力値は、変数の組み合わせによって活性化されるパスを、情報担体が転送されることにより決められる。BDDノードデバイス(BDDデバイス)に要求される機能は入力変数にしたがって情報担体の転送される方向を切り替える、2分岐スイッチングである。本研究においては、分岐点の2つの枝において、ジョセフソン接合の超伝導―常電導遷移を用いてボルテックスの転送方向を切り替える方式のデバイスを提案した。提案したBDDデバイスを用いて構成される32ビット加算器および32ビット比較器についてシュミレーションを行った結果、両者とも正しく動作することが示され、加算器では高々350psの処理時間、比較器では高々750psの処理時間で計算が可能なことが示された。また、SBDD...
    文部科学省, 特定領域研究(A), 北海道大学, Principal investigator, Competitive research funding, 11129201
  • Single-electron device based on the majority logic.
    Grants-in-Aid for Scientific Research(基盤研究(B))
    1998 - 1999
    Yoshihito AMEMIYA; 〓 南健; 赤澤 正道; 陽 完治; 浅井 哲他
    In this project, we developed single-electron gate circuits based on the principle of the majority logic. The majority logic gate circuit proposed consists of a capacitor array for input summation and a single-electron inverter for threshold operation. It accepts an odd number of inputs and produces the corresponding output on the basis of the principle of majority decision; it produces an output of logic "1" if the majority of the inputs is 1 , and an output of "0" if the majority is 0. By combining the proposed majority gate circuits, various subsystems can be constructed with a smaller n...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 10450129
  • Implementation of Ultra Micro Boltzmann Machine Neuron
    Grants-in-Aid for Scientific Research(基盤研究(C))
    1997 - 1998
    Masamichi AKAZAWA; 呉 南健; 雨宮 好仁
    We have investigated ways of using a single-electron-tunneling (SET) circuit to solve problems in neural networks, and have obtained the following results :1) A simple circuit for a Boltzmann machine neuron : The circuit for the Boltzmann machine neuron that has a stochastic response is usually complicated. We found, however, that by using a single-electron-tunneling circuit, we can construct a compact neuron circuit in which the Coulomb blockade condition is adjusted appropriately, It can produce an output of a random 1-0 bit stream with the probability for an output of 1 controlled by an ...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(C), 北海道大学, Principal investigator, Competitive research funding, 09650375
  • "Fabrication of high-speed and low-power-consumption InP-based HEMT by novel interface control techniques"
    Grants-in-Aid for Scientific Research(基盤研究(B))
    1997 - 1998
    Tamotsu HASHIZUME; 関 昇平; 呉 南健; 赤澤 正道; 長谷川 英機; 藤倉 序章
    The purpose of this study is to fabricate a high-speed InAlAs/InGaAs HEMT with Schottky gate using in-situ electrochemical process and to fabricate an insulated-gate InAIAs/InGaAs HEMT with low-power consumption using ultrathin Si interface-control technique. The main results obtained are listed below :(1) A novel in-situ pulsed-mode electrochemical process enables us to produce good Schottky contacts on InP, InAlAs and lnGaAs with carrier transport properties according to the thermionic emission model.(2) A Ti/n-InP contact formed by sputtering showed good ohmic characteristics after rapid...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 09555092
  • High Speed InP Schottky Power Rectifier
    Grants-in-Aid for Scientific Research(基盤研究(B))
    1997 - 1998
    Nan-Jian WU; 石井 宏辰; 赤沢 正道; 雨宮 好仁; 安永 均
    The optimal structure of high speed InP Schottky power rectifier was designed. InP Schottky power rectifier was fabricated by Novel In-Situ Electrochemical process. Summary of the results is given as following.1) The rectification efficiency of InP Schottky power rectifier trades off the maximum operating frequency. Structure of the InP Schottky power rectifier was designed optimally. For example, to fabricate an InP Schottky power rectifier with a blocking voltage of 40V and efficiency of above 90%, the parameter of the InP epi-substrata must be designed as following. The thickness and don...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学->電気通信大学, Competitive research funding, 09555105
  • Single-electron devices based on the binary decision diagram.
    Grants-in-Aid for Scientific Research(基盤研究(B))
    1996 - 1997
    Yoshihito AMEMIYA; 呉 南健; 赤澤 正道
    We proposed a method of constructing singleelectron logic systems on the basis of the binary decision diagram. Following the guiding principle that we have proposed, we designed sample logic subsystems, an adder and a comparator, by combining singleelectron BDD devices. Matters that require attention in designing the subsystems were discussed. The operation of the designed subsystems was calculated by computer simulation. It was demonstrated that the designed subsystems successfully produce an output data flow in reponse to the input data flow through pipelined processing. The operation err...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 08455156
  • Cellular-Automaton Circuits Using Single-Electron-Tunneling Junctions
    Grants-in-Aid for Scientific Research(基盤研究(C))
    1996 - 1997
    Nan-Jian WU; 赤澤 正道; 雨宮 好仁
    We propose cellular automaton cicuits that use single-electron-tunneling cicuits (SET-CA). The unit cell consists of four intrinsic semiconductor islands and four single-electron-tunneling junctions. The dielectric constant of the intrinsic semiconductor is much larger than that of the junction insulator.The unit cell is charged with two single electrons. Polarization states of the two single electrons in the unit cell can be used to encode a binary signal. We designed various binary logic SET-CA circuits, and analyzed their operation by computer simulation. It was demonstrated that the SET...
    Ministry of Education, Culture, Sports, Science and Technology, 基盤研究(C), 北海道大学, Coinvestigator not use grants, Competitive research funding, 08650396
  • 超高密度多値メモリ集積回路の実現に関する基礎的研究
    科学研究費補助金(奨励研究(A))
    1996 - 1996
    赤澤 正道
    高々数個の電子を情報媒体とする極微細な「多値メモリ素子」を独自の設計思想で世界で初めて実現し、多値論理の情報処理システムに使用できる高速・高密度・低消費電力のメモリLSIに応用するための基礎的研究を行った。その結果、次のことがわかった。1)単電子トランジスタのトンネル接合を、方向性単電子トンネル接合におきかえると、多値メモリを構成できることをモンテカルロシミュレーションにより確認した。2)方向性単電子トンネル接合は、金属と誘電率の大きく異なる2種の絶縁体の組み合わせによって実現可能であることを理論的計算により予測した。3)実際の多値メモリデバイス構造は、TiあるいはTaの金属超薄膜をSTM/AFMにより微細加工することによって作製可能であることを実験により確認した。4)多値メモリセルは200MHzでの駆動が可能であり、また200nsecのデータ保持が可能であることが予測された。このとき、消費電力は1bit当り1pW程度になり、1Tbitの集積度でも1Wの消費電力で済むことになる。5)単電子の有無を電圧の情報に変換する入出力回路や、多値論理サブシステムの単電子回路による構成も可能であることをモンテカルロシミュレーションにより確認した。
    文部科学省, 奨励研究(A), 北海道大学, Principal investigator, Competitive research funding, 08750387
  • Control of surface states for III-V semiconductor quantum structures and its application to novel optical devices
    Grants-in-Aid for Scientific Research(一般研究(B), 基盤研究(B))
    1995 - 1996
    Hideki HASEGAWA; 赤沢 正道; 本久 順一; 橋詰 保
    The purpose of this study is to investigate the interaction mechanism between surface states and confined levels in III-V compound semiconductor quantum structures and to control the surface properties by use of ultrathin silicon interface control layr (SiICL) for fabrication of novel optical devices. The main results obtained are listed below :(1) It was found that the photoluminescence (PL) intensity from the near-surface quantum well (OW) with the surface-to-well distance of 5nm, was reduced by a factor of 1000 as compared with that from the reference QW located deeply inside. We reveale...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(B), 基盤研究(B), 北海道大学, Competitive research funding, 07455017
  • Fabrication of InP-based high-speed integrated circuits using MESFETs with high Schottky barrier height
    Grants-in-Aid for Scientific Research(試験研究(B), 基盤研究(B))
    1995 - 1996
    Tamotsu HASHIZUME; 関 昇平; 呉 南健; 赤沢 正道; 長谷川 英機
    The purpose of this study is to realize Schottky contacts with high barrier height to n-InP by a novel in-situ electrochemical process and to apply this Schottky gate technology to fabrication InP MESFETs and related high-speed integrated circuits and optoelectronic integrated circuits. The main results obtained are listed below :(1) A novel in-situ electrochemical process enables us to produce Pt/n-InP Schottky diodes with a barrier height of 0.86eV or higher and n-value of 1.1 or lower.(2) Capacitance-voltage measurements, Raman spectroscopy and X-ray photoelectron spectroscopy revealed t...
    Ministry of Education, Culture, Sports, Science and Technology, 試験研究(B), 基盤研究(B), 北海道大学, Competitive research funding, 07555093
  • "A study on novel quantum structures utilizing direct Schottky contacts to the two dimensional electon gas"
    Grants-in-Aid for Scientific Research(一般研究(C), 基盤研究(C))
    1995 - 1996
    Tamotsu HASHIZUME; 呉 南健; 赤沢 正道; 長谷川 英機
    The purpose of this study is to investigate the properties of Schottky/2DEG contacts and to realize novel quantum structures utilizing the Schottky/2DEG contacts as in-plane gates. The main results obtained are listed below :(1) We developed a novel technique to form a direct Schottky contact to the edge of 2DEG in AlGaAs/GaAs heterojunction by use of in-situ electrochemical process, and applied this technique to formation of in-plane-gate type quantum structures.(2) In-plane-gate type quantum wire transistors were successfully fabricated. Quantized conductance was observed up to 100K,indic...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(C), 基盤研究(C), 北海道大学, Competitive research funding, 07837001
  • Fabrication and Characterization of Self-organized Quantum Nano-structures.
    Grants-in-Aid for Scientific Research(一般研究(A))
    1994 - 1995
    Takashi FUKUI; 赤澤 正道; 本久 順一; 長谷川 英機
    We have fabricated AlGaAs/GaAs quantum dot structures using selective area metalorganic vapor phase epitaxy (MOVPE). First, GaAs pyramidal structures with four-fold symmetric {011} facet side walls are formed on SiN_x masked (001) GaAs with square openings. Once the pyramidal structures were completely formed, no growth occurs on the top and side walls of the pyramids. Furthermore, the shape and width of the top area observed by a scanning electron microscope (SEM) and an atomic force microscope (AFM) shows to be highly uniform. This indicates that self-limited growth mode occurs. Next, usi...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(A), 北海道大学, Coinvestigator not use grants, Competitive research funding, 06402037
  • Study on Supcr-High Efficicncy InGaAs/InP Solar Ccll With Controlled Surface
    Grants-in-Aid for Scientific Research(一般研究(C))
    1994 - 1995
    齋藤 俊也; 斉藤 俊也; 齋藤 俊也; Toshiya SAITOH; 澤田 孝幸; 赤澤 正道; 陽 完治
    Solar cells using InP and its related materials are drawing attention for sources of electricity of man-made satellites. However, the surface recombination velocity at InP surface is known to be larger than that at conventional Si solar cell surface. In this study, firstly, contactless and non-destructive measurements of surface state density distribution of InP surface and its related materials are carried out for the improvement of passivation technology. The measurement of surface recombination velocity under sunlight are done, for the first time, for various sunlight intensity using pho...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(C), 北海道大学, Coinvestigator not use grants, Competitive research funding, 06650345
  • InGaAs2次元電子ガスMISFETの試作
    科学研究費補助金(奨励研究(A))
    1994 - 1994
    赤澤 正道
    本研究は、新しい構造をもつ2次元電子ガスMISFETを実現するための基礎的研究である。年限内に得られた成果を以下に挙げる。(1)Si超薄膜による絶縁体(Si_3N_4あるいはSiO_2)-InGaAs界面の制御は、非常に薄い(100Å)InGaAs活性層上においても有効であることがわかり、2次元電子ガスの、MISゲートによる駆動にも成功した。(2)MISゲート電極下の逆HEMT構造のMBE成長条件の最適化を計り、低温成長スペ-サ層の挿入により2次元電子の移動度を、77Kにおいて5,000cm/v・secから40,000cm/v・secまで向上させた。(3)一般的にInGaAs系HEMTにおいて問題となっている、メサエッチングした側面でのゲート電極と2次元電子ガスとの接触に起因する、漏れ電流の問題を、弗化水素による表面処理とSi超薄膜形成とを組み合わせて、界面を制御して絶縁体を推積することにより回避することに成功した。年限内に、良好な特性を有する2次元電子ガスMISFETの実現には到達しなかった。これは、ソース・ドレイン電極のオーミック接触の抵抗値を下げる技術を開発できなかったためであるが、今後この点が解決されれば、本研究により得られた成果と合わせて、良好な特性を持つ新しい素子が実現すると考えられる。
    文部科学省, 奨励研究(A), 北海道大学, Principal investigator, Competitive research funding, 06750299
  • Characterization and Control of Interaction between Quantized Energy Levels and Surface/Interface States in Compound Semiconductor Quantum Structures.
    Grants-in-Aid for Scientific Research(一般研究(B))
    1993 - 1994
    Hideki HASEGAWA; 赤澤 正道; 澤田 孝幸
    The purpose of the research is to investigate an interaction between the quantized energy levels and the surface/interface states in compound semiconductor quantum structures, and to investigate the applicability of the novel silicon-intelayr based passivation technique to passivation of compound semiconductor quantum structures. The main results are summarized below.(1) It has been shown that the photoluminescence (PL) intensity from the near-surface AlGaAs/GaAs quantum wells (QWs) decreases exponentially with decreasing the thickness of the top AlGaAs barrier layr below 10nm, and that thi...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 05452181
  • Fabrication of Highly Functional MMICs Using Traveling Wave Interaction Mode and Static Magnetic Wave Mode
    Grants-in-Aid for Scientific Research(一般研究(C))
    1992 - 1993
    Masamichi AKAZAWA; 斉藤 俊也; 福井 孝志; 長谷川 英機
    The semiconductor carrier waves and their traveling wave interactions with the electromagnetic fields in InP and GaAs layrs using the metal-insulator-semiconductor (MIS)-type carrier confinement structure were studied. Traveling wave amplifier (TWA)-type devices were made and the admittance of the devices was measured. For the first time, the existence of carrier waves was observed from the drift velocity dependence of the admittance and two modes of interaction were observed from the frequency dependence of the drift velocity, which gave the reduction peaks of the conductance. To discuss t...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(C), 北海道大学, Principal investigator, Competitive research funding, 04805028
  • Fabrication and Characterization of Semiconductor Quantum Dots by Selective Area Grant
    Grants-in-Aid for Scientific Research(一般研究(B))
    1992 - 1993
    Takashi FUKUI; 赤沢 正道; 長谷川 英機; 本久 順一
    GaAs and AlGaAs micro-Pyramidal Structures having four-fold symetry facets (011) were fabricated using selective area MOVPE on (001) GaAs substrates partlally masked with a SiO_2. In order to study accurate growth rate, wider mask-patterned substrates were used. Low pressure horizontal MOVPE reactor was used. Source materials were TMGa, TEAI, quality of micro-pyramidal structures were characterized by cleaved cross section image of scanning electron microscope (SEM) and photoluminescence (PL) from quantum well. The main results are as follows : The growth rate enhances in selective are grow...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(B), 北海道大学, Competitive research funding, 04452165
  • A Novel Contactless and Nondestructive Measurement Method of Surface State Density on Semiconductor Free Surface, and Control of Their Surfaces
    Grants-in-Aid for Scientific Research(一般研究(B))
    1991 - 1992
    Hideki HASEGAWA; 飯塚 浩一; 赤沢 正道
    (1) A novel photoluminescence (PL)-based measurement method (PL Surface State Spectroscopy : PLS^3) for semiconductor surface state density, N_, was newly developed. It consists of detailed measurement of the band-edge photoluminescence efficiency as a function of the excitation intensity, and its rigorous analysis by computer. By this method, N_ distribution as well as the value of surface recombination velocity, S, can be determined in a contactless and nondestructive fashion. (2) The proposed PLS^3 technique was successfully applied for the first time for in-situ determination of...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(B), 北海道大学, Competitive research funding, 03452147
  • A new MIS Interface Control Technology for Fabrication of High Spatial Resolution InGaAs Change Coupled Devices for Imaging
    Grants-in-Aid for Scientific Research(試験研究(B))
    1991 - 1992
    Hideki HASEGAWA; 飯塚 浩一; 坪内 夏朗; 赤沢 正道
    For advanced image technologies including HDTVs, solid state imaging devices whose spatial resolution is much higher than today's standard is required. The spatial resolution of conventional Si CCDs is limited not by lithography, but by its indirect bandgap nature which makes the optical absorption layer inevitably thick, causing smearing of images due to carrier diffusion. This difficulty can be overcome by using a direct energy gap materials like InGaAs. However, compound semiconductor MIS interfaces generally possess high density of gap states which makes realization of MIS devices diffi...
    Ministry of Education, Culture, Sports, Science and Technology, 試験研究(B), 北海道大学, Competitive research funding, 03555056
  • Growth and Characterization of Diluted Magnetic III-V Compound Semiconductors
    Grants-in-Aid for Scientific Research(一般研究(B))
    1990 - 1991
    Hideo OHNO; 赤沢 正道; 飯塚 浩一; 長谷川 英機
    Molecular beam epitaxial (MBE) growth and electric and magnetic properties of diluted magnetic III-V semiconductors, especially (In, Mn) As, are studied. Following is a summary of the research results. Molecular Beam Epitaxial Growth : Maximum Mn concentration that can be incorporated into InAs lattice without having second phase (which is MnAs) is critically dependent on the growth temperature during MBE growth. At 300ﾟC, x (in In_<1-x>Mn_xAs) has to be<0.03 and the conduction is p-type whereas at 200ﾟC, x<0.25 and n-type.Characterization of Epitaxial layers : (1) Magnetism All n-type samp...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(B), 北海道大学, Competitive research funding, 02452142
  • New Waveguides for Microwave Monolithic Integrated Circuits Using Distributed Parameter Effects of Semiconductor Carriers
    Grants-in-Aid for Scientific Research(一般研究(B))
    1988 - 1989
    長谷川 英機; 長谷川 秀機; Hideki HASEGAWA; 大野 英男; 飯塚 浩一; 深井 一郎; 赤澤 正道
    The integration level of monolithic microwave integrated circuits (MMICs)is presently limited owing to large substrate area requirements for passive circuitry in spite of the advanced miniaturization of active semiconductor devices with fine-line lithography.In the present study, MIS (metal-insulator-semiconductor) and Schottky coplanar waveguides for application to MMICs are investigated theoretically and experimentally. They are formed on semi-insulating compound semiconductor substrates ( GaAs and InP) with epitaxial surface layers, and show remarkable slow-wave propagation due to distri...
    Ministry of Education, Culture, Sports, Science and Technology, 一般研究(B), 北海道大学, Coinvestigator not use grants, Competitive research funding, 63460115
■ Industrial Property Rights
  • 電界効果トランジスタおよびその製造方法
    Patent right, 橋詰 保; 赤澤 正道; 廣木 正伸
    特願2011-208741, 26 Sep. 2011